c05564c4d8
Android 13
237 lines
4 KiB
C
Executable file
237 lines
4 KiB
C
Executable file
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/of_device.h>
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#include <linux/kthread.h>
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#include <sspm_ipi.h>
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#include <sspm_ipi_pin.h>
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#include <linux/arm-smccc.h>
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#include <linux/soc/mediatek/mtk_sip_svc.h>
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#include "mtk_qos_ipi.h"
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#include "mtk_qos_sram.h"
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#include "mtk_qos_common.h"
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static const struct qos_ipi_cmd mt6761_qos_ipi_pin[] = {
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[QOS_IPI_QOS_ENABLE] = {
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.id = 0,
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.valid = true,
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},
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[QOS_IPI_QOS_BOUND] = {
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.id = 0x100,
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.valid = false,
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},
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[QOS_IPI_QOS_BOUND_ENABLE] = {
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.id = 0x100,
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.valid = false,
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},
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[QOS_IPI_QOS_BOUND_STRESS_ENABLE] = {
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.id = 0x100,
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.valid = false,
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},
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[QOS_IPI_SWPM_INIT] = {
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.id = 5,
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.valid = true,
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},
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[QOS_IPI_UPOWER_DATA_TRANSFER] = {
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.id = 6,
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.valid = true,
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},
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[QOS_IPI_UPOWER_DUMP_TABLE] = {
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.id = 7,
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.valid = true,
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},
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[QOS_IPI_GET_GPU_BW] = {
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.id = 8,
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.valid = true,
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},
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[QOS_IPI_SWPM_ENABLE] = {
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.id = 9,
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.valid = true,
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},
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[QOS_IPI_SMI_MET_MON] = {
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.id = 0x100,
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.valid = false,
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},
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[QOS_IPI_SETUP_GPU_INFO] = {
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.id = 0x100,
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.valid = false,
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},
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[QOS_IPI_SWPM_SET_UPDATE_CNT] = {
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.id = 0x100,
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.valid = false,
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},
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};
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static const struct qos_sram_addr mt6761_qos_sram_pin[] = {
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[QOS_DEBUG_0] = {
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.offset = 0x38,
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.valid = true,
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},
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[QOS_DEBUG_1] = {
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.offset = 0x3C,
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.valid = true,
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},
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[QOS_DEBUG_2] = {
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.offset = 0x40,
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.valid = true,
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},
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[QOS_DEBUG_3] = {
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.offset = 0x44,
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.valid = true,
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},
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[QOS_DEBUG_4] = {
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.offset = 0x48,
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.valid = true,
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},
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[MM_SMI_VENC] = {
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.offset = 0x100,
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.valid = false,
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},
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[MM_SMI_CAM] = {
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.offset = 0x100,
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.valid = false,
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},
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[MM_SMI_IMG] = {
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.offset = 0x100,
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.valid = false,
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},
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[MM_SMI_MDP] = {
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.offset = 0x100,
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.valid = false,
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},
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[MM_SMI_CLK] = {
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.offset = 0x100,
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.valid = false,
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},
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[MM_SMI_CLR] = {
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.offset = 0x100,
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.valid = false,
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},
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[MM_SMI_EXE] = {
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.offset = 0x100,
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.valid = false,
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},
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[MM_SMI_DUMP] = {
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.offset = 0x100,
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.valid = false,
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},
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[APU_CLK] = {
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.offset = 0x100,
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.valid = false,
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},
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[APU_BW_NORD] = {
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.offset = 0x100,
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.valid = false,
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},
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[DVFSRC_TIMESTAMP_OFFSET] = {
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.offset = 0x100,
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.valid = false,
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},
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[CM_STALL_RATIO_ID_0] = {
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.offset = 0x100,
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.valid = false,
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},
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[CM_STALL_RATIO_ID_1] = {
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.offset = 0x100,
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.valid = false,
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},
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[CM_STALL_RATIO_ID_2] = {
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.offset = 0x100,
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.valid = false,
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},
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[CM_STALL_RATIO_ID_3] = {
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.offset = 0x100,
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.valid = false,
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},
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[CM_STALL_RATIO_ID_4] = {
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.offset = 0x100,
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.valid = false,
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},
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[CM_STALL_RATIO_ID_5] = {
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.offset = 0x100,
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.valid = false,
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},
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[CM_STALL_RATIO_ID_6] = {
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.offset = 0x100,
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.valid = false,
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},
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[CM_STALL_RATIO_ID_7] = {
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.offset = 0x100,
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.valid = false,
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},
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[QOS_TOTAL_BW] = {
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.offset = 0x20,
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.valid = true,
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},
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};
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static const struct mtk_qos_soc mt6761_qos_data = {
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.ipi_pin = mt6761_qos_ipi_pin,
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.sram_pin = mt6761_qos_sram_pin,
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.qos_sspm_init = NULL,
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.qos_ipi_recv_handler = NULL,
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};
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static int mt6761_qos_probe(struct platform_device *pdev)
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{
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return mtk_qos_probe(pdev, &mt6761_qos_data);
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}
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static const struct of_device_id mtk_qos_of_match[] = {
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{
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.compatible = "mediatek,mt6761-qos",
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.data = &mt6761_qos_data,
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}, {
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.compatible = "mediatek,mt6765-qos",
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.data = &mt6761_qos_data,
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}, {
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/* sentinel */
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},
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};
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static int mt6761_qos_remove(struct platform_device *pdev)
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{
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return 0;
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}
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static struct platform_driver mt6761_qos_platdrv = {
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.probe = mt6761_qos_probe,
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.remove = mt6761_qos_remove,
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.driver = {
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.name = "mt6761-qos",
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.of_match_table = mtk_qos_of_match,
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},
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};
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static int __init mt6761_qos_init(void)
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{
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int ret = 0;
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ret = platform_driver_register(&mt6761_qos_platdrv);
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return ret;
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}
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late_initcall(mt6761_qos_init)
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static void __exit mt6761_qos_exit(void)
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{
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platform_driver_unregister(&mt6761_qos_platdrv);
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}
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module_exit(mt6761_qos_exit)
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