124 lines
4.3 KiB
C
Executable file
124 lines
4.3 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __SCP_REG_H
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#define __SCP_REG_H
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/*#define SCP_BASE (scpreg.cfg)*/
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#define SCP_AP_RESOURCE (scpreg.cfg + 0x0004)
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#define SCP_BUS_RESOURCE (scpreg.cfg + 0x0008)
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#define SCP_A_TO_HOST_REG (scpreg.cfg + 0x001C)
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#define SCP_IRQ_SCP2HOST (1 << 0)
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#define SCP_IRQ_WDT (1 << 8)
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#define SCP_TO_SPM_REG (scpreg.cfg + 0x0020)
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#define SCP_GIPC_IN_REG (scpreg.cfg + 0x0028)
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#define HOST_TO_SCP_A (1 << 0)
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#define HOST_TO_SCP_B (1 << 1)
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/* scp awake lock definition*/
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#define SCP_A_IPI_AWAKE_NUM (2)
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#define SCP_B_IPI_AWAKE_NUM (3)
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#define SCP_A_DEBUG_PC_REG (scpreg.cfg + 0x00B4)
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#define SCP_A_DEBUG_PSP_REG (scpreg.cfg + 0x00B0)
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#define SCP_A_DEBUG_LR_REG (scpreg.cfg + 0x00AC)
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#define SCP_A_DEBUG_SP_REG (scpreg.cfg + 0x00A8)
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#define SCP_A_WDT_REG (scpreg.cfg + 0x0084)
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#define SCP_A_GENERAL_REG0 (scpreg.cfg + 0x0050)
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#define SCP_A_GENERAL_REG1 (scpreg.cfg + 0x0054)
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#define SCP_A_GENERAL_REG2 (scpreg.cfg + 0x0058)
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/*EXPECTED_FREQ_REG*/
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#define SCP_A_GENERAL_REG3 (scpreg.cfg + 0x005C)
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#define EXPECTED_FREQ_REG (scpreg.cfg + 0x5C)
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/*CURRENT_FREQ_REG*/
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#define SCP_A_GENERAL_REG4 (scpreg.cfg + 0x0060)
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#define CURRENT_FREQ_REG (scpreg.cfg + 0x60)
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/*SCP_GPR_CM4_A_REBOOT*/
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#define SCP_A_GENERAL_REG5 (scpreg.cfg + 0x0064)
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#define SCP_GPR_CM4_A_REBOOT (scpreg.cfg + 0x64)
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#define CM4_A_READY_TO_REBOOT 0x34
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#define CM4_A_REBOOT_OK 0x1
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#define SCP_A_GENERAL_REG6 (scpreg.cfg + 0x0068)
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#define SCP_A_GENERAL_REG7 (scpreg.cfg + 0x006C)
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#define SCP_SEMAPHORE (scpreg.cfg + 0x90)
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#define SCP_SCP2SPM_VOL_LV (scpreg.cfg + 0x0094)
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#define SCP_SLP_PROTECT_CFG (scpreg.cfg + 0x00C8)
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#define SCP_WDT_SP (scpreg.cfg + 0x00B8)
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#define SCP_WDT_LR (scpreg.cfg + 0x00BC)
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#define SCP_WDT_PSP (scpreg.cfg + 0x00C0)
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#define SCP_WDT_PC (scpreg.cfg + 0x00C4)
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#define SCP_BUS_CTRL (scpreg.cfg + 0x00F0)
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#define dbg_irq_info_sel_shift 26
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#define dbg_irq_info_sel_mask (0x3 << 26)
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#define SCP_DEBUG_ADDR_S2R (scpreg.cfg + 0x00F4)
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#define SCP_DEBUG_ADDR_DMA (scpreg.cfg + 0x00F8)
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#define SCP_DEBUG_ADDR_SPI0 (scpreg.cfg + 0x00FC)
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#define SCP_DEBUG_ADDR_SPI1 (scpreg.cfg + 0x0100)
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#define SCP_DEBUG_ADDR_SPI2 (scpreg.cfg + 0x0104)
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#define SCP_DEBUG_BUS_STATUS (scpreg.cfg + 0x0110)
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#define SCP_CPU_SLEEP_STATUS (scpreg.cfg + 0x0114)
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#define SCP_A_DEEP_SLEEP_BIT (1)
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#define SCP_B_DEEP_SLEEP_BIT (3)
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#define SCP_SLEEP_STATUS_REG (scpreg.cfg + 0x0114)
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#define SCP_A_IS_SLEEP (1<<0)
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#define SCP_A_IS_DEEPSLEEP (1<<1)
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#define SCP_B_IS_SLEEP (1<<2)
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#define SCP_B_IS_DEEPSLEEP (1<<3)
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#define INFRA_CTRL_STATUS (scpreg.cfg + 0x011C)
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#define SCP_DEBUG_IRQ_INFO (scpreg.cfg + 0x0160)
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/* clk reg*/
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#define SCP_CLK_CTRL_BASE (scpreg.clkctrl)
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#define SCP_CLK_SW_SEL (scpreg.clkctrl)
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#define SCP_CLK_ENABLE (scpreg.clkctrl + 0x0004)
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#define SCP_A_SLEEP_DEBUG_REG (scpreg.clkctrl + 0x0028)
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#define SCP_SRAM_PDN (scpreg.clkctrl + 0x002C)
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#define SCP_CLK_HIGH_CORE_CG (scpreg.clkctrl + 0x005C)
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#define SCP_CLK_CTRL_L1_SRAM_PD (scpreg.clkctrl + 0x0080)
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#define SCP_CLK_CTRL_TCM_TAIL_SRAM_PD (scpreg.clkctrl + 0x0094)
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/* SCP INTC register*/
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#define SCP_INTC_IRQ_STATUS (scpreg.cfg + 0x2000)
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#define SCP_INTC_IRQ_ENABLE (scpreg.cfg + 0x2004)
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#define SCP_INTC_IRQ_SLEEP (scpreg.cfg + 0x200C)
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#define SCP_INTC_IRQ_STATUS_MSB (scpreg.cfg + 0x2080)
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#define SCP_INTC_IRQ_ENABLE_MSB (scpreg.cfg + 0x2084)
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#define SCP_INTC_IRQ_SLEEP_MSB (scpreg.cfg + 0x208C)
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/* SCP System Reset */
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#define MODULE_RESET_SET (scpreg.scpsys + 0x0140)
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#define MODULE_RESET_CLR (scpreg.scpsys + 0x0144)
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#define MODULE_RESET_STATUS (scpreg.scpsys + 0x0148)
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#define SCP_RESET_BIT (1 << 3)
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#define SCP_SEC_RESET_BIT (1 << 10)
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/* INFRA Sleep Protect */
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#define INFRA_SLP_PROT_SET (scpreg.scpsys + 0x220)
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#define INFRA_SLP_PROT_STAT (scpreg.scpsys + 0x224)
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#define SCP_TO_INFRA_BIT (1 << 30)
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#define SCP_TO_AUDIO_BIT (1 << 31)
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/* INFRA_IRQ */
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#define INFRA_IRQ_SET (scpreg.scpsys + 0x0B14)
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#define AP_AWAKE_LOCK (0)
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#define AP_AWAKE_UNLOCK (1)
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#define CONNSYS_AWAKE_LOCK (2)
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#define CONNSYS_AWAKE_UNLOCK (3)
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#define INFRA_IRQ_CLEAR (scpreg.scpsys + 0x0B18)
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#define SCP_SYS_INFRA_MON (scpreg.scpsys + 0x0D50)
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#endif
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