275 lines
9.1 KiB
C
Executable file
275 lines
9.1 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MMDVFS_CONFIG_MT6739_H__
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#define __MMDVFS_CONFIG_MT6739_H__
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#include "mmdvfs_config_util.h"
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#ifdef VCORE_READY
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#include "mtk_vcorefs_manager.h"
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#else
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#define OPP_0 0
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#define OPP_1 1
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#define OPP_2 2
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#define OPP_3 3
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#endif
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/* Part I MMSVFS HW Configuration (OPP)*/
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/* Define the number of mmdvfs, vcore and mm clks opps */
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#define MT6739_MMDVFS_OPP_MAX 4
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#define MT6739_MMDVFS_CLK_OPP_MAX 4
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#define MT6739_MMDVFS_VCORE_OPP_MAX 4
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/* CLK source configuration */
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/* CLK source IDs */
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/* Define the internal index of each CLK source*/
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#define MT6739_MMDVFS_CLK_TOP_SYSPLL2_D2 0
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#define MT6739_MMDVFS_CLK_TOP_VENCPLL_CK 1
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#define MT6739_CLK_SOURCE_NUM 2
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/* CLK Source definiation */
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/* Define the clk source description */
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struct mmdvfs_clk_source_desc mt6739_clk_sources[MT6739_CLK_SOURCE_NUM] = {
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{NULL, "mmdvfs_clk_top_syspll2_d2", 182},
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{NULL, "mmdvfs_clk_top_vencpll_ck", 300},
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};
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/*
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* B. CLK Change adaption configurtion
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* B.1 Define the clk change method and data of each MM CLK step
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* Field decscription:
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* 1. config_method:
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* a. MMDVFS_CLK_CONFIG_BY_MUX
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* b. MMDVFS_CLK_CONFIG_PLL
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* c. MMDVFS_CLK_CONFIG_NONE
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* 2. pll_id: PLL ID, please set -1 if PLL hopping is not used
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* 3. clk mux desc {hanlde, name}, plz set -1
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* and it will be initialized by driver automaticlly
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* 4. total step: the number of the steps supported by this sub sys
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* 5. hopping dss of each steps: please set -1 if it is not used
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* 6. clk sources id of each steps: please set -1 if it is not used
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*/
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struct mmdvfs_clk_hw_map mt6739_mmdvfs_clk_hw_map[MMDVFS_CLK_MUX_NUM] = {
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{ MMDVFS_CLK_CONFIG_NONE,
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{ NULL, "MMDVFS_CLK_MUX_TOP_SMI0_2X_SEL"}, -1, 2,
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{-1, -1},
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{-1, -1}
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},
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{ MMDVFS_CLK_CONFIG_NONE,
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{ NULL, "MMDVFS_CLK_TOP_MMPLL_CK"}, -1, 2,
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{-1, -1},
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{MT6739_MMDVFS_CLK_TOP_VENCPLL_CK,
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MT6739_MMDVFS_CLK_TOP_SYSPLL2_D2}
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},
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{ MMDVFS_CLK_CONFIG_NONE,
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{ NULL, "MMDVFS_CLK_MUX_TOP_CAM_SEL"}, -1, 2,
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{-1, -1},
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{-1, -1}
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},
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{ MMDVFS_CLK_CONFIG_NONE,
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{ NULL, "MMDVFS_CLK_MUX_TOP_IMG_SEL"}, -1, 2,
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{-1, -1},
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{-1, -1}
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},
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{ MMDVFS_CLK_CONFIG_NONE,
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{ NULL, "MMDVFS_CLK_MUX_TOP_VENC_SEL"}, -1, 2,
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{-1, -1},
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{-1, -1}
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},
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{ MMDVFS_CLK_CONFIG_NONE,
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{ NULL, "MMDVFS_CLK_MUX_TOP_VDEC_SEL"}, -1, 2,
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{-1, -1},
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{-1, -1}
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},
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{ MMDVFS_CLK_CONFIG_NONE,
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{ NULL, "MMDVFS_CLK_MUX_TOP_MJC_SEL"}, -1, 2,
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{-1, -1},
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{-1, -1}
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},
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{ MMDVFS_CLK_CONFIG_NONE,
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{ NULL, "MMDVFS_CLK_MUX_TOP_VPU_IF_SEL"}, -1, 2,
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{-1, -1},
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{-1, -1}
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},
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{ MMDVFS_CLK_CONFIG_NONE,
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{ NULL, "MMDVFS_CLK_MUX_TOP_VPU_IF_SEL"}, -1, 2,
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{-1, -1},
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{-1, -1}
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},
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{ MMDVFS_CLK_CONFIG_NONE,
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{ NULL, "MMDVFS_CLK_MUX_TOP_VPU_SEL"}, -1, 2,
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{-1, -1},
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{-1, -1}
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}
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};
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/* Part II MMDVFS Scenario's Step Confuguration */
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#define MT6739_MMDVFS_SENSOR_MIN (7900000)
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/* A.1 [LP4 2-ch] Scenarios of each MM DVFS Step (force kicker) */
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/* OPP 0 scenarios */
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#define MT6739_MMDVFS_OPP0_NUM 11
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struct mmdvfs_profile mt6739_mmdvfs_opp0_profiles[MT6739_MMDVFS_OPP0_NUM] = {
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{"ICFP", SMI_BWC_SCEN_ICFP, {0, 0, 0}, {0, 0, 0 } },
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{"Full Sensor Preview (ZSD)", SMI_BWC_SCEN_CAM_PV,
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{MT6739_MMDVFS_SENSOR_MIN, 0, 0}, {0, 0, 0 } },
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{"Full Sensor Capture (ZSD)", SMI_BWC_SCEN_CAM_CP,
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{MT6739_MMDVFS_SENSOR_MIN, 0, 0}, {0, 0, 0 } },
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{"Full Sensor Camera Recording", SMI_BWC_SCEN_VR,
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{MT6739_MMDVFS_SENSOR_MIN, 0, 0}, {0, 0, 0 } },
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{"VSS", SMI_BWC_SCEN_VSS,
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{MT6739_MMDVFS_SENSOR_MIN, 0, 0}, {0, 0, 0 } },
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{"PIP Feature Preview", SMI_BWC_SCEN_CAM_PV,
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{0, MMDVFS_CAMERA_MODE_FLAG_PIP, 0}, {0, 0, 0 } },
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{"PIP Feature Capture", SMI_BWC_SCEN_CAM_CP,
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{0, MMDVFS_CAMERA_MODE_FLAG_PIP, 0}, {0, 0, 0 } },
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{"PIP Feature Recording", SMI_BWC_SCEN_VR,
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{0, MMDVFS_CAMERA_MODE_FLAG_PIP, 0}, {0, 0, 0 } },
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{"FHD VR/ VSS (VENC)", SMI_BWC_SCEN_VENC,
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{0, 0, 0}, {1920, 1080, 0} },
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{"High resolution video playback", SMI_BWC_SCEN_VP_HIGH_RESOLUTION,
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{0, 0, 0}, {0, 0, 0 } },
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{"WFD", SMI_BWC_SCEN_WFD, {0, 0, 0}, {0, 0, 0 } },
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};
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/* OPP 1 scenarios */
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#define MT6739_MMDVFS_OPP1_NUM 0
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struct mmdvfs_profile mt6739_mmdvfs_opp1_profiles[MT6739_MMDVFS_OPP1_NUM] = {
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};
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/* OPP 2 scenarios */
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#define MT6739_MMDVFS_OPP2_NUM 0
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struct mmdvfs_profile mt6739_mmdvfs_opp2_profiles[MT6739_MMDVFS_OPP2_NUM] = {
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};
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/* OPP 3 scenarios */
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#define MT6739_MMDVFS_OPP3_NUM 19
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struct mmdvfs_profile mt6739_mmdvfs_opp3_profiles[MT6739_MMDVFS_OPP3_NUM] = {
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{"SMVR", SMI_BWC_SCEN_VR_SLOW, {0, 0, 0}, {0, 0, 0 } },
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{"EIS Feature Recording", SMI_BWC_SCEN_VR,
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{0, MMDVFS_CAMERA_MODE_FLAG_EIS_2_0, 0}, {0, 0, 0 } },
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{"Camera Preview", SMI_BWC_SCEN_CAM_PV, {0, 0, 0}, {0, 0, 0 } },
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{"Camera Capture", SMI_BWC_SCEN_CAM_CP, {0, 0, 0}, {0, 0, 0 } },
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{"Camera Recording", SMI_BWC_SCEN_VR, {0, 0, 0}, {0, 0, 0 } },
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{"VSS", SMI_BWC_SCEN_VSS, {0, 0, 0}, {0, 0, 0 } },
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{"VENC", SMI_BWC_SCEN_VENC, {0, 0, 0}, {0, 0, 0} },
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{"MHL", MMDVFS_SCEN_MHL, {0, 0, 0}, {0, 0, 0 } },
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{"High frame rate video playback", SMI_BWC_SCEN_VP_HIGH_FPS,
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{0, 0, 0}, {0, 0, 0 } },
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{"vFB Feature Preview", SMI_BWC_SCEN_CAM_PV,
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{0, MMDVFS_CAMERA_MODE_FLAG_VFB, 0}, {0, 0, 0 } },
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{"vFB Feature Capture", SMI_BWC_SCEN_CAM_CP,
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{0, MMDVFS_CAMERA_MODE_FLAG_VFB, 0}, {0, 0, 0 } },
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{"vFB Feature Recording", SMI_BWC_SCEN_VR,
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{0, MMDVFS_CAMERA_MODE_FLAG_VFB, 0}, {0, 0, 0 } },
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{"Stereo Feature Preview", SMI_BWC_SCEN_CAM_PV,
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{0, MMDVFS_CAMERA_MODE_FLAG_STEREO, 0}, {0, 0, 0 } },
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{"Stereo Feature Capture", SMI_BWC_SCEN_CAM_CP,
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{0, MMDVFS_CAMERA_MODE_FLAG_STEREO, 0}, {0, 0, 0 } },
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{"Stereo Feature Recording", SMI_BWC_SCEN_VR,
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{0, MMDVFS_CAMERA_MODE_FLAG_STEREO, 0}, {0, 0, 0 } },
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{"Dual zoom preview", SMI_BWC_SCEN_CAM_PV,
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{0, MMDVFS_CAMERA_MODE_FLAG_DUAL_ZOOM, 0}, {0, 0, 0 } },
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{"Dual zoom preview (reserved)", SMI_BWC_SCEN_CAM_CP,
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{0, MMDVFS_CAMERA_MODE_FLAG_DUAL_ZOOM, 0}, {0, 0, 0 } },
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{"Dual zoom preview (reserved)", SMI_BWC_SCEN_VR,
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{0, MMDVFS_CAMERA_MODE_FLAG_DUAL_ZOOM, 0}, {0, 0, 0 } },
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{"EIS 4K Feature Recording", SMI_BWC_SCEN_VR,
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{MT6739_MMDVFS_SENSOR_MIN,
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MMDVFS_CAMERA_MODE_FLAG_EIS_2_0, 0},
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{0, 0, 0 } },
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};
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/* Defined the smi scenarios whose DVFS is controlled by low-level driver */
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/* directly, not by BWC scenario change event */
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#define MT6739_MMDVFS_SMI_USER_CONTROL_SCEN_MASK (1 << SMI_BWC_SCEN_VP)
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/* Part III Scenario and MMSVFS HW configuration mapping */
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/* 1. For a single mmdvfs step's profiles and hardware configuration */
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struct mmdvfs_step_profile mt6739_step_profile[MT6739_MMDVFS_OPP_MAX] = {
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{0, mt6739_mmdvfs_opp0_profiles, MT6739_MMDVFS_OPP0_NUM,
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{OPP_0,
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{MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0,
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MMDVFS_MMCLK_OPP0, MMDVFS_MMCLK_OPP0}, MMDVFS_CLK_MUX_NUM
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}
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},
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{1, mt6739_mmdvfs_opp1_profiles, MT6739_MMDVFS_OPP1_NUM,
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{OPP_1,
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{MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1}, MMDVFS_CLK_MUX_NUM
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}
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},
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{2, mt6739_mmdvfs_opp2_profiles, MT6739_MMDVFS_OPP2_NUM,
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{OPP_2,
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{MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1}, MMDVFS_CLK_MUX_NUM
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}
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},
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{3, mt6739_mmdvfs_opp3_profiles, MT6739_MMDVFS_OPP3_NUM,
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{OPP_3,
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{MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1,
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MMDVFS_MMCLK_OPP1, MMDVFS_MMCLK_OPP1}, MMDVFS_CLK_MUX_NUM
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}
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},
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};
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/* Part III Scenario and MMSVFS HW configuration mapping */
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#define MT6739_MMDVFS_VOLTAGE_LOW_OPP 3
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#define MT6739_MMDVFS_VOLTAGE_HIGH_OPP 0
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#define MT6739_MMDVFS_VOLTAGE_DEFAULT_STEP_OPP -1
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#define MT6739_MMDVFS_VOLTAGE_LOW_LOW_OPP 3
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int mt6739_mmdvfs_legacy_step_to_opp[MMDVFS_VOLTAGE_COUNT] = {
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MT6739_MMDVFS_VOLTAGE_LOW_OPP,
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MT6739_MMDVFS_VOLTAGE_HIGH_OPP,
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MT6739_MMDVFS_VOLTAGE_DEFAULT_STEP_OPP,
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MT6739_MMDVFS_VOLTAGE_LOW_LOW_OPP
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};
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#define MT6739_MMCLK_OPP0_LEGACY_STEP MMSYS_CLK_HIGH
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#define MT6739_MMCLK_OPP1_LEGACY_STEP MMSYS_CLK_LOW
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/* MMCLK_OPP3 and OPP2 is not used in this configuration */
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#define MT6739_MMCLK_OPP2_LEGACY_STEP MMSYS_CLK_LOW
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#define MT6739_MMCLK_OPP3_LEGACY_STEP MMSYS_CLK_LOW
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int mt6739_mmdvfs_mmclk_opp_to_legacy_mmclk_step[MT6739_MMDVFS_OPP_MAX] = {
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MT6739_MMCLK_OPP0_LEGACY_STEP, MT6739_MMCLK_OPP1_LEGACY_STEP,
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MT6739_MMCLK_OPP2_LEGACY_STEP, MT6739_MMCLK_OPP3_LEGACY_STEP
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};
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/* Part IV VPU association */
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/* There is no VPU DVFS in MT6739 */
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/* Part V ISP DVFS configuration */
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#define MMDVFS_ISP_THRESHOLD_NUM 2
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int mt6739_mmdvs_isp_threshold_setting[MMDVFS_ISP_THRESHOLD_NUM] = {300, 182};
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int mt6739_mmdvs_isp_threshold_opp[MMDVFS_ISP_THRESHOLD_NUM] = {
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MMDVFS_FINE_STEP_OPP0, MMDVFS_FINE_STEP_OPP3};
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struct mmdvfs_threshold_setting mt6739_mmdvfs_threshold[MMDVFS_PMQOS_NUM] = {
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{ MMDVFS_PM_QOS_SUB_SYS_CAMERA, mt6739_mmdvs_isp_threshold_setting,
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mt6739_mmdvs_isp_threshold_opp,
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MMDVFS_ISP_THRESHOLD_NUM, MMDVFS_PMQOS_ISP},
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};
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#endif /* __MMDVFS_CONFIG_MT6739_H__ */
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