179 lines
6 KiB
C
Executable file
179 lines
6 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __SMI_CONF_H__
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#define __SMI_CONF_H__
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#include <soc/mediatek/smi.h>
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#include "smi_hw.h"
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#include "../smi_reg.h"
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#include "../smi_conf_dbg.h"
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#define SMI_SCEN_NUM 3
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#define SMI_ESL_INIT 0
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#define SMI_ESL_VPWFD (SMI_ESL_INIT)
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#define SMI_ESL_ICFP 1
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#define SMI_ESL_VR4K (SMI_ESL_ICFP)
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#define SMI_ESL_WFD 2
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static u32 smi_scen_map[SMI_BWC_SCEN_CNT] = {
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SMI_ESL_INIT, SMI_ESL_INIT, SMI_ESL_INIT,
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SMI_ESL_INIT, SMI_ESL_INIT, SMI_ESL_INIT,
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SMI_ESL_WFD, SMI_ESL_VPWFD, SMI_ESL_VPWFD,
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SMI_ESL_VPWFD, SMI_ESL_VPWFD,
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SMI_ESL_VR4K, SMI_ESL_VR4K, SMI_ESL_VR4K, SMI_ESL_VR4K,
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SMI_ESL_ICFP, SMI_ESL_ICFP, SMI_ESL_ICFP, SMI_ESL_INIT
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};
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static u32 smi_larb_cmd_gp_en_port[SMI_LARB_NUM][2] = {
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{0, 3}, {0, 0}, {0, 0},
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};
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static u32 smi_larb_bw_thrt_en_port[SMI_LARB_NUM][2] = { /* non-HRT */
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{0, 0}, {0, 0}, {0, 0},
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};
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/* conf */
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#define SMI_COMM_CONF_NUM 13
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struct mtk_smi_pair smi_comm_conf_pair[SMI_COMM_CONF_NUM] = {
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{SMI_L1LEN, 0xb}, {SMI_WRR_REG0, 0x6186186}, {SMI_WRR_REG1, 0x6186},
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{SMI_Mx_RWULTRA_WRRy(1, 0, 0), 0x6186186},
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{SMI_Mx_RWULTRA_WRRy(1, 0, 1), 0x6186},
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{SMI_Mx_RWULTRA_WRRy(1, 1, 0), 0x6186186},
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{SMI_Mx_RWULTRA_WRRy(1, 1, 1), 0x6186},
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{SMI_Mx_RWULTRA_WRRy(2, 0, 0), 0x6186186},
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{SMI_Mx_RWULTRA_WRRy(2, 0, 1), 0x6186},
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{SMI_Mx_RWULTRA_WRRy(2, 1, 0), 0x6186186},
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{SMI_Mx_RWULTRA_WRRy(2, 1, 1), 0x6186},
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{SMI_DCM, 0x4f1}, {SMI_DUMMY, 0x1},
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};
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#define SMI_LARB0_CONF_NUM 4
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struct mtk_smi_pair smi_larb0_conf_pair[SMI_LARB0_CONF_NUM] = {
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{SMI_LARB_SW_FLAG, 0x1},
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{SMI_LARB_WRR_PORT(0), 0x5}, {SMI_LARB_WRR_PORT(1), 0x5},
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{SMI_LARB_WRR_PORT(2), 0x5},
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};
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#define SMI_LARB1_CONF_NUM 1
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struct mtk_smi_pair smi_larb1_conf_pair[SMI_LARB1_CONF_NUM] = {
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{SMI_LARB_SW_FLAG, 0x1},
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};
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u32 smi_conf_pair_num[SMI_LARB_NUM + 1] = {
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SMI_LARB0_CONF_NUM, SMI_LARB1_CONF_NUM, SMI_LARB1_CONF_NUM,
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SMI_COMM_CONF_NUM,
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};
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struct mtk_smi_pair *smi_conf_pair[SMI_LARB_NUM + 1] = {
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smi_larb0_conf_pair, smi_larb1_conf_pair, smi_larb1_conf_pair,
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smi_comm_conf_pair,
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};
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/* scen: INIT */
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struct mtk_smi_pair smi_comm_init_pair[SMI_LARB_NUM] = {
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{SMI_L1ARB(0), 0x12f6}, {SMI_L1ARB(1), 0x1000}, {SMI_L1ARB(2), 0x1000},
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};
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struct mtk_smi_pair smi_larb0_init_pair[SMI_LARB0_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x1f}, {SMI_LARB_OSTDL_PORT(1), 0x1f},
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{SMI_LARB_OSTDL_PORT(2), 0x1f}, {SMI_LARB_OSTDL_PORT(3), 0x2},
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{SMI_LARB_OSTDL_PORT(4), 0x1}, {SMI_LARB_OSTDL_PORT(5), 0x1},
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{SMI_LARB_OSTDL_PORT(6), 0x5},
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};
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struct mtk_smi_pair smi_larb1_init_pair[SMI_LARB1_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x3}, {SMI_LARB_OSTDL_PORT(1), 0x1},
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{SMI_LARB_OSTDL_PORT(2), 0x2}, {SMI_LARB_OSTDL_PORT(3), 0x1},
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{SMI_LARB_OSTDL_PORT(4), 0x1}, {SMI_LARB_OSTDL_PORT(5), 0x3},
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{SMI_LARB_OSTDL_PORT(6), 0x2}, {SMI_LARB_OSTDL_PORT(7), 0x1},
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{SMI_LARB_OSTDL_PORT(8), 0x1}, {SMI_LARB_OSTDL_PORT(9), 0x1},
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{SMI_LARB_OSTDL_PORT(10), 0x5},
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};
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struct mtk_smi_pair smi_larb2_init_pair[SMI_LARB2_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0xc}, {SMI_LARB_OSTDL_PORT(1), 0x6},
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{SMI_LARB_OSTDL_PORT(2), 0x2}, {SMI_LARB_OSTDL_PORT(3), 0x2},
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{SMI_LARB_OSTDL_PORT(4), 0x2}, {SMI_LARB_OSTDL_PORT(5), 0x2},
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{SMI_LARB_OSTDL_PORT(6), 0x2}, {SMI_LARB_OSTDL_PORT(7), 0x2},
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{SMI_LARB_OSTDL_PORT(8), 0x4}, {SMI_LARB_OSTDL_PORT(9), 0x3},
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{SMI_LARB_OSTDL_PORT(10), 0x1},
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};
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/* scen: WFD */
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struct mtk_smi_pair smi_larb0_wfd_pair[SMI_LARB0_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x1}, {SMI_LARB_OSTDL_PORT(1), 0x1f},
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{SMI_LARB_OSTDL_PORT(2), 0x1f}, {SMI_LARB_OSTDL_PORT(3), 0x2},
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{SMI_LARB_OSTDL_PORT(4), 0x1}, {SMI_LARB_OSTDL_PORT(5), 0x1},
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{SMI_LARB_OSTDL_PORT(6), 0x5},
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};
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/* {SMI_LARB_OSTDL_PORT(0), 0x1f}, */
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/* scen: ICFP */
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struct mtk_smi_pair smi_comm_icfp_pair[SMI_LARB_NUM] = {
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{SMI_L1ARB(0), 0x119a}, {SMI_L1ARB(1), 0x118f}, {SMI_L1ARB(2), 0x1250},
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};
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struct mtk_smi_pair smi_larb0_icfp_pair[SMI_LARB0_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x1f}, {SMI_LARB_OSTDL_PORT(1), 0x1f},
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{SMI_LARB_OSTDL_PORT(2), 0x1f}, {SMI_LARB_OSTDL_PORT(3), 0xe},
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{SMI_LARB_OSTDL_PORT(4), 0x1}, {SMI_LARB_OSTDL_PORT(5), 0x1},
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{SMI_LARB_OSTDL_PORT(6), 0x7},
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};
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/* {SMI_LARB_OSTDL_PORT(3), 0x2}, {SMI_LARB_OSTDL_PORT(6), 0x5}, */
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struct mtk_smi_pair smi_larb1_icfp_pair[SMI_LARB1_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x1}, {SMI_LARB_OSTDL_PORT(1), 0x1},
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{SMI_LARB_OSTDL_PORT(2), 0x1}, {SMI_LARB_OSTDL_PORT(3), 0x1},
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{SMI_LARB_OSTDL_PORT(4), 0x1}, {SMI_LARB_OSTDL_PORT(5), 0x1},
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{SMI_LARB_OSTDL_PORT(6), 0x1}, {SMI_LARB_OSTDL_PORT(7), 0x1},
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{SMI_LARB_OSTDL_PORT(8), 0x1}, {SMI_LARB_OSTDL_PORT(9), 0x1},
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{SMI_LARB_OSTDL_PORT(10), 0x4},
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};
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/* {SMI_LARB_OSTDL_PORT(0), 0x3}, {SMI_LARB_OSTDL_PORT(2), 0x2},
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* {SMI_LARB_OSTDL_PORT(5), 0x3}, {SMI_LARB_OSTDL_PORT(6), 0x2},
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* {SMI_LARB_OSTDL_PORT(10), 0x5},
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*/
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struct mtk_smi_pair smi_larb2_icfp_pair[SMI_LARB2_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0xa}, {SMI_LARB_OSTDL_PORT(1), 0x4},
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{SMI_LARB_OSTDL_PORT(2), 0x2}, {SMI_LARB_OSTDL_PORT(3), 0x2},
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{SMI_LARB_OSTDL_PORT(4), 0x2}, {SMI_LARB_OSTDL_PORT(5), 0x2},
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{SMI_LARB_OSTDL_PORT(6), 0x2}, {SMI_LARB_OSTDL_PORT(7), 0x2},
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{SMI_LARB_OSTDL_PORT(8), 0x4}, {SMI_LARB_OSTDL_PORT(9), 0x2},
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{SMI_LARB_OSTDL_PORT(10), 0x1},
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};
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/* {SMI_LARB_OSTDL_PORT(0), 0xc}, {SMI_LARB_OSTDL_PORT(1), 0x6},
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* {SMI_LARB_OSTDL_PORT(9), 0x3},
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*/
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/* scen: ALL */
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struct mtk_smi_pair *smi_comm_scen_pair[SMI_SCEN_NUM] = {
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smi_comm_init_pair, smi_comm_icfp_pair, smi_comm_icfp_pair,
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};
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struct mtk_smi_pair *smi_larb0_scen_pair[SMI_SCEN_NUM] = {
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smi_larb0_init_pair, smi_larb0_icfp_pair, smi_larb0_wfd_pair,
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};
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struct mtk_smi_pair *smi_larb1_scen_pair[SMI_SCEN_NUM] = {
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smi_larb1_init_pair, smi_larb1_icfp_pair, smi_larb1_icfp_pair,
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};
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struct mtk_smi_pair *smi_larb2_scen_pair[SMI_SCEN_NUM] = {
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smi_larb2_init_pair, smi_larb2_icfp_pair, smi_larb2_icfp_pair,
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};
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u32 smi_scen_pair_num[SMI_LARB_NUM + 1] = {
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SMI_LARB0_PORT_NUM, SMI_LARB1_PORT_NUM, SMI_LARB2_PORT_NUM,
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SMI_LARB_NUM,
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};
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struct mtk_smi_pair **smi_scen_pair[SMI_LARB_NUM + 1] = {
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smi_larb0_scen_pair, smi_larb1_scen_pair, smi_larb2_scen_pair,
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smi_comm_scen_pair,
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};
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#endif
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