495 lines
14 KiB
C
Executable file
495 lines
14 KiB
C
Executable file
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifdef pr_fmt
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#undef pr_fmt
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#endif
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#define pr_fmt(fmt) "["KBUILD_MODNAME"]" fmt
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include "mtk_sd.h"
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#include <mmc/core/core.h>
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#include <mmc/core/card.h>
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#include "dbg.h"
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#include "autok.h"
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#include "autok_dvfs.h"
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void msdc_sdio_restore_after_resume(struct msdc_host *host)
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{
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}
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void msdc_save_timing_setting(struct msdc_host *host)
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{
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struct msdc_hw *hw = host->hw;
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void __iomem *base = host->base, *base_top;
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int i;
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MSDC_GET_FIELD(MSDC_IOCON, MSDC_IOCON_RSPL, hw->cmd_edge);
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MSDC_GET_FIELD(MSDC_IOCON, MSDC_IOCON_R_D_SMPL, hw->rdata_edge);
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MSDC_GET_FIELD(MSDC_IOCON, MSDC_IOCON_W_D_SMPL, hw->wdata_edge);
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// this is for suspend only
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host->saved_para.sdc_cfg = MSDC_READ32(SDC_CFG);
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host->saved_para.iocon = MSDC_READ32(MSDC_IOCON);
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host->saved_para.emmc50_cfg0 = MSDC_READ32(EMMC50_CFG0);
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host->saved_para.pb0 = MSDC_READ32(MSDC_PATCH_BIT0);
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host->saved_para.pb1 = MSDC_READ32(MSDC_PATCH_BIT1);
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host->saved_para.pb2 = MSDC_READ32(MSDC_PATCH_BIT2);
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host->saved_para.sdc_fifo_cfg = MSDC_READ32(SDC_FIFO_CFG);
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host->saved_para.sdc_adv_cfg0 = MSDC_READ32(SDC_ADV_CFG0);
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if (host->base_top) {
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base_top = host->base_top;
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host->saved_para.emmc_top_control
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= MSDC_READ32(EMMC_TOP_CONTROL);
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host->saved_para.emmc_top_cmd
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= MSDC_READ32(EMMC_TOP_CMD);
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host->saved_para.top_emmc50_pad_ctl0
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= MSDC_READ32(TOP_EMMC50_PAD_CTL0);
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host->saved_para.top_emmc50_pad_ds_tune
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= MSDC_READ32(TOP_EMMC50_PAD_DS_TUNE);
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for (i = 0; i < 8; i++) {
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host->saved_para.top_emmc50_pad_dat_tune[i]
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= MSDC_READ32(TOP_EMMC50_PAD_DAT0_TUNE + i * 4);
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}
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} else {
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host->saved_para.pad_tune0 = MSDC_READ32(MSDC_PAD_TUNE0);
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host->saved_para.pad_tune1 = MSDC_READ32(MSDC_PAD_TUNE1);
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}
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}
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void msdc_set_bad_card_and_remove(struct msdc_host *host)
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{
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unsigned long flags;
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if (host == NULL) {
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pr_info("WARN: host is NULL");
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return;
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}
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if (host->card_inserted) {
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host->block_bad_card = 1;
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host->card_inserted = 0;
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}
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if ((host->mmc == NULL) || (host->mmc->card == NULL)) {
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ERR_MSG("WARN: mmc or card is NULL");
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return;
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}
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if (host->mmc->card) {
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spin_lock_irqsave(&host->remove_bad_card, flags);
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mmc_card_set_removed(host->mmc->card);
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spin_unlock_irqrestore(&host->remove_bad_card, flags);
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#ifndef CONFIG_GPIOLIB
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ERR_MSG("Cannot get gpio %d level", cd_gpio);
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#else
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if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE)) {
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ERR_MSG("Schedule mmc_rescan");
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mmc_detect_change(host->mmc, msecs_to_jiffies(200));
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} else
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#endif
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{
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/*
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* prevent from calling device_del with mmcqd/X,
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* it will cause dead lock
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*/
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ERR_MSG("Schedule msdc_remove_card");
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schedule_delayed_work(&host->remove_card,
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msecs_to_jiffies(200));
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}
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if (host->block_bad_card)
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ERR_MSG(
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"Remove the bad card, block_bad_card=%d, card_inserted=%d",
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host->block_bad_card, host->card_inserted);
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}
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}
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void msdc_remove_card(struct work_struct *work)
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{
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struct msdc_host *host =
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container_of(work, struct msdc_host, remove_card.work);
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if (!host->mmc || !host->mmc->card) {
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ERR_MSG("WARN: mmc or card is NULL");
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return;
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}
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ERR_MSG("Remove card");
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mmc_claim_host(host->mmc);
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mmc_remove_card(host->mmc->card);
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host->mmc->card = NULL;
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mmc_detach_bus(host->mmc);
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mmc_power_off(host->mmc);
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mmc_release_host(host->mmc);
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}
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int msdc_data_timeout_cont_chk(struct msdc_host *host)
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{
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if ((host->hw->host_function == MSDC_SD) &&
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(host->data_timeout_cont >= MSDC_MAX_DATA_TIMEOUT_CONTINUOUS)) {
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ERR_MSG("force remove bad card, data timeout continuous %d",
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host->data_timeout_cont);
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msdc_set_bad_card_and_remove(host);
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return 1;
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}
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return 0;
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}
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int emmc_reinit_tuning(struct mmc_host *mmc)
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{
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struct msdc_host *host = mmc_priv(mmc);
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void __iomem *base = host->base;
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u32 div = 0;
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u32 mode = 0;
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unsigned int caps_hw_reset = 0;
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if (!mmc->card) {
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pr_notice("mmc card = NULL, skip reset tuning\n");
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return -1;
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}
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/* Switch to DDR/HS mode */
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if (mmc->card->mmc_avail_type
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& (EXT_CSD_CARD_TYPE_HS200 | EXT_CSD_CARD_TYPE_HS400)) {
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mmc->card->mmc_avail_type &=
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~(EXT_CSD_CARD_TYPE_HS200|EXT_CSD_CARD_TYPE_HS400);
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pr_notice("msdc%d: switch to DDR/HS mode, reinit card\n",
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host->id);
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if (mmc->caps & MMC_CAP_HW_RESET) {
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caps_hw_reset = 1;
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} else {
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caps_hw_reset = 0;
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mmc->caps |= MMC_CAP_HW_RESET;
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}
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mmc->ios.timing = MMC_TIMING_LEGACY;
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mmc->ios.clock = 260000;
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msdc_ops_set_ios(mmc, &mmc->ios);
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host->hs400_mode = false;
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if (mmc_hw_reset(mmc))
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pr_notice("msdc%d fail to switch to DDR/HS mode\n",
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host->id);
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/* restore MMC_CAP_HW_RESET */
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if (!caps_hw_reset)
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mmc->caps &= ~MMC_CAP_HW_RESET;
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goto done;
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}
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/* Reduce to lower frequency */
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MSDC_GET_FIELD(MSDC_CFG, MSDC_CFG_CKDIV, div);
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MSDC_GET_FIELD(MSDC_CFG, MSDC_CFG_CKMOD, mode);
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div += 1;
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if (div > EMMC_MAX_FREQ_DIV) {
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pr_notice("msdc%d: max lower freq: %d\n", host->id, div);
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return 1;
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}
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msdc_clk_stable(host, mode, div, 0);
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host->sclk = (div == 0) ? host->hclk / 4 : host->hclk / (4 * div);
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pr_notice("msdc%d: reduce frequence to %dMhz\n",
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host->id, host->sclk / 1000000);
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done:
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return 0;
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}
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int sdcard_hw_reset(struct mmc_host *mmc)
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{
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struct msdc_host *host = mmc_priv(mmc);
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int ret = 0;
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int level = 1;
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#ifdef CONFIG_GPIOLIB
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level = __gpio_get_value(cd_gpio);
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#endif
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host->card_inserted = (host->hw->cd_level == level) ? 1 : 0;
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if (!(host->card_inserted)) {
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pr_notice("card is not inserted!\n");
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msdc_set_bad_card_and_remove(host);
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ret = -1;
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return ret;
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}
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/* power reset sdcard */
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mmc->ios.timing = MMC_TIMING_LEGACY;
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/* do not set same as HOST_MIN_MCLK
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* or else it will be set as block_bad_card when power off
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*/
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mmc->ios.clock = 300000;
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msdc_ops_set_ios(mmc, &mmc->ios);
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ret = mmc_hw_reset(mmc);
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if (ret) {
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if (++host->power_cycle_cnt
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> MSDC_MAX_POWER_CYCLE_FAIL_CONTINUOUS)
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msdc_set_bad_card_and_remove(host);
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pr_notice(
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"msdc%d power reset (%d) failed, block_bad_card = %d\n",
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host->id, host->power_cycle_cnt, host->block_bad_card);
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} else {
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host->power_cycle_cnt = 0;
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pr_notice("msdc%d power reset success\n", host->id);
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}
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return ret;
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}
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/* SDcard will change speed mode and power reset
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* UHS card
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* UHS_SDR104 --> UHS_DDR50 --> UHS_SDR50 --> UHS_SDR25
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* HS card
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* 50MHz --> 25MHz --> 12.5MHz --> 6.25MHz
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*/
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int sdcard_reset_tuning(struct mmc_host *mmc)
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{
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struct msdc_host *host = mmc_priv(mmc);
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char *remove_cap;
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int ret = 0;
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if (!mmc->card) {
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pr_notice("mmc card = NULL, skip reset tuning\n");
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return -1;
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}
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if (mmc_card_uhs(mmc->card)) {
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if (mmc->card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR104) {
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mmc->card->sw_caps.sd3_bus_mode &= ~SD_MODE_UHS_SDR104;
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remove_cap = "UHS_SDR104";
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} else if (mmc->card->sw_caps.sd3_bus_mode
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& SD_MODE_UHS_DDR50) {
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mmc->card->sw_caps.sd3_bus_mode &= ~SD_MODE_UHS_DDR50;
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remove_cap = "UHS_DDR50";
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} else if (mmc->card->sw_caps.sd3_bus_mode
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& SD_MODE_UHS_SDR50) {
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mmc->card->sw_caps.sd3_bus_mode &= ~SD_MODE_UHS_SDR50;
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remove_cap = "UHS_SDR50";
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} else if (mmc->card->sw_caps.sd3_bus_mode
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& SD_MODE_UHS_SDR25) {
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mmc->card->sw_caps.sd3_bus_mode &= ~SD_MODE_UHS_SDR25;
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remove_cap = "UHS_SDR25";
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} else {
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remove_cap = "none";
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}
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pr_notice("msdc%d: remove %s mode then reinit card\n", host->id,
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remove_cap);
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} else if (mmc_card_hs(mmc->card)) {
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if (mmc->card->sw_caps.hs_max_dtr >= HIGH_SPEED_MAX_DTR / 4)
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mmc->card->sw_caps.hs_max_dtr /= 2;
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pr_notice("msdc%d: set hs speed %dhz then reinit card\n",
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host->id, mmc->card->sw_caps.hs_max_dtr);
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} else {
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pr_notice("msdc%d: ds card just reinit card\n", host->id);
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}
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/* force remove card for continuous data timeout */
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ret = msdc_data_timeout_cont_chk(host);
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if (ret) {
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ret = -1;
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goto done;
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}
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/* power cycle sdcard */
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ret = sdcard_hw_reset(mmc);
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if (ret) {
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ret = -1;
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goto done;
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}
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done:
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return ret;
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}
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void msdc_restore_timing_setting(struct msdc_host *host)
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{
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void __iomem *base = host->base, *base_top = host->base_top;
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int emmc = (host->hw->host_function == MSDC_EMMC) ? 1 : 0;
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int i;
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autok_path_sel(host);
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MSDC_WRITE32(SDC_CFG, host->saved_para.sdc_cfg);
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MSDC_WRITE32(MSDC_IOCON, host->saved_para.iocon);
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if (!host->base_top) {
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MSDC_WRITE32(MSDC_PAD_TUNE0, host->saved_para.pad_tune0);
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MSDC_WRITE32(MSDC_PAD_TUNE1, host->saved_para.pad_tune1);
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}
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MSDC_WRITE32(MSDC_PATCH_BIT0, host->saved_para.pb0);
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MSDC_WRITE32(MSDC_PATCH_BIT1, host->saved_para.pb1);
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MSDC_WRITE32(MSDC_PATCH_BIT2, host->saved_para.pb2);
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MSDC_WRITE32(SDC_FIFO_CFG, host->saved_para.sdc_fifo_cfg);
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MSDC_WRITE32(SDC_ADV_CFG0, host->saved_para.sdc_adv_cfg0);
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if (emmc && !host->base_top) {
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/* FIX ME: sdio shall add extra check for sdio3.0+ */
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MSDC_SET_FIELD(EMMC50_PAD_DS_TUNE, MSDC_EMMC50_PAD_DS_TUNE_DLY1,
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host->saved_para.ds_dly1);
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MSDC_SET_FIELD(EMMC50_PAD_DS_TUNE, MSDC_EMMC50_PAD_DS_TUNE_DLY3,
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host->saved_para.ds_dly3);
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MSDC_WRITE32(EMMC50_PAD_CMD_TUNE,
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host->saved_para.emmc50_pad_cmd_tune);
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MSDC_WRITE32(EMMC50_PAD_DAT01_TUNE,
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host->saved_para.emmc50_dat01);
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MSDC_WRITE32(EMMC50_PAD_DAT23_TUNE,
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host->saved_para.emmc50_dat23);
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MSDC_WRITE32(EMMC50_PAD_DAT45_TUNE,
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host->saved_para.emmc50_dat45);
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MSDC_WRITE32(EMMC50_PAD_DAT67_TUNE,
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host->saved_para.emmc50_dat67);
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}
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if (emmc)
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MSDC_WRITE32(EMMC50_CFG0, host->saved_para.emmc50_cfg0);
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if (host->base_top) {
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MSDC_WRITE32(EMMC_TOP_CONTROL,
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host->saved_para.emmc_top_control);
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MSDC_WRITE32(EMMC_TOP_CMD,
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host->saved_para.emmc_top_cmd);
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MSDC_WRITE32(TOP_EMMC50_PAD_CTL0,
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host->saved_para.top_emmc50_pad_ctl0);
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MSDC_WRITE32(TOP_EMMC50_PAD_DS_TUNE,
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host->saved_para.top_emmc50_pad_ds_tune);
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for (i = 0; i < 8; i++) {
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MSDC_WRITE32(TOP_EMMC50_PAD_DAT0_TUNE + i * 4,
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host->saved_para.top_emmc50_pad_dat_tune[i]);
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}
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}
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if (host->use_hw_dvfs == 1)
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msdc_dvfs_reg_restore(host);
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}
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void msdc_init_tune_path(struct msdc_host *host, unsigned char timing)
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{
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void __iomem *base = host->base, *base_top = host->base_top;
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MSDC_WRITE32(MSDC_PAD_TUNE0, 0x00000000);
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if (host->base_top) {
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/* FIX ME: toggle these fields accroding to timing */
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/* FIX ME: maybe unnecessary if autok can take care */
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MSDC_CLR_BIT32(EMMC_TOP_CONTROL, DATA_K_VALUE_SEL);
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MSDC_CLR_BIT32(EMMC_TOP_CONTROL, DELAY_EN);
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MSDC_CLR_BIT32(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY);
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MSDC_CLR_BIT32(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL);
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MSDC_CLR_BIT32(EMMC_TOP_CONTROL, PAD_RXDLY_SEL);
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MSDC_CLR_BIT32(EMMC_TOP_CMD, PAD_CMD_RXDLY);
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MSDC_CLR_BIT32(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY_SEL);
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MSDC_CLR_BIT32(TOP_EMMC50_PAD_CTL0, PAD_CLK_TXDLY);
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}
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MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_DDLSEL);
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MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_R_D_SMPL_SEL);
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MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_R_D_SMPL);
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if (timing == MMC_TIMING_MMC_HS400) {
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MSDC_CLR_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL);
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MSDC_CLR_BIT32(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL);
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if (host->base_top) {
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/* FIX ME: maybe unnecessary if autok can take care */
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MSDC_CLR_BIT32(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL);
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MSDC_CLR_BIT32(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL);
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}
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} else {
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MSDC_SET_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL);
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MSDC_CLR_BIT32(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL);
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if (host->base_top) {
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/* FIX ME: maybe unnecessary if autok can take care */
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MSDC_SET_BIT32(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL);
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MSDC_CLR_BIT32(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL);
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}
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}
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if (timing == MMC_TIMING_MMC_HS400)
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MSDC_CLR_BIT32(MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTS);
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else
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MSDC_SET_BIT32(MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTS);
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MSDC_CLR_BIT32(MSDC_IOCON, MSDC_IOCON_W_D_SMPL_SEL);
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MSDC_CLR_BIT32(MSDC_PATCH_BIT2, MSDC_PB2_CFGRESP);
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MSDC_SET_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_CMDRRDLYSEL);
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MSDC_CLR_BIT32(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_CMDRRDLY2SEL);
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if ((timing == MMC_TIMING_MMC_HS400) && (host->base_top)) {
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/* FIX ME: maybe unnecessary if autok can take care */
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MSDC_SET_BIT32(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY_SEL);
|
|
MSDC_CLR_BIT32(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY2_SEL);
|
|
}
|
|
|
|
MSDC_CLR_BIT32(EMMC50_CFG0, MSDC_EMMC50_CFG_CMD_RESP_SEL);
|
|
|
|
autok_path_sel(host);
|
|
}
|
|
|
|
void msdc_init_tune_setting(struct msdc_host *host)
|
|
{
|
|
void __iomem *base = host->base, *base_top = host->base_top;
|
|
u32 val;
|
|
|
|
/* FIX ME: check if always convered by autok */
|
|
MSDC_SET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_CLKTXDLY,
|
|
MSDC_CLKTXDLY);
|
|
if (host->base_top) {
|
|
MSDC_SET_FIELD(TOP_EMMC50_PAD_CTL0, PAD_CLK_TXDLY,
|
|
MSDC_CLKTXDLY);
|
|
MSDC_SET_FIELD(EMMC_TOP_CONTROL,
|
|
(PAD_DAT_RD_RXDLY2 | PAD_DAT_RD_RXDLY), 0);
|
|
MSDC_SET_FIELD(EMMC_TOP_CMD,
|
|
(PAD_CMD_RXDLY2 | PAD_CMD_RXDLY), 0);
|
|
MSDC_SET_FIELD(TOP_EMMC50_PAD_DS_TUNE,
|
|
(PAD_DS_DLY3 | PAD_DS_DLY2 | PAD_DS_DLY1), 0);
|
|
}
|
|
|
|
/* Reserve MSDC_IOCON_DDR50CKD bit, clear all other bits */
|
|
val = MSDC_READ32(MSDC_IOCON) & MSDC_IOCON_DDR50CKD;
|
|
MSDC_WRITE32(MSDC_IOCON, val);
|
|
|
|
MSDC_WRITE32(MSDC_DAT_RDDLY0, 0x00000000);
|
|
MSDC_WRITE32(MSDC_DAT_RDDLY1, 0x00000000);
|
|
|
|
MSDC_WRITE32(MSDC_PATCH_BIT0, MSDC_PB0_DEFAULT_VAL);
|
|
MSDC_WRITE32(MSDC_PATCH_BIT1, MSDC_PB1_DEFAULT_VAL);
|
|
|
|
/* Fix HS400 mode */
|
|
MSDC_CLR_BIT32(EMMC50_CFG0, MSDC_EMMC50_CFG_TXSKEW_SEL);
|
|
MSDC_SET_BIT32(MSDC_PATCH_BIT1, MSDC_PB1_DDR_CMD_FIX_SEL);
|
|
|
|
/* DDR50 mode */
|
|
MSDC_SET_BIT32(MSDC_PATCH_BIT2, MSDC_PB2_DDR50SEL);
|
|
|
|
/* 64T + 48T cmd <-> resp */
|
|
MSDC_SET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_RESPWAITCNT,
|
|
MSDC_PB2_DEFAULT_RESPWAITCNT);
|
|
MSDC_SET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_RESPSTENSEL,
|
|
MSDC_PB2_DEFAULT_RESPSTENSEL);
|
|
MSDC_SET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_CRCSTSENSEL,
|
|
MSDC_PB2_DEFAULT_CRCSTSENSEL);
|
|
|
|
/* FIX ME: check if can be moved to msdc_cust.c */
|
|
#ifdef CONFIG_MACH_MT6799
|
|
if (CHIP_IS_VER2())
|
|
SET_EMMC50_CFG_END_BIT_CHK_CNT(EMMC50_CFG_END_BIT_CHK_CNT);
|
|
#endif
|
|
|
|
autok_path_sel(host);
|
|
}
|
|
|
|
void msdc_ios_tune_setting(struct msdc_host *host, struct mmc_ios *ios)
|
|
{
|
|
autok_msdc_tx_setting(host, ios);
|
|
}
|