1510 lines
43 KiB
C
Executable file
1510 lines
43 KiB
C
Executable file
/**
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* dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
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*
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* Copyright (C) 2014 Chen-Zhi (Roger Chen)
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*
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* Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/stmmac.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/phy.h>
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#include <linux/of_net.h>
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#include <linux/gpio.h>
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#include <linux/module.h>
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#include <linux/of_gpio.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/pm_runtime.h>
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#include "stmmac_platform.h"
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struct rk_priv_data;
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struct rk_gmac_ops {
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void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
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int tx_delay, int rx_delay);
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void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
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void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
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void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
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void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
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};
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struct rk_priv_data {
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struct platform_device *pdev;
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int phy_iface;
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struct regulator *regulator;
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bool suspended;
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const struct rk_gmac_ops *ops;
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bool clk_enabled;
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bool clock_input;
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bool integrated_phy;
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struct clk *clk_mac;
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struct clk *gmac_clkin;
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struct clk *mac_clk_rx;
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struct clk *mac_clk_tx;
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struct clk *clk_mac_ref;
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struct clk *clk_mac_refout;
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struct clk *clk_mac_speed;
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struct clk *aclk_mac;
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struct clk *pclk_mac;
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struct clk *clk_phy;
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struct reset_control *phy_reset;
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int tx_delay;
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int rx_delay;
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struct regmap *grf;
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};
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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#define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
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#define GRF_CLR_BIT(nr) (BIT(nr+16))
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#define DELAY_ENABLE(soc, tx, rx) \
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(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
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((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
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#define PX30_GRF_GMAC_CON1 0x0904
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/* PX30_GRF_GMAC_CON1 */
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#define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
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GRF_BIT(6))
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#define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
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#define PX30_GMAC_SPEED_100M GRF_BIT(2)
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static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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return;
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}
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regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
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PX30_GMAC_PHY_INTF_SEL_RMII);
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}
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static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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int ret;
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if (IS_ERR(bsp_priv->clk_mac_speed)) {
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dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
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return;
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}
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if (speed == 10) {
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regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
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PX30_GMAC_SPEED_10M);
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ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000);
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if (ret)
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dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
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__func__, ret);
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} else if (speed == 100) {
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regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
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PX30_GMAC_SPEED_100M);
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ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000);
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if (ret)
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dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
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__func__, ret);
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} else {
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dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
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}
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}
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static const struct rk_gmac_ops px30_ops = {
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.set_to_rmii = px30_set_to_rmii,
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.set_rmii_speed = px30_set_rmii_speed,
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};
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#define RK3128_GRF_MAC_CON0 0x0168
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#define RK3128_GRF_MAC_CON1 0x016c
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/* RK3128_GRF_MAC_CON0 */
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#define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
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#define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
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#define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
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#define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
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#define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
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#define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
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/* RK3128_GRF_MAC_CON1 */
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#define RK3128_GMAC_PHY_INTF_SEL_RGMII \
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(GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
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#define RK3128_GMAC_PHY_INTF_SEL_RMII \
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(GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
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#define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
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#define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
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#define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
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#define RK3128_GMAC_SPEED_100M GRF_BIT(10)
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#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
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#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
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#define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
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#define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
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#define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
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#define RK3128_GMAC_RMII_MODE GRF_BIT(14)
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#define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
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static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
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int tx_delay, int rx_delay)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "Missing rockchip,grf property\n");
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return;
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}
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regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
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RK3128_GMAC_PHY_INTF_SEL_RGMII |
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RK3128_GMAC_RMII_MODE_CLR);
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regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
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DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
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RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
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RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
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}
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static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "Missing rockchip,grf property\n");
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return;
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}
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regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
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RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
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}
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static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "Missing rockchip,grf property\n");
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return;
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}
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if (speed == 10)
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regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
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RK3128_GMAC_CLK_2_5M);
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else if (speed == 100)
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regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
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RK3128_GMAC_CLK_25M);
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else if (speed == 1000)
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regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
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RK3128_GMAC_CLK_125M);
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else
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dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
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}
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static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "Missing rockchip,grf property\n");
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return;
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}
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if (speed == 10) {
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regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
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RK3128_GMAC_RMII_CLK_2_5M |
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RK3128_GMAC_SPEED_10M);
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} else if (speed == 100) {
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regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
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RK3128_GMAC_RMII_CLK_25M |
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RK3128_GMAC_SPEED_100M);
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} else {
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dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
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}
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}
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static const struct rk_gmac_ops rk3128_ops = {
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.set_to_rgmii = rk3128_set_to_rgmii,
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.set_to_rmii = rk3128_set_to_rmii,
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.set_rgmii_speed = rk3128_set_rgmii_speed,
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.set_rmii_speed = rk3128_set_rmii_speed,
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};
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#define RK3228_GRF_MAC_CON0 0x0900
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#define RK3228_GRF_MAC_CON1 0x0904
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#define RK3228_GRF_CON_MUX 0x50
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/* RK3228_GRF_MAC_CON0 */
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#define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
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#define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
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/* RK3228_GRF_MAC_CON1 */
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#define RK3228_GMAC_PHY_INTF_SEL_RGMII \
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(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
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#define RK3228_GMAC_PHY_INTF_SEL_RMII \
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(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
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#define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
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#define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
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#define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
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#define RK3228_GMAC_SPEED_100M GRF_BIT(2)
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#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
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#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
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#define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
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#define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9))
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#define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9))
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#define RK3228_GMAC_RMII_MODE GRF_BIT(10)
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#define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
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#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
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#define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
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#define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
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#define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
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/* RK3228_GRF_COM_MUX */
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#define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15)
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static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
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int tx_delay, int rx_delay)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "Missing rockchip,grf property\n");
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return;
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}
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regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
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RK3228_GMAC_PHY_INTF_SEL_RGMII |
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RK3228_GMAC_RMII_MODE_CLR |
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DELAY_ENABLE(RK3228, tx_delay, rx_delay));
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regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
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RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
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RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
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}
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static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "Missing rockchip,grf property\n");
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return;
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}
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regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
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RK3228_GMAC_PHY_INTF_SEL_RMII |
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RK3228_GMAC_RMII_MODE);
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/* set MAC to RMII mode */
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regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
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}
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static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "Missing rockchip,grf property\n");
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return;
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}
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if (speed == 10)
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regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
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RK3228_GMAC_CLK_2_5M);
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else if (speed == 100)
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regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
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RK3228_GMAC_CLK_25M);
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else if (speed == 1000)
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regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
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RK3228_GMAC_CLK_125M);
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else
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dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
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}
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static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "Missing rockchip,grf property\n");
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return;
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}
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if (speed == 10)
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regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
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RK3228_GMAC_RMII_CLK_2_5M |
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RK3228_GMAC_SPEED_10M);
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else if (speed == 100)
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regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
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RK3228_GMAC_RMII_CLK_25M |
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RK3228_GMAC_SPEED_100M);
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else
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dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
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}
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static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
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{
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regmap_write(priv->grf, RK3228_GRF_CON_MUX,
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RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
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}
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static const struct rk_gmac_ops rk3228_ops = {
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.set_to_rgmii = rk3228_set_to_rgmii,
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.set_to_rmii = rk3228_set_to_rmii,
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.set_rgmii_speed = rk3228_set_rgmii_speed,
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.set_rmii_speed = rk3228_set_rmii_speed,
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.integrated_phy_powerup = rk3228_integrated_phy_powerup,
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};
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#define RK3288_GRF_SOC_CON1 0x0248
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#define RK3288_GRF_SOC_CON3 0x0250
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/*RK3288_GRF_SOC_CON1*/
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#define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \
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GRF_CLR_BIT(8))
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#define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
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GRF_BIT(8))
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#define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
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#define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
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#define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
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#define RK3288_GMAC_SPEED_100M GRF_BIT(10)
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#define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
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#define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
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#define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
|
|
#define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
|
|
#define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
|
|
#define RK3288_GMAC_RMII_MODE GRF_BIT(14)
|
|
#define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
|
|
|
|
/*RK3288_GRF_SOC_CON3*/
|
|
#define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
|
|
#define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
|
|
#define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
|
|
#define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
|
|
#define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
|
|
#define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
|
|
|
|
static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
|
|
int tx_delay, int rx_delay)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "Missing rockchip,grf property\n");
|
|
return;
|
|
}
|
|
|
|
regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
|
|
RK3288_GMAC_PHY_INTF_SEL_RGMII |
|
|
RK3288_GMAC_RMII_MODE_CLR);
|
|
regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
|
|
DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
|
|
RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
|
|
RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
|
|
}
|
|
|
|
static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "Missing rockchip,grf property\n");
|
|
return;
|
|
}
|
|
|
|
regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
|
|
RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
|
|
}
|
|
|
|
static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "Missing rockchip,grf property\n");
|
|
return;
|
|
}
|
|
|
|
if (speed == 10)
|
|
regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
|
|
RK3288_GMAC_CLK_2_5M);
|
|
else if (speed == 100)
|
|
regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
|
|
RK3288_GMAC_CLK_25M);
|
|
else if (speed == 1000)
|
|
regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
|
|
RK3288_GMAC_CLK_125M);
|
|
else
|
|
dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
|
|
}
|
|
|
|
static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "Missing rockchip,grf property\n");
|
|
return;
|
|
}
|
|
|
|
if (speed == 10) {
|
|
regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
|
|
RK3288_GMAC_RMII_CLK_2_5M |
|
|
RK3288_GMAC_SPEED_10M);
|
|
} else if (speed == 100) {
|
|
regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
|
|
RK3288_GMAC_RMII_CLK_25M |
|
|
RK3288_GMAC_SPEED_100M);
|
|
} else {
|
|
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
|
|
}
|
|
}
|
|
|
|
static const struct rk_gmac_ops rk3288_ops = {
|
|
.set_to_rgmii = rk3288_set_to_rgmii,
|
|
.set_to_rmii = rk3288_set_to_rmii,
|
|
.set_rgmii_speed = rk3288_set_rgmii_speed,
|
|
.set_rmii_speed = rk3288_set_rmii_speed,
|
|
};
|
|
|
|
#define RK3328_GRF_MAC_CON0 0x0900
|
|
#define RK3328_GRF_MAC_CON1 0x0904
|
|
#define RK3328_GRF_MAC_CON2 0x0908
|
|
#define RK3328_GRF_MACPHY_CON1 0xb04
|
|
|
|
/* RK3328_GRF_MAC_CON0 */
|
|
#define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
|
|
#define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
|
|
|
|
/* RK3328_GRF_MAC_CON1 */
|
|
#define RK3328_GMAC_PHY_INTF_SEL_RGMII \
|
|
(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
|
|
#define RK3328_GMAC_PHY_INTF_SEL_RMII \
|
|
(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
|
|
#define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
|
|
#define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
|
|
#define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
|
|
#define RK3328_GMAC_SPEED_100M GRF_BIT(2)
|
|
#define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
|
|
#define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
|
|
#define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
|
|
#define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12))
|
|
#define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12))
|
|
#define RK3328_GMAC_RMII_MODE GRF_BIT(9)
|
|
#define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9)
|
|
#define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
|
|
#define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
|
|
#define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
|
|
#define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0)
|
|
|
|
/* RK3328_GRF_MACPHY_CON1 */
|
|
#define RK3328_MACPHY_RMII_MODE GRF_BIT(9)
|
|
|
|
static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
|
|
int tx_delay, int rx_delay)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "Missing rockchip,grf property\n");
|
|
return;
|
|
}
|
|
|
|
regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
|
|
RK3328_GMAC_PHY_INTF_SEL_RGMII |
|
|
RK3328_GMAC_RMII_MODE_CLR |
|
|
RK3328_GMAC_RXCLK_DLY_ENABLE |
|
|
RK3328_GMAC_TXCLK_DLY_ENABLE);
|
|
|
|
regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
|
|
RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
|
|
RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
|
|
}
|
|
|
|
static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
unsigned int reg;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "Missing rockchip,grf property\n");
|
|
return;
|
|
}
|
|
|
|
reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
|
|
RK3328_GRF_MAC_CON1;
|
|
|
|
regmap_write(bsp_priv->grf, reg,
|
|
RK3328_GMAC_PHY_INTF_SEL_RMII |
|
|
RK3328_GMAC_RMII_MODE);
|
|
}
|
|
|
|
static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "Missing rockchip,grf property\n");
|
|
return;
|
|
}
|
|
|
|
if (speed == 10)
|
|
regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
|
|
RK3328_GMAC_CLK_2_5M);
|
|
else if (speed == 100)
|
|
regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
|
|
RK3328_GMAC_CLK_25M);
|
|
else if (speed == 1000)
|
|
regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
|
|
RK3328_GMAC_CLK_125M);
|
|
else
|
|
dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
|
|
}
|
|
|
|
static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
unsigned int reg;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "Missing rockchip,grf property\n");
|
|
return;
|
|
}
|
|
|
|
reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
|
|
RK3328_GRF_MAC_CON1;
|
|
|
|
if (speed == 10)
|
|
regmap_write(bsp_priv->grf, reg,
|
|
RK3328_GMAC_RMII_CLK_2_5M |
|
|
RK3328_GMAC_SPEED_10M);
|
|
else if (speed == 100)
|
|
regmap_write(bsp_priv->grf, reg,
|
|
RK3328_GMAC_RMII_CLK_25M |
|
|
RK3328_GMAC_SPEED_100M);
|
|
else
|
|
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
|
|
}
|
|
|
|
static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
|
|
{
|
|
regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
|
|
RK3328_MACPHY_RMII_MODE);
|
|
}
|
|
|
|
static const struct rk_gmac_ops rk3328_ops = {
|
|
.set_to_rgmii = rk3328_set_to_rgmii,
|
|
.set_to_rmii = rk3328_set_to_rmii,
|
|
.set_rgmii_speed = rk3328_set_rgmii_speed,
|
|
.set_rmii_speed = rk3328_set_rmii_speed,
|
|
.integrated_phy_powerup = rk3328_integrated_phy_powerup,
|
|
};
|
|
|
|
#define RK3366_GRF_SOC_CON6 0x0418
|
|
#define RK3366_GRF_SOC_CON7 0x041c
|
|
|
|
/* RK3366_GRF_SOC_CON6 */
|
|
#define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
|
|
GRF_CLR_BIT(11))
|
|
#define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
|
|
GRF_BIT(11))
|
|
#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
|
|
#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
|
|
#define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
|
|
#define RK3366_GMAC_SPEED_100M GRF_BIT(7)
|
|
#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
|
|
#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
|
|
#define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
|
|
#define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
|
|
#define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
|
|
#define RK3366_GMAC_RMII_MODE GRF_BIT(6)
|
|
#define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
|
|
|
|
/* RK3366_GRF_SOC_CON7 */
|
|
#define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
|
|
#define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
|
|
#define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
|
|
#define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
|
|
#define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
|
|
#define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
|
|
|
|
static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
|
|
int tx_delay, int rx_delay)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
|
|
RK3366_GMAC_PHY_INTF_SEL_RGMII |
|
|
RK3366_GMAC_RMII_MODE_CLR);
|
|
regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
|
|
DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
|
|
RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
|
|
RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
|
|
}
|
|
|
|
static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
|
|
RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
|
|
}
|
|
|
|
static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
if (speed == 10)
|
|
regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
|
|
RK3366_GMAC_CLK_2_5M);
|
|
else if (speed == 100)
|
|
regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
|
|
RK3366_GMAC_CLK_25M);
|
|
else if (speed == 1000)
|
|
regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
|
|
RK3366_GMAC_CLK_125M);
|
|
else
|
|
dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
|
|
}
|
|
|
|
static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
if (speed == 10) {
|
|
regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
|
|
RK3366_GMAC_RMII_CLK_2_5M |
|
|
RK3366_GMAC_SPEED_10M);
|
|
} else if (speed == 100) {
|
|
regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
|
|
RK3366_GMAC_RMII_CLK_25M |
|
|
RK3366_GMAC_SPEED_100M);
|
|
} else {
|
|
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
|
|
}
|
|
}
|
|
|
|
static const struct rk_gmac_ops rk3366_ops = {
|
|
.set_to_rgmii = rk3366_set_to_rgmii,
|
|
.set_to_rmii = rk3366_set_to_rmii,
|
|
.set_rgmii_speed = rk3366_set_rgmii_speed,
|
|
.set_rmii_speed = rk3366_set_rmii_speed,
|
|
};
|
|
|
|
#define RK3368_GRF_SOC_CON15 0x043c
|
|
#define RK3368_GRF_SOC_CON16 0x0440
|
|
|
|
/* RK3368_GRF_SOC_CON15 */
|
|
#define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
|
|
GRF_CLR_BIT(11))
|
|
#define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
|
|
GRF_BIT(11))
|
|
#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
|
|
#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
|
|
#define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
|
|
#define RK3368_GMAC_SPEED_100M GRF_BIT(7)
|
|
#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
|
|
#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
|
|
#define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
|
|
#define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
|
|
#define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
|
|
#define RK3368_GMAC_RMII_MODE GRF_BIT(6)
|
|
#define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
|
|
|
|
/* RK3368_GRF_SOC_CON16 */
|
|
#define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
|
|
#define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
|
|
#define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
|
|
#define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
|
|
#define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
|
|
#define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
|
|
|
|
static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
|
|
int tx_delay, int rx_delay)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
|
|
RK3368_GMAC_PHY_INTF_SEL_RGMII |
|
|
RK3368_GMAC_RMII_MODE_CLR);
|
|
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
|
|
DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
|
|
RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
|
|
RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
|
|
}
|
|
|
|
static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
|
|
RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
|
|
}
|
|
|
|
static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
if (speed == 10)
|
|
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
|
|
RK3368_GMAC_CLK_2_5M);
|
|
else if (speed == 100)
|
|
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
|
|
RK3368_GMAC_CLK_25M);
|
|
else if (speed == 1000)
|
|
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
|
|
RK3368_GMAC_CLK_125M);
|
|
else
|
|
dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
|
|
}
|
|
|
|
static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
if (speed == 10) {
|
|
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
|
|
RK3368_GMAC_RMII_CLK_2_5M |
|
|
RK3368_GMAC_SPEED_10M);
|
|
} else if (speed == 100) {
|
|
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
|
|
RK3368_GMAC_RMII_CLK_25M |
|
|
RK3368_GMAC_SPEED_100M);
|
|
} else {
|
|
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
|
|
}
|
|
}
|
|
|
|
static const struct rk_gmac_ops rk3368_ops = {
|
|
.set_to_rgmii = rk3368_set_to_rgmii,
|
|
.set_to_rmii = rk3368_set_to_rmii,
|
|
.set_rgmii_speed = rk3368_set_rgmii_speed,
|
|
.set_rmii_speed = rk3368_set_rmii_speed,
|
|
};
|
|
|
|
#define RK3399_GRF_SOC_CON5 0xc214
|
|
#define RK3399_GRF_SOC_CON6 0xc218
|
|
|
|
/* RK3399_GRF_SOC_CON5 */
|
|
#define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
|
|
GRF_CLR_BIT(11))
|
|
#define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
|
|
GRF_BIT(11))
|
|
#define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
|
|
#define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
|
|
#define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
|
|
#define RK3399_GMAC_SPEED_100M GRF_BIT(7)
|
|
#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
|
|
#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
|
|
#define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
|
|
#define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
|
|
#define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
|
|
#define RK3399_GMAC_RMII_MODE GRF_BIT(6)
|
|
#define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
|
|
|
|
/* RK3399_GRF_SOC_CON6 */
|
|
#define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
|
|
#define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
|
|
#define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
|
|
#define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
|
|
#define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
|
|
#define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
|
|
|
|
static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
|
|
int tx_delay, int rx_delay)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
|
|
RK3399_GMAC_PHY_INTF_SEL_RGMII |
|
|
RK3399_GMAC_RMII_MODE_CLR);
|
|
regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
|
|
DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
|
|
RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
|
|
RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
|
|
}
|
|
|
|
static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
|
|
RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
|
|
}
|
|
|
|
static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
if (speed == 10)
|
|
regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
|
|
RK3399_GMAC_CLK_2_5M);
|
|
else if (speed == 100)
|
|
regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
|
|
RK3399_GMAC_CLK_25M);
|
|
else if (speed == 1000)
|
|
regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
|
|
RK3399_GMAC_CLK_125M);
|
|
else
|
|
dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
|
|
}
|
|
|
|
static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
if (speed == 10) {
|
|
regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
|
|
RK3399_GMAC_RMII_CLK_2_5M |
|
|
RK3399_GMAC_SPEED_10M);
|
|
} else if (speed == 100) {
|
|
regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
|
|
RK3399_GMAC_RMII_CLK_25M |
|
|
RK3399_GMAC_SPEED_100M);
|
|
} else {
|
|
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
|
|
}
|
|
}
|
|
|
|
static const struct rk_gmac_ops rk3399_ops = {
|
|
.set_to_rgmii = rk3399_set_to_rgmii,
|
|
.set_to_rmii = rk3399_set_to_rmii,
|
|
.set_rgmii_speed = rk3399_set_rgmii_speed,
|
|
.set_rmii_speed = rk3399_set_rmii_speed,
|
|
};
|
|
|
|
#define RV1108_GRF_GMAC_CON0 0X0900
|
|
|
|
/* RV1108_GRF_GMAC_CON0 */
|
|
#define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
|
|
GRF_BIT(6))
|
|
#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
|
|
#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
|
|
#define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
|
|
#define RV1108_GMAC_SPEED_100M GRF_BIT(2)
|
|
#define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7)
|
|
#define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
|
|
|
|
static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
|
|
RV1108_GMAC_PHY_INTF_SEL_RMII);
|
|
}
|
|
|
|
static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
|
|
{
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (IS_ERR(bsp_priv->grf)) {
|
|
dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
|
|
return;
|
|
}
|
|
|
|
if (speed == 10) {
|
|
regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
|
|
RV1108_GMAC_RMII_CLK_2_5M |
|
|
RV1108_GMAC_SPEED_10M);
|
|
} else if (speed == 100) {
|
|
regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
|
|
RV1108_GMAC_RMII_CLK_25M |
|
|
RV1108_GMAC_SPEED_100M);
|
|
} else {
|
|
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
|
|
}
|
|
}
|
|
|
|
static const struct rk_gmac_ops rv1108_ops = {
|
|
.set_to_rmii = rv1108_set_to_rmii,
|
|
.set_rmii_speed = rv1108_set_rmii_speed,
|
|
};
|
|
|
|
#define RK_GRF_MACPHY_CON0 0xb00
|
|
#define RK_GRF_MACPHY_CON1 0xb04
|
|
#define RK_GRF_MACPHY_CON2 0xb08
|
|
#define RK_GRF_MACPHY_CON3 0xb0c
|
|
|
|
#define RK_MACPHY_ENABLE GRF_BIT(0)
|
|
#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
|
|
#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
|
|
#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
|
|
#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
|
|
#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
|
|
|
|
static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
|
|
{
|
|
if (priv->ops->integrated_phy_powerup)
|
|
priv->ops->integrated_phy_powerup(priv);
|
|
|
|
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
|
|
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
|
|
|
|
regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
|
|
regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
|
|
|
|
if (priv->phy_reset) {
|
|
/* PHY needs to be disabled before trying to reset it */
|
|
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
|
|
if (priv->phy_reset)
|
|
reset_control_assert(priv->phy_reset);
|
|
usleep_range(10, 20);
|
|
if (priv->phy_reset)
|
|
reset_control_deassert(priv->phy_reset);
|
|
usleep_range(10, 20);
|
|
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
|
|
msleep(30);
|
|
}
|
|
}
|
|
|
|
static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
|
|
{
|
|
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
|
|
if (priv->phy_reset)
|
|
reset_control_assert(priv->phy_reset);
|
|
}
|
|
|
|
static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
|
|
{
|
|
struct rk_priv_data *bsp_priv = plat->bsp_priv;
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
int ret;
|
|
|
|
bsp_priv->clk_enabled = false;
|
|
|
|
bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
|
|
if (IS_ERR(bsp_priv->mac_clk_rx))
|
|
dev_err(dev, "cannot get clock %s\n",
|
|
"mac_clk_rx");
|
|
|
|
bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
|
|
if (IS_ERR(bsp_priv->mac_clk_tx))
|
|
dev_err(dev, "cannot get clock %s\n",
|
|
"mac_clk_tx");
|
|
|
|
bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
|
|
if (IS_ERR(bsp_priv->aclk_mac))
|
|
dev_err(dev, "cannot get clock %s\n",
|
|
"aclk_mac");
|
|
|
|
bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
|
|
if (IS_ERR(bsp_priv->pclk_mac))
|
|
dev_err(dev, "cannot get clock %s\n",
|
|
"pclk_mac");
|
|
|
|
bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
|
|
if (IS_ERR(bsp_priv->clk_mac))
|
|
dev_err(dev, "cannot get clock %s\n",
|
|
"stmmaceth");
|
|
|
|
if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
|
|
bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
|
|
if (IS_ERR(bsp_priv->clk_mac_ref))
|
|
dev_err(dev, "cannot get clock %s\n",
|
|
"clk_mac_ref");
|
|
|
|
if (!bsp_priv->clock_input) {
|
|
bsp_priv->clk_mac_refout =
|
|
devm_clk_get(dev, "clk_mac_refout");
|
|
if (IS_ERR(bsp_priv->clk_mac_refout))
|
|
dev_err(dev, "cannot get clock %s\n",
|
|
"clk_mac_refout");
|
|
}
|
|
}
|
|
|
|
bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
|
|
if (IS_ERR(bsp_priv->clk_mac_speed))
|
|
dev_err(dev, "cannot get clock %s\n", "clk_mac_speed");
|
|
|
|
if (bsp_priv->clock_input) {
|
|
dev_info(dev, "clock input from PHY\n");
|
|
} else {
|
|
if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
|
|
clk_set_rate(bsp_priv->clk_mac, 50000000);
|
|
}
|
|
|
|
if (plat->phy_node && bsp_priv->integrated_phy) {
|
|
bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
|
|
if (IS_ERR(bsp_priv->clk_phy)) {
|
|
ret = PTR_ERR(bsp_priv->clk_phy);
|
|
dev_err(dev, "Cannot get PHY clock: %d\n", ret);
|
|
return -EINVAL;
|
|
}
|
|
clk_set_rate(bsp_priv->clk_phy, 50000000);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
|
|
{
|
|
int phy_iface = bsp_priv->phy_iface;
|
|
|
|
if (enable) {
|
|
if (!bsp_priv->clk_enabled) {
|
|
if (phy_iface == PHY_INTERFACE_MODE_RMII) {
|
|
if (!IS_ERR(bsp_priv->mac_clk_rx))
|
|
clk_prepare_enable(
|
|
bsp_priv->mac_clk_rx);
|
|
|
|
if (!IS_ERR(bsp_priv->clk_mac_ref))
|
|
clk_prepare_enable(
|
|
bsp_priv->clk_mac_ref);
|
|
|
|
if (!IS_ERR(bsp_priv->clk_mac_refout))
|
|
clk_prepare_enable(
|
|
bsp_priv->clk_mac_refout);
|
|
}
|
|
|
|
if (!IS_ERR(bsp_priv->clk_phy))
|
|
clk_prepare_enable(bsp_priv->clk_phy);
|
|
|
|
if (!IS_ERR(bsp_priv->aclk_mac))
|
|
clk_prepare_enable(bsp_priv->aclk_mac);
|
|
|
|
if (!IS_ERR(bsp_priv->pclk_mac))
|
|
clk_prepare_enable(bsp_priv->pclk_mac);
|
|
|
|
if (!IS_ERR(bsp_priv->mac_clk_tx))
|
|
clk_prepare_enable(bsp_priv->mac_clk_tx);
|
|
|
|
if (!IS_ERR(bsp_priv->clk_mac_speed))
|
|
clk_prepare_enable(bsp_priv->clk_mac_speed);
|
|
|
|
/**
|
|
* if (!IS_ERR(bsp_priv->clk_mac))
|
|
* clk_prepare_enable(bsp_priv->clk_mac);
|
|
*/
|
|
mdelay(5);
|
|
bsp_priv->clk_enabled = true;
|
|
}
|
|
} else {
|
|
if (bsp_priv->clk_enabled) {
|
|
if (phy_iface == PHY_INTERFACE_MODE_RMII) {
|
|
clk_disable_unprepare(bsp_priv->mac_clk_rx);
|
|
|
|
clk_disable_unprepare(bsp_priv->clk_mac_ref);
|
|
|
|
clk_disable_unprepare(bsp_priv->clk_mac_refout);
|
|
}
|
|
|
|
clk_disable_unprepare(bsp_priv->clk_phy);
|
|
|
|
clk_disable_unprepare(bsp_priv->aclk_mac);
|
|
|
|
clk_disable_unprepare(bsp_priv->pclk_mac);
|
|
|
|
clk_disable_unprepare(bsp_priv->mac_clk_tx);
|
|
|
|
clk_disable_unprepare(bsp_priv->clk_mac_speed);
|
|
/**
|
|
* if (!IS_ERR(bsp_priv->clk_mac))
|
|
* clk_disable_unprepare(bsp_priv->clk_mac);
|
|
*/
|
|
bsp_priv->clk_enabled = false;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
|
|
{
|
|
struct regulator *ldo = bsp_priv->regulator;
|
|
int ret;
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
if (!ldo)
|
|
return 0;
|
|
|
|
if (enable) {
|
|
ret = regulator_enable(ldo);
|
|
if (ret)
|
|
dev_err(dev, "fail to enable phy-supply\n");
|
|
} else {
|
|
ret = regulator_disable(ldo);
|
|
if (ret)
|
|
dev_err(dev, "fail to disable phy-supply\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
|
|
struct plat_stmmacenet_data *plat,
|
|
const struct rk_gmac_ops *ops)
|
|
{
|
|
struct rk_priv_data *bsp_priv;
|
|
struct device *dev = &pdev->dev;
|
|
int ret;
|
|
const char *strings = NULL;
|
|
int value;
|
|
|
|
bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
|
|
if (!bsp_priv)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
|
|
bsp_priv->ops = ops;
|
|
|
|
bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
|
|
if (IS_ERR(bsp_priv->regulator)) {
|
|
if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
|
|
dev_err(dev, "phy regulator is not available yet, deferred probing\n");
|
|
return ERR_PTR(-EPROBE_DEFER);
|
|
}
|
|
dev_err(dev, "no regulator found\n");
|
|
bsp_priv->regulator = NULL;
|
|
}
|
|
|
|
ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
|
|
if (ret) {
|
|
dev_err(dev, "Can not read property: clock_in_out.\n");
|
|
bsp_priv->clock_input = true;
|
|
} else {
|
|
dev_info(dev, "clock input or output? (%s).\n",
|
|
strings);
|
|
if (!strcmp(strings, "input"))
|
|
bsp_priv->clock_input = true;
|
|
else
|
|
bsp_priv->clock_input = false;
|
|
}
|
|
|
|
ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
|
|
if (ret) {
|
|
bsp_priv->tx_delay = 0x30;
|
|
dev_err(dev, "Can not read property: tx_delay.");
|
|
dev_err(dev, "set tx_delay to 0x%x\n",
|
|
bsp_priv->tx_delay);
|
|
} else {
|
|
dev_info(dev, "TX delay(0x%x).\n", value);
|
|
bsp_priv->tx_delay = value;
|
|
}
|
|
|
|
ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
|
|
if (ret) {
|
|
bsp_priv->rx_delay = 0x10;
|
|
dev_err(dev, "Can not read property: rx_delay.");
|
|
dev_err(dev, "set rx_delay to 0x%x\n",
|
|
bsp_priv->rx_delay);
|
|
} else {
|
|
dev_info(dev, "RX delay(0x%x).\n", value);
|
|
bsp_priv->rx_delay = value;
|
|
}
|
|
|
|
bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
|
|
"rockchip,grf");
|
|
|
|
if (plat->phy_node) {
|
|
bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
|
|
"phy-is-integrated");
|
|
if (bsp_priv->integrated_phy) {
|
|
bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
|
|
if (IS_ERR(bsp_priv->phy_reset)) {
|
|
dev_err(&pdev->dev, "No PHY reset control found.\n");
|
|
bsp_priv->phy_reset = NULL;
|
|
}
|
|
}
|
|
}
|
|
dev_info(dev, "integrated PHY? (%s).\n",
|
|
bsp_priv->integrated_phy ? "yes" : "no");
|
|
|
|
bsp_priv->pdev = pdev;
|
|
|
|
return bsp_priv;
|
|
}
|
|
|
|
static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
|
|
{
|
|
int ret;
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
ret = gmac_clk_enable(bsp_priv, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*rmii or rgmii*/
|
|
switch (bsp_priv->phy_iface) {
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
dev_info(dev, "init for RGMII\n");
|
|
bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
|
|
bsp_priv->rx_delay);
|
|
break;
|
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
|
dev_info(dev, "init for RGMII_ID\n");
|
|
bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
|
|
break;
|
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
|
dev_info(dev, "init for RGMII_RXID\n");
|
|
bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
|
|
break;
|
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
|
dev_info(dev, "init for RGMII_TXID\n");
|
|
bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
|
|
break;
|
|
case PHY_INTERFACE_MODE_RMII:
|
|
dev_info(dev, "init for RMII\n");
|
|
bsp_priv->ops->set_to_rmii(bsp_priv);
|
|
break;
|
|
default:
|
|
dev_err(dev, "NO interface defined!\n");
|
|
}
|
|
|
|
ret = phy_power_on(bsp_priv, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pm_runtime_enable(dev);
|
|
pm_runtime_get_sync(dev);
|
|
|
|
if (bsp_priv->integrated_phy)
|
|
rk_gmac_integrated_phy_powerup(bsp_priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void rk_gmac_powerdown(struct rk_priv_data *gmac)
|
|
{
|
|
struct device *dev = &gmac->pdev->dev;
|
|
|
|
if (gmac->integrated_phy)
|
|
rk_gmac_integrated_phy_powerdown(gmac);
|
|
|
|
pm_runtime_put_sync(dev);
|
|
pm_runtime_disable(dev);
|
|
|
|
phy_power_on(gmac, false);
|
|
gmac_clk_enable(gmac, false);
|
|
}
|
|
|
|
static void rk_fix_speed(void *priv, unsigned int speed)
|
|
{
|
|
struct rk_priv_data *bsp_priv = priv;
|
|
struct device *dev = &bsp_priv->pdev->dev;
|
|
|
|
switch (bsp_priv->phy_iface) {
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
|
bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
|
|
break;
|
|
case PHY_INTERFACE_MODE_RMII:
|
|
bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
|
|
break;
|
|
default:
|
|
dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
|
|
}
|
|
}
|
|
|
|
static int rk_gmac_probe(struct platform_device *pdev)
|
|
{
|
|
struct plat_stmmacenet_data *plat_dat;
|
|
struct stmmac_resources stmmac_res;
|
|
const struct rk_gmac_ops *data;
|
|
int ret;
|
|
|
|
data = of_device_get_match_data(&pdev->dev);
|
|
if (!data) {
|
|
dev_err(&pdev->dev, "no of match data provided\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = stmmac_get_platform_resources(pdev, &stmmac_res);
|
|
if (ret)
|
|
return ret;
|
|
|
|
plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
|
|
if (IS_ERR(plat_dat))
|
|
return PTR_ERR(plat_dat);
|
|
|
|
plat_dat->has_gmac = true;
|
|
plat_dat->fix_mac_speed = rk_fix_speed;
|
|
|
|
plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
|
|
if (IS_ERR(plat_dat->bsp_priv)) {
|
|
ret = PTR_ERR(plat_dat->bsp_priv);
|
|
goto err_remove_config_dt;
|
|
}
|
|
|
|
ret = rk_gmac_clk_init(plat_dat);
|
|
if (ret)
|
|
goto err_remove_config_dt;
|
|
|
|
ret = rk_gmac_powerup(plat_dat->bsp_priv);
|
|
if (ret)
|
|
goto err_remove_config_dt;
|
|
|
|
ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
|
|
if (ret)
|
|
goto err_gmac_powerdown;
|
|
|
|
return 0;
|
|
|
|
err_gmac_powerdown:
|
|
rk_gmac_powerdown(plat_dat->bsp_priv);
|
|
err_remove_config_dt:
|
|
stmmac_remove_config_dt(pdev, plat_dat);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rk_gmac_remove(struct platform_device *pdev)
|
|
{
|
|
struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
|
|
int ret = stmmac_dvr_remove(&pdev->dev);
|
|
|
|
rk_gmac_powerdown(bsp_priv);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int rk_gmac_suspend(struct device *dev)
|
|
{
|
|
struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
|
|
int ret = stmmac_suspend(dev);
|
|
|
|
/* Keep the PHY up if we use Wake-on-Lan. */
|
|
if (!device_may_wakeup(dev)) {
|
|
rk_gmac_powerdown(bsp_priv);
|
|
bsp_priv->suspended = true;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rk_gmac_resume(struct device *dev)
|
|
{
|
|
struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
|
|
|
|
/* The PHY was up for Wake-on-Lan. */
|
|
if (bsp_priv->suspended) {
|
|
rk_gmac_powerup(bsp_priv);
|
|
bsp_priv->suspended = false;
|
|
}
|
|
|
|
return stmmac_resume(dev);
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
|
|
|
|
static const struct of_device_id rk_gmac_dwmac_match[] = {
|
|
{ .compatible = "rockchip,px30-gmac", .data = &px30_ops },
|
|
{ .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
|
|
{ .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
|
|
{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
|
|
{ .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
|
|
{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
|
|
{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
|
|
{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
|
|
{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
|
|
|
|
static struct platform_driver rk_gmac_dwmac_driver = {
|
|
.probe = rk_gmac_probe,
|
|
.remove = rk_gmac_remove,
|
|
.driver = {
|
|
.name = "rk_gmac-dwmac",
|
|
.pm = &rk_gmac_pm_ops,
|
|
.of_match_table = rk_gmac_dwmac_match,
|
|
},
|
|
};
|
|
module_platform_driver(rk_gmac_dwmac_driver);
|
|
|
|
MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
|
|
MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
|
|
MODULE_LICENSE("GPL");
|