89 lines
2.8 KiB
C
Executable file
89 lines
2.8 KiB
C
Executable file
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*
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* Author: Light Hsieh <light.hsieh@mediatek.com>
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*
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*/
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#include "pinctrl-mtk-mt6768.h"
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#include "pinctrl-paris.h"
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/* MT6768 have multiple bases to program pin configuration listed as the below:
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* gpio:0x10005000, iocfg_lt:0x10002000, iocfg_lm:0x10002200,
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* iocfg_lb:0x10002400, iocfg_bl:0x10002600, iocfg_rm:0x10002800,
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* iocfg_rb:0x10002A00, iocfg_rt:0x10002C00, iocfg_tl:0x10002E00
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* _i_based could be used to indicate what base the pin should be mapped into.
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*/
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#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
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PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
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32, 0)
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#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
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PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
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32, 1)
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static const struct mtk_pin_reg_calc mt6768_reg_cals[PINCTRL_PIN_REG_MAX] = {
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[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6768_pin_mode_range),
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[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6768_pin_dir_range),
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[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6768_pin_di_range),
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[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6768_pin_do_range),
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[PINCTRL_PIN_REG_SR] = MTK_RANGE(mt6768_pin_dir_range),
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[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6768_pin_smt_range),
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[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6768_pin_ies_range),
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[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6768_pin_pu_range),
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[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6768_pin_pd_range),
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[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6768_pin_drv_range),
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[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6768_pin_pupd_range),
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[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6768_pin_r0_range),
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[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6768_pin_r1_range),
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};
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static const struct mtk_eint_hw mt6768_eint_hw = {
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.port_mask = 7,
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.ports = 6,
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.ap_num = 212,
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.db_cnt = 13,
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};
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static const struct mtk_pin_soc mt6768_data = {
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.reg_cal = mt6768_reg_cals,
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.pins = mtk_pins_mt6768,
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.npins = ARRAY_SIZE(mtk_pins_mt6768),
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.ngrps = ARRAY_SIZE(mtk_pins_mt6768),
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.nfuncs = 8,
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.eint_hw = &mt6768_eint_hw,
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.gpio_m = 0,
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.race_free_access = true,
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.bias_set_combo = mtk_pinconf_bias_set_combo,
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.bias_get_combo = mtk_pinconf_bias_get_combo,
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.drive_set = mtk_pinconf_drive_set_raw,
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.drive_get = mtk_pinconf_drive_get_raw,
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};
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static const struct of_device_id mt6768_pinctrl_of_match[] = {
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{ .compatible = "mediatek,mt6768-pinctrl", },
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{ }
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};
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static int mt6768_pinctrl_probe(struct platform_device *pdev)
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{
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return mtk_paris_pinctrl_probe(pdev, &mt6768_data);
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}
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static struct platform_driver mt6768_pinctrl_driver = {
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.driver = {
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.name = "mt6768-pinctrl",
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.of_match_table = mt6768_pinctrl_of_match,
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.pm = &mtk_eint_pm_ops_v2,
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},
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.probe = mt6768_pinctrl_probe,
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};
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static int __init mt6768_pinctrl_init(void)
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{
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return platform_driver_register(&mt6768_pinctrl_driver);
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}
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arch_initcall(mt6768_pinctrl_init);
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