513 lines
12 KiB
C
Executable file
513 lines
12 KiB
C
Executable file
/*
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* arch/powerpc/sysdev/qe_lib/qe_ic.c
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*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Li Yang <leoli@freescale.com>
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* Based on code from Shlomi Gridish <gridish@freescale.com>
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*
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* QUICC ENGINE Interrupt Controller
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/slab.h>
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#include <linux/stddef.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/device.h>
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#include <linux/spinlock.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <soc/fsl/qe/qe_ic.h>
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#include "qe_ic.h"
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static DEFINE_RAW_SPINLOCK(qe_ic_lock);
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static struct qe_ic_info qe_ic_info[] = {
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[1] = {
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.mask = 0x00008000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 0,
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.pri_reg = QEIC_CIPWCC,
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},
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[2] = {
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.mask = 0x00004000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 1,
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.pri_reg = QEIC_CIPWCC,
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},
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[3] = {
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.mask = 0x00002000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 2,
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.pri_reg = QEIC_CIPWCC,
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},
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[10] = {
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.mask = 0x00000040,
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.mask_reg = QEIC_CIMR,
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.pri_code = 1,
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.pri_reg = QEIC_CIPZCC,
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},
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[11] = {
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.mask = 0x00000020,
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.mask_reg = QEIC_CIMR,
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.pri_code = 2,
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.pri_reg = QEIC_CIPZCC,
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},
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[12] = {
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.mask = 0x00000010,
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.mask_reg = QEIC_CIMR,
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.pri_code = 3,
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.pri_reg = QEIC_CIPZCC,
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},
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[13] = {
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.mask = 0x00000008,
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.mask_reg = QEIC_CIMR,
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.pri_code = 4,
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.pri_reg = QEIC_CIPZCC,
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},
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[14] = {
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.mask = 0x00000004,
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.mask_reg = QEIC_CIMR,
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.pri_code = 5,
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.pri_reg = QEIC_CIPZCC,
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},
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[15] = {
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.mask = 0x00000002,
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.mask_reg = QEIC_CIMR,
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.pri_code = 6,
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.pri_reg = QEIC_CIPZCC,
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},
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[20] = {
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.mask = 0x10000000,
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.mask_reg = QEIC_CRIMR,
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.pri_code = 3,
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.pri_reg = QEIC_CIPRTA,
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},
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[25] = {
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.mask = 0x00800000,
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.mask_reg = QEIC_CRIMR,
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.pri_code = 0,
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.pri_reg = QEIC_CIPRTB,
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},
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[26] = {
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.mask = 0x00400000,
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.mask_reg = QEIC_CRIMR,
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.pri_code = 1,
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.pri_reg = QEIC_CIPRTB,
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},
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[27] = {
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.mask = 0x00200000,
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.mask_reg = QEIC_CRIMR,
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.pri_code = 2,
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.pri_reg = QEIC_CIPRTB,
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},
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[28] = {
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.mask = 0x00100000,
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.mask_reg = QEIC_CRIMR,
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.pri_code = 3,
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.pri_reg = QEIC_CIPRTB,
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},
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[32] = {
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.mask = 0x80000000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 0,
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.pri_reg = QEIC_CIPXCC,
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},
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[33] = {
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.mask = 0x40000000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 1,
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.pri_reg = QEIC_CIPXCC,
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},
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[34] = {
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.mask = 0x20000000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 2,
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.pri_reg = QEIC_CIPXCC,
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},
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[35] = {
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.mask = 0x10000000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 3,
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.pri_reg = QEIC_CIPXCC,
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},
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[36] = {
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.mask = 0x08000000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 4,
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.pri_reg = QEIC_CIPXCC,
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},
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[40] = {
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.mask = 0x00800000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 0,
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.pri_reg = QEIC_CIPYCC,
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},
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[41] = {
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.mask = 0x00400000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 1,
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.pri_reg = QEIC_CIPYCC,
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},
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[42] = {
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.mask = 0x00200000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 2,
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.pri_reg = QEIC_CIPYCC,
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},
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[43] = {
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.mask = 0x00100000,
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.mask_reg = QEIC_CIMR,
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.pri_code = 3,
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.pri_reg = QEIC_CIPYCC,
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},
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};
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static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
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{
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return in_be32(base + (reg >> 2));
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}
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static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
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u32 value)
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{
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out_be32(base + (reg >> 2), value);
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}
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static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
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{
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return irq_get_chip_data(virq);
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}
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static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
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{
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return irq_data_get_irq_chip_data(d);
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}
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static void qe_ic_unmask_irq(struct irq_data *d)
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{
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struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
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unsigned int src = irqd_to_hwirq(d);
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unsigned long flags;
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u32 temp;
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raw_spin_lock_irqsave(&qe_ic_lock, flags);
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temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
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qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
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temp | qe_ic_info[src].mask);
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raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
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}
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static void qe_ic_mask_irq(struct irq_data *d)
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{
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struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
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unsigned int src = irqd_to_hwirq(d);
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unsigned long flags;
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u32 temp;
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raw_spin_lock_irqsave(&qe_ic_lock, flags);
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temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
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qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
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temp & ~qe_ic_info[src].mask);
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/* Flush the above write before enabling interrupts; otherwise,
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* spurious interrupts will sometimes happen. To be 100% sure
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* that the write has reached the device before interrupts are
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* enabled, the mask register would have to be read back; however,
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* this is not required for correctness, only to avoid wasting
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* time on a large number of spurious interrupts. In testing,
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* a sync reduced the observed spurious interrupts to zero.
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*/
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mb();
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raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
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}
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static struct irq_chip qe_ic_irq_chip = {
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.name = "QEIC",
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.irq_unmask = qe_ic_unmask_irq,
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.irq_mask = qe_ic_mask_irq,
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.irq_mask_ack = qe_ic_mask_irq,
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};
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static int qe_ic_host_match(struct irq_domain *h, struct device_node *node,
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enum irq_domain_bus_token bus_token)
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{
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/* Exact match, unless qe_ic node is NULL */
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struct device_node *of_node = irq_domain_get_of_node(h);
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return of_node == NULL || of_node == node;
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}
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static int qe_ic_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct qe_ic *qe_ic = h->host_data;
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struct irq_chip *chip;
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if (hw >= ARRAY_SIZE(qe_ic_info)) {
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pr_err("%s: Invalid hw irq number for QEIC\n", __func__);
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return -EINVAL;
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}
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if (qe_ic_info[hw].mask == 0) {
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printk(KERN_ERR "Can't map reserved IRQ\n");
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return -EINVAL;
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}
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/* Default chip */
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chip = &qe_ic->hc_irq;
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irq_set_chip_data(virq, qe_ic);
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_chip_and_handler(virq, chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops qe_ic_host_ops = {
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.match = qe_ic_host_match,
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.map = qe_ic_host_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
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unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
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{
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int irq;
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BUG_ON(qe_ic == NULL);
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/* get the interrupt source vector. */
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irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
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if (irq == 0)
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return NO_IRQ;
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return irq_linear_revmap(qe_ic->irqhost, irq);
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}
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/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
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unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
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{
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int irq;
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BUG_ON(qe_ic == NULL);
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/* get the interrupt source vector. */
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irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
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if (irq == 0)
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return NO_IRQ;
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return irq_linear_revmap(qe_ic->irqhost, irq);
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}
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void __init qe_ic_init(struct device_node *node, unsigned int flags,
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void (*low_handler)(struct irq_desc *desc),
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void (*high_handler)(struct irq_desc *desc))
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{
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struct qe_ic *qe_ic;
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struct resource res;
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u32 temp = 0, ret, high_active = 0;
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ret = of_address_to_resource(node, 0, &res);
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if (ret)
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return;
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qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
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if (qe_ic == NULL)
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return;
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qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
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&qe_ic_host_ops, qe_ic);
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if (qe_ic->irqhost == NULL) {
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kfree(qe_ic);
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return;
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}
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qe_ic->regs = ioremap(res.start, resource_size(&res));
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qe_ic->hc_irq = qe_ic_irq_chip;
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qe_ic->virq_high = irq_of_parse_and_map(node, 0);
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qe_ic->virq_low = irq_of_parse_and_map(node, 1);
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if (qe_ic->virq_low == NO_IRQ) {
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printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
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kfree(qe_ic);
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return;
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}
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/* default priority scheme is grouped. If spread mode is */
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/* required, configure cicr accordingly. */
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if (flags & QE_IC_SPREADMODE_GRP_W)
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temp |= CICR_GWCC;
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if (flags & QE_IC_SPREADMODE_GRP_X)
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temp |= CICR_GXCC;
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if (flags & QE_IC_SPREADMODE_GRP_Y)
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temp |= CICR_GYCC;
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if (flags & QE_IC_SPREADMODE_GRP_Z)
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temp |= CICR_GZCC;
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if (flags & QE_IC_SPREADMODE_GRP_RISCA)
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temp |= CICR_GRTA;
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if (flags & QE_IC_SPREADMODE_GRP_RISCB)
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temp |= CICR_GRTB;
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/* choose destination signal for highest priority interrupt */
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if (flags & QE_IC_HIGH_SIGNAL) {
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temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
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high_active = 1;
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}
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qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
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irq_set_handler_data(qe_ic->virq_low, qe_ic);
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irq_set_chained_handler(qe_ic->virq_low, low_handler);
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if (qe_ic->virq_high != NO_IRQ &&
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qe_ic->virq_high != qe_ic->virq_low) {
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irq_set_handler_data(qe_ic->virq_high, qe_ic);
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irq_set_chained_handler(qe_ic->virq_high, high_handler);
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}
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}
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void qe_ic_set_highest_priority(unsigned int virq, int high)
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{
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struct qe_ic *qe_ic = qe_ic_from_irq(virq);
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unsigned int src = virq_to_hw(virq);
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u32 temp = 0;
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temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
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temp &= ~CICR_HP_MASK;
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temp |= src << CICR_HP_SHIFT;
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temp &= ~CICR_HPIT_MASK;
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temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
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qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
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}
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/* Set Priority level within its group, from 1 to 8 */
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int qe_ic_set_priority(unsigned int virq, unsigned int priority)
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{
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struct qe_ic *qe_ic = qe_ic_from_irq(virq);
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unsigned int src = virq_to_hw(virq);
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u32 temp;
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if (priority > 8 || priority == 0)
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return -EINVAL;
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if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
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"%s: Invalid hw irq number for QEIC\n", __func__))
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return -EINVAL;
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if (qe_ic_info[src].pri_reg == 0)
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return -EINVAL;
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temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
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if (priority < 4) {
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temp &= ~(0x7 << (32 - priority * 3));
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temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
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} else {
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temp &= ~(0x7 << (24 - priority * 3));
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temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
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}
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qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
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return 0;
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}
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/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
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int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
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{
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struct qe_ic *qe_ic = qe_ic_from_irq(virq);
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unsigned int src = virq_to_hw(virq);
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u32 temp, control_reg = QEIC_CICNR, shift = 0;
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if (priority > 2 || priority == 0)
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return -EINVAL;
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if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
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"%s: Invalid hw irq number for QEIC\n", __func__))
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return -EINVAL;
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switch (qe_ic_info[src].pri_reg) {
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case QEIC_CIPZCC:
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shift = CICNR_ZCC1T_SHIFT;
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break;
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case QEIC_CIPWCC:
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shift = CICNR_WCC1T_SHIFT;
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break;
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case QEIC_CIPYCC:
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shift = CICNR_YCC1T_SHIFT;
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break;
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case QEIC_CIPXCC:
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shift = CICNR_XCC1T_SHIFT;
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break;
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case QEIC_CIPRTA:
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shift = CRICR_RTA1T_SHIFT;
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control_reg = QEIC_CRICR;
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break;
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case QEIC_CIPRTB:
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shift = CRICR_RTB1T_SHIFT;
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control_reg = QEIC_CRICR;
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break;
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default:
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return -EINVAL;
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}
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shift += (2 - priority) * 2;
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temp = qe_ic_read(qe_ic->regs, control_reg);
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temp &= ~(SIGNAL_MASK << shift);
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temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
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qe_ic_write(qe_ic->regs, control_reg, temp);
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return 0;
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}
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static struct bus_type qe_ic_subsys = {
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.name = "qe_ic",
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.dev_name = "qe_ic",
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};
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|
|
static struct device device_qe_ic = {
|
|
.id = 0,
|
|
.bus = &qe_ic_subsys,
|
|
};
|
|
|
|
static int __init init_qe_ic_sysfs(void)
|
|
{
|
|
int rc;
|
|
|
|
printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
|
|
|
|
rc = subsys_system_register(&qe_ic_subsys, NULL);
|
|
if (rc) {
|
|
printk(KERN_ERR "Failed registering qe_ic sys class\n");
|
|
return -ENODEV;
|
|
}
|
|
rc = device_register(&device_qe_ic);
|
|
if (rc) {
|
|
printk(KERN_ERR "Failed registering qe_ic sys device\n");
|
|
return -ENODEV;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
subsys_initcall(init_qe_ic_sysfs);
|