379 lines
8.8 KiB
C
Executable file
379 lines
8.8 KiB
C
Executable file
/*
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* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/kobject.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include <soc/tegra/common.h>
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#include <soc/tegra/fuse.h>
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#include "fuse.h"
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struct tegra_sku_info tegra_sku_info;
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EXPORT_SYMBOL(tegra_sku_info);
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static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
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[TEGRA_REVISION_UNKNOWN] = "unknown",
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[TEGRA_REVISION_A01] = "A01",
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[TEGRA_REVISION_A02] = "A02",
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[TEGRA_REVISION_A03] = "A03",
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[TEGRA_REVISION_A03p] = "A03 prime",
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[TEGRA_REVISION_A04] = "A04",
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};
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static u8 fuse_readb(struct tegra_fuse *fuse, unsigned int offset)
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{
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u32 val;
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val = fuse->read(fuse, round_down(offset, 4));
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val >>= (offset % 4) * 8;
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val &= 0xff;
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return val;
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}
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static ssize_t fuse_read(struct file *fd, struct kobject *kobj,
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struct bin_attribute *attr, char *buf,
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loff_t pos, size_t size)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct tegra_fuse *fuse = dev_get_drvdata(dev);
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int i;
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if (pos < 0 || pos >= attr->size)
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return 0;
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if (size > attr->size - pos)
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size = attr->size - pos;
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for (i = 0; i < size; i++)
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buf[i] = fuse_readb(fuse, pos + i);
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return i;
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}
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static struct bin_attribute fuse_bin_attr = {
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.attr = { .name = "fuse", .mode = S_IRUGO, },
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.read = fuse_read,
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};
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static int tegra_fuse_create_sysfs(struct device *dev, unsigned int size,
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const struct tegra_fuse_info *info)
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{
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fuse_bin_attr.size = size;
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return device_create_bin_file(dev, &fuse_bin_attr);
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}
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static const struct of_device_id car_match[] __initconst = {
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{ .compatible = "nvidia,tegra20-car", },
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{ .compatible = "nvidia,tegra30-car", },
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{ .compatible = "nvidia,tegra114-car", },
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{ .compatible = "nvidia,tegra124-car", },
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{ .compatible = "nvidia,tegra132-car", },
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{ .compatible = "nvidia,tegra210-car", },
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{},
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};
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static struct tegra_fuse *fuse = &(struct tegra_fuse) {
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.base = NULL,
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.soc = NULL,
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};
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static const struct of_device_id tegra_fuse_match[] = {
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#ifdef CONFIG_ARCH_TEGRA_186_SOC
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{ .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_210_SOC
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{ .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_132_SOC
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{ .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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{ .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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{ .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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{ .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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{ .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
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#endif
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{ /* sentinel */ }
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};
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static int tegra_fuse_probe(struct platform_device *pdev)
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{
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void __iomem *base = fuse->base;
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struct resource *res;
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int err;
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/* take over the memory region from the early initialization */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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fuse->phys = res->start;
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fuse->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(fuse->base)) {
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err = PTR_ERR(fuse->base);
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fuse->base = base;
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return err;
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}
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fuse->clk = devm_clk_get(&pdev->dev, "fuse");
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if (IS_ERR(fuse->clk)) {
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dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
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PTR_ERR(fuse->clk));
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fuse->base = base;
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return PTR_ERR(fuse->clk);
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}
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platform_set_drvdata(pdev, fuse);
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fuse->dev = &pdev->dev;
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if (fuse->soc->probe) {
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err = fuse->soc->probe(fuse);
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if (err < 0) {
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fuse->base = base;
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return err;
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}
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}
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if (tegra_fuse_create_sysfs(&pdev->dev, fuse->soc->info->size,
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fuse->soc->info))
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return -ENODEV;
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/* release the early I/O memory mapping */
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iounmap(base);
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return 0;
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}
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static struct platform_driver tegra_fuse_driver = {
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.driver = {
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.name = "tegra-fuse",
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.of_match_table = tegra_fuse_match,
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.suppress_bind_attrs = true,
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},
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.probe = tegra_fuse_probe,
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};
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builtin_platform_driver(tegra_fuse_driver);
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bool __init tegra_fuse_read_spare(unsigned int spare)
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{
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unsigned int offset = fuse->soc->info->spare + spare * 4;
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return fuse->read_early(fuse, offset) & 1;
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}
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u32 __init tegra_fuse_read_early(unsigned int offset)
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{
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return fuse->read_early(fuse, offset);
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}
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int tegra_fuse_readl(unsigned long offset, u32 *value)
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{
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if (!fuse->read)
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return -EPROBE_DEFER;
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*value = fuse->read(fuse, offset);
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return 0;
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}
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EXPORT_SYMBOL(tegra_fuse_readl);
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static void tegra_enable_fuse_clk(void __iomem *base)
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{
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u32 reg;
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reg = readl_relaxed(base + 0x48);
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reg |= 1 << 28;
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writel(reg, base + 0x48);
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/*
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* Enable FUSE clock. This needs to be hardcoded because the clock
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* subsystem is not active during early boot.
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*/
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reg = readl(base + 0x14);
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reg |= 1 << 7;
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writel(reg, base + 0x14);
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}
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struct device * __init tegra_soc_device_register(void)
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{
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struct soc_device_attribute *attr;
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struct soc_device *dev;
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attr = kzalloc(sizeof(*attr), GFP_KERNEL);
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if (!attr)
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return NULL;
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attr->family = kasprintf(GFP_KERNEL, "Tegra");
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attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_sku_info.revision);
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attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
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dev = soc_device_register(attr);
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if (IS_ERR(dev)) {
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kfree(attr->soc_id);
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kfree(attr->revision);
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kfree(attr->family);
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kfree(attr);
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return ERR_CAST(dev);
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}
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return soc_device_to_device(dev);
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}
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static int __init tegra_init_fuse(void)
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{
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const struct of_device_id *match;
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struct device_node *np;
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struct resource regs;
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tegra_init_apbmisc();
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np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
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if (!np) {
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/*
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* Fall back to legacy initialization for 32-bit ARM only. All
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* 64-bit ARM device tree files for Tegra are required to have
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* a FUSE node.
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*
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* This is for backwards-compatibility with old device trees
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* that didn't contain a FUSE node.
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*/
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if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
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u8 chip = tegra_get_chip_id();
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regs.start = 0x7000f800;
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regs.end = 0x7000fbff;
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regs.flags = IORESOURCE_MEM;
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switch (chip) {
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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case TEGRA20:
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fuse->soc = &tegra20_fuse_soc;
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break;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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case TEGRA30:
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fuse->soc = &tegra30_fuse_soc;
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break;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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case TEGRA114:
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fuse->soc = &tegra114_fuse_soc;
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break;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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case TEGRA124:
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fuse->soc = &tegra124_fuse_soc;
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break;
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#endif
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default:
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pr_warn("Unsupported SoC: %02x\n", chip);
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break;
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}
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} else {
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/*
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* At this point we're not running on Tegra, so play
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* nice with multi-platform kernels.
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*/
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return 0;
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}
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} else {
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/*
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* Extract information from the device tree if we've found a
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* matching node.
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*/
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if (of_address_to_resource(np, 0, ®s) < 0) {
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pr_err("failed to get FUSE register\n");
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return -ENXIO;
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}
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fuse->soc = match->data;
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}
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np = of_find_matching_node(NULL, car_match);
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if (np) {
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void __iomem *base = of_iomap(np, 0);
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if (base) {
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tegra_enable_fuse_clk(base);
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iounmap(base);
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} else {
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pr_err("failed to map clock registers\n");
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return -ENXIO;
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}
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}
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fuse->base = ioremap_nocache(regs.start, resource_size(®s));
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if (!fuse->base) {
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pr_err("failed to map FUSE registers\n");
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return -ENXIO;
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}
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fuse->soc->init(fuse);
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pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
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tegra_revision_name[tegra_sku_info.revision],
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tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
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tegra_sku_info.soc_process_id);
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pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
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tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
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return 0;
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}
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early_initcall(tegra_init_fuse);
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#ifdef CONFIG_ARM64
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static int __init tegra_init_soc(void)
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{
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struct device_node *np;
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struct device *soc;
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/* make sure we're running on Tegra */
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np = of_find_matching_node(NULL, tegra_fuse_match);
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if (!np)
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return 0;
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of_node_put(np);
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soc = tegra_soc_device_register();
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if (IS_ERR(soc)) {
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pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc));
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return PTR_ERR(soc);
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}
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return 0;
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}
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device_initcall(tegra_init_soc);
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#endif
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