152 lines
3.5 KiB
C
Executable file
152 lines
3.5 KiB
C
Executable file
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2011, 2012 Cavium, Inc.
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*/
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#include <linux/spi/spi.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "spi-cavium.h"
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static void octeon_spi_wait_ready(struct octeon_spi *p)
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{
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union cvmx_mpi_sts mpi_sts;
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unsigned int loops = 0;
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do {
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if (loops++)
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__delay(500);
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mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS(p));
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} while (mpi_sts.s.busy);
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}
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static int octeon_spi_do_transfer(struct octeon_spi *p,
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struct spi_message *msg,
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struct spi_transfer *xfer,
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bool last_xfer)
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{
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struct spi_device *spi = msg->spi;
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union cvmx_mpi_cfg mpi_cfg;
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union cvmx_mpi_tx mpi_tx;
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unsigned int clkdiv;
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int mode;
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bool cpha, cpol;
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const u8 *tx_buf;
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u8 *rx_buf;
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int len;
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int i;
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mode = spi->mode;
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cpha = mode & SPI_CPHA;
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cpol = mode & SPI_CPOL;
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clkdiv = p->sys_freq / (2 * xfer->speed_hz);
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mpi_cfg.u64 = 0;
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mpi_cfg.s.clkdiv = clkdiv;
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mpi_cfg.s.cshi = (mode & SPI_CS_HIGH) ? 1 : 0;
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mpi_cfg.s.lsbfirst = (mode & SPI_LSB_FIRST) ? 1 : 0;
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mpi_cfg.s.wireor = (mode & SPI_3WIRE) ? 1 : 0;
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mpi_cfg.s.idlelo = cpha != cpol;
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mpi_cfg.s.cslate = cpha ? 1 : 0;
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mpi_cfg.s.enable = 1;
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if (spi->chip_select < 4)
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p->cs_enax |= 1ull << (12 + spi->chip_select);
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mpi_cfg.u64 |= p->cs_enax;
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if (mpi_cfg.u64 != p->last_cfg) {
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p->last_cfg = mpi_cfg.u64;
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writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p));
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}
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tx_buf = xfer->tx_buf;
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rx_buf = xfer->rx_buf;
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len = xfer->len;
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while (len > OCTEON_SPI_MAX_BYTES) {
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for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
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u8 d;
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if (tx_buf)
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d = *tx_buf++;
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else
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d = 0;
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writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
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}
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mpi_tx.u64 = 0;
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mpi_tx.s.csid = spi->chip_select;
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mpi_tx.s.leavecs = 1;
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mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
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mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
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writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));
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octeon_spi_wait_ready(p);
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if (rx_buf)
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for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
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u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
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*rx_buf++ = (u8)v;
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}
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len -= OCTEON_SPI_MAX_BYTES;
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}
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for (i = 0; i < len; i++) {
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u8 d;
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if (tx_buf)
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d = *tx_buf++;
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else
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d = 0;
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writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
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}
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mpi_tx.u64 = 0;
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mpi_tx.s.csid = spi->chip_select;
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if (last_xfer)
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mpi_tx.s.leavecs = xfer->cs_change;
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else
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mpi_tx.s.leavecs = !xfer->cs_change;
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mpi_tx.s.txnum = tx_buf ? len : 0;
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mpi_tx.s.totnum = len;
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writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));
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octeon_spi_wait_ready(p);
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if (rx_buf)
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for (i = 0; i < len; i++) {
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u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
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*rx_buf++ = (u8)v;
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}
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if (xfer->delay_usecs)
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udelay(xfer->delay_usecs);
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return xfer->len;
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}
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int octeon_spi_transfer_one_message(struct spi_master *master,
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struct spi_message *msg)
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{
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struct octeon_spi *p = spi_master_get_devdata(master);
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unsigned int total_len = 0;
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int status = 0;
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struct spi_transfer *xfer;
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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bool last_xfer = list_is_last(&xfer->transfer_list,
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&msg->transfers);
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int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer);
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if (r < 0) {
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status = r;
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goto err;
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}
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total_len += r;
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}
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err:
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msg->status = status;
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msg->actual_length = total_len;
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spi_finalize_current_message(master);
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return status;
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}
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