128 lines
4.5 KiB
C
Executable file
128 lines
4.5 KiB
C
Executable file
/*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __XEN_PUBLIC_HVM_PARAMS_H__
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#define __XEN_PUBLIC_HVM_PARAMS_H__
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#include <xen/interface/hvm/hvm_op.h>
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/*
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* Parameter space for HVMOP_{set,get}_param.
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*/
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#define HVM_PARAM_CALLBACK_IRQ 0
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/*
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* How should CPU0 event-channel notifications be delivered?
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*
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* If val == 0 then CPU0 event-channel notifications are not delivered.
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* If val != 0, val[63:56] encodes the type, as follows:
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*/
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#define HVM_PARAM_CALLBACK_TYPE_GSI 0
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/*
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* val[55:0] is a delivery GSI. GSI 0 cannot be used, as it aliases val == 0,
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* and disables all notifications.
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*/
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#define HVM_PARAM_CALLBACK_TYPE_PCI_INTX 1
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/*
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* val[55:0] is a delivery PCI INTx line:
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* Domain = val[47:32], Bus = val[31:16] DevFn = val[15:8], IntX = val[1:0]
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#define HVM_PARAM_CALLBACK_TYPE_VECTOR 2
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/*
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* val[7:0] is a vector number. Check for XENFEAT_hvm_callback_vector to know
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* if this delivery method is available.
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*/
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#elif defined(__arm__) || defined(__aarch64__)
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#define HVM_PARAM_CALLBACK_TYPE_PPI 2
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/*
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* val[55:16] needs to be zero.
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* val[15:8] is interrupt flag of the PPI used by event-channel:
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* bit 8: the PPI is edge(1) or level(0) triggered
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* bit 9: the PPI is active low(1) or high(0)
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* val[7:0] is a PPI number used by event-channel.
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* This is only used by ARM/ARM64 and masking/eoi the interrupt associated to
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* the notification is handled by the interrupt controller.
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*/
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#endif
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#define HVM_PARAM_STORE_PFN 1
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#define HVM_PARAM_STORE_EVTCHN 2
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#define HVM_PARAM_PAE_ENABLED 4
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#define HVM_PARAM_IOREQ_PFN 5
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#define HVM_PARAM_BUFIOREQ_PFN 6
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/*
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* Set mode for virtual timers (currently x86 only):
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* delay_for_missed_ticks (default):
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* Do not advance a vcpu's time beyond the correct delivery time for
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* interrupts that have been missed due to preemption. Deliver missed
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* interrupts when the vcpu is rescheduled and advance the vcpu's virtual
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* time stepwise for each one.
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* no_delay_for_missed_ticks:
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* As above, missed interrupts are delivered, but guest time always tracks
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* wallclock (i.e., real) time while doing so.
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* no_missed_ticks_pending:
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* No missed interrupts are held pending. Instead, to ensure ticks are
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* delivered at some non-zero rate, if we detect missed ticks then the
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* internal tick alarm is not disabled if the VCPU is preempted during the
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* next tick period.
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* one_missed_tick_pending:
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* Missed interrupts are collapsed together and delivered as one 'late tick'.
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* Guest time always tracks wallclock (i.e., real) time.
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*/
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#define HVM_PARAM_TIMER_MODE 10
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#define HVMPTM_delay_for_missed_ticks 0
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#define HVMPTM_no_delay_for_missed_ticks 1
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#define HVMPTM_no_missed_ticks_pending 2
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#define HVMPTM_one_missed_tick_pending 3
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/* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
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#define HVM_PARAM_HPET_ENABLED 11
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/* Identity-map page directory used by Intel EPT when CR0.PG=0. */
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#define HVM_PARAM_IDENT_PT 12
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/* Device Model domain, defaults to 0. */
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#define HVM_PARAM_DM_DOMAIN 13
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/* ACPI S state: currently support S0 and S3 on x86. */
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#define HVM_PARAM_ACPI_S_STATE 14
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/* TSS used on Intel when CR0.PE=0. */
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#define HVM_PARAM_VM86_TSS 15
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/* Boolean: Enable aligning all periodic vpts to reduce interrupts */
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#define HVM_PARAM_VPT_ALIGN 16
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/* Console debug shared memory ring and event channel */
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#define HVM_PARAM_CONSOLE_PFN 17
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#define HVM_PARAM_CONSOLE_EVTCHN 18
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#define HVM_NR_PARAMS 19
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#endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */
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