320 lines
11 KiB
C
Executable file
320 lines
11 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ALSA SoC ES7243E adc driver
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*
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* Author: David Yang, <yangxiaohua@everest-semi.com>
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* or
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* <info@everest-semi.com>
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* Copyright: (C) 2019 Everest Semiconductor Co Ltd.,
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*
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* Based on sound/soc/codecs/es7243.c by DavidYang
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Notes:
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* this is an important file, you need to check it before you use ES7243E.
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* es7243e_usr_cfg.h is a user interface which is convenient for digital
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* format, clock ratio, etc.
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*
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*/
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#define ES7243E_RESET 0x00 /* RESET circuit */
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#define ES7243E_CLK1 0x01 /* CLOCK MANAGER */
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#define ES7243E_CLK2 0x02 /* CLOCK MANAGER */
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#define ES7243E_ADC_OSR 0x03 /*ADC Over Sample Rate control */
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#define ES7243E_PREDIV 0x04 /*MCLK Pre-multiplication and divider */
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#define ES7243E_CLK_DIV 0x05 /*CF&DSP clock divider */
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#define ES7243E_BCLK_DIV 0x06 /*BCLK divider at master mode */
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#define ES7243E_CLK_TRI 0x07 /*Tri-state control and Master LRCK divider */
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#define ES7243E_LRCK_DIV 0x08 /*Master LRCK divider */
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#define ES7243E_S1_SEL 0x09 /*state machine 1 select */
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#define ES7243E_S3_SEL 0x0A /*state machine 3 select */
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#define ES7243E_SDP_FORMAT 0x0B /*SDP formate and word length */
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#define ES7243E_TDM 0x0C /*TDM_MODE TDM_FLAG */
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#define ES7243E_ADCCTL1 0x0D /*ADC gain scale up ADC data mux */
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#define ES7243E_ADC_VOL 0x0E /*ADC volume control */
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#define ES7243E_ADCCTL2 0x0F /*ADC VC ramp rate */
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#define ES7243E_AUTOMUTE1 0x10 /*ADC automute noise gate and window size */
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#define ES7243E_AUTOMUTE2 0x11 /*ADC automute SDP control */
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#define ES7243E_AUTOMUTE3 0x12 /*ADC automute control */
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#define ES7243E_AUTOMUTE4 0x13 /*ALC rate selection, ALC target level */
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#define ES7243E_ADC_HPF1 0x14 /*ADCHPF stage1 coeff */
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#define ES7243E_ADC_HPF2 0x15 /*ADCHPF stage2 coeff */
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#define ES7243E_ANALOG_PDN 0x16 /*powerdown analog & PGA */
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#define ES7243E_VMIDSEL 0x17 /*select VMID */
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#define ES7243E_ADC_BIAS_0x18 0x18 /*ADC BIAS_SW */
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#define ES7243E_PGA_BIAS 0x19 /*PGA BIAS_SW */
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#define ES7243E_ADC_BIAS_0x1A 0x1A /*ADC I1BIAS_SW */
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#define ES7243E_ADC_MICBIAS 0x1B /*ADC MBIAS_SW */
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#define ES7243E_ADC_VRPBIAS 0x1C /*ADC VRPBIAS_SW */
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#define ES7243E_ADC_LP 0x1D /*ADC low power select */
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#define ES7243E_ADC_PGA_LP 0x1E /*PGA low power select */
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#define ES7243E_ADC_VMID 0x1F /*VMIDLVL select */
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#define ES7243E_PGA1 0x20 /*PGA1 gain, input */
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#define ES7243E_PGA2 0x21 /*PGA2 gain, input */
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#define ES7243E_TESTMOD_0xF7 0xF7 /* */
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#define ES7243E_TESTMOD_0xF8 0xF8 /* */
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#define ES7243E_DLL_PWN 0xF9 /*DLL_PWD */
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#define ES7243E_I2C_CONFIG 0xFC /*I2C signals retime */
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#define ES7243E_FLAG 0xFA /*CSM & ADC automute flag */
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#define ES7243E_CHIPID1 0xFD /*chip ID1 */
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#define ES7243E_CHIPID2 0xFE /*chip ID2 */
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#define ES7243E_CHIP_VER 0xFF /*chip versoin */
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#define ENABLE 1
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#define DISABLE 0
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/*
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* Here is the definition of ES7243E ADC Digital Format
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* Users must select correct digital format for their systerm.
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*
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* ES7243E_WORK_MODE is used to select digital format, and user must update it for their system
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* In ES7243E codec driver (es7243e.c), ES7243E_WORK_MODE will be used for digital format setting.
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*
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* In normal mode, ES7243E supports four digital formats including I2S, LJ, DSP-A and DSP-B, with
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* resolution from 16bits to 32bits.
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* In TDM mode, ES7243E only supports DSP-A TDM, doesn't support DSP-B TDM.
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* In NFS mode, ES7243E only supports NFS I2S mode, doesn't support DSP or LJ NFS mode.
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*/
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#define ES7243E_NORMAL_I2S 0
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#define ES7243E_NORMAL_LJ 1
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#define ES7243E_NORMAL_DSPA 2
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#define ES7243E_NORMAL_DSPB 3
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#define ES7243E_TDM_A 4
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#define ES7243E_NFS_I2S 5
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#define ES7243E_NFS_DSPA 6
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#define ES7243E_WORK_MODE ES7243E_NORMAL_I2S
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/*
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* Here is the definition of the common MCLK/LRCK rato.
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* ES7243E will have different register configuration for each MCLK/LRCK ratio.
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* Please check the MCLK/LRCK ratio in your system before you update ES7243E_MCLK_LRCK_RATIO.
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* ES7243E codec driver will configure the clock registers according to the value of ES7243E_MCLK_LRCK_RATO.
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*/
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#define RATIO_3072 3072
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#define RATIO_2048 2048
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#define RATIO_1536 1536
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#define RATIO_1024 1024
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#define RATIO_768 768
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#define RATIO_512 512
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#define RATIO_384 384
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#define RATIO_256 256
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#define RATIO_192 192
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#define RATIO_128 128
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#define RATIO_64 64
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#define ES7243E_MCLK_LRCK_RATIO RATIO_64
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/*
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* To select the total analog input channel for microphone array
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*/
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#define AIN_2_CH 2
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#define AIN_4_CH 4
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#define AIN_6_CH 6
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#define AIN_8_CH 8
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#define AIN_10_CH 10
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#define AIN_12_CH 12
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#define AIN_14_CH 14
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#define AIN_16_CH 16
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#define ES7243E_CHANNELS_MAX AIN_2_CH
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/*
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* to select the clock soure for internal MCLK clock
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*/
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#define FROM_MCLK_PIN 0
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#define FROM_INTERNAL_BCLK 1
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#define ES7243E_MCLK_SOURCE FROM_INTERNAL_BCLK
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/*
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* to select the data length or resolution
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*/
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#define DATA_16BITS 0
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#define DATA_24BITS 1
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#define DATA_32BITS 2
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#define ES7243E_DATA_LENGTH DATA_32BITS
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/*
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* to select the pdm digital microphone interface
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*/
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#define DMIC_INTERFACE_ON false
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#define DMIC_INTERFACE_OFF true
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#define DMIC_INTERFACE DMIC_INTERFACE_OFF
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/*
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* to select bclk inverted or not
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*/
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#define BCLK_NORMAL false
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#define BCLK_INVERTED true
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#define BCLK_INVERTED_OR_NOT BCLK_NORMAL
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/*
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* to select mclk inverted or not
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*/
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#define MCLK_NORMAL false
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#define MCLK_INVERTED true
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#define MCLK_INVERTED_OR_NOT MCLK_NORMAL
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/*
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* to select PGA gain for different analog input channel
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* user must allocate the PGA gain for each analog input channel
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* ES7243E_MIC_ARRAY_AIN1_PGA to ES7243E_MIC_ARRAY_AIN16_PGA is used for PGA gain
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*/
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#define PGA_0DB 0
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#define PGA_3DB 1
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#define PGA_6DB 2
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#define PGA_9DB 3
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#define PGA_12DB 4
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#define PGA_15DB 5
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#define PGA_18DB 6
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#define PGA_21DB 7
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#define PGA_24DB 8
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#define PGA_27DB 9
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#define PGA_30DB 10
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#define PGA_33DB 11
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#define PGA_34DB 12
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#define PGA_36DB 13
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#define PGA_37DB 14
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#if ES7243E_CHANNELS_MAX > 0
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#define ES7243E_MIC_ARRAY_AIN1_PGA PGA_27DB
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#define ES7243E_MIC_ARRAY_AIN2_PGA PGA_27DB
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#endif
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#if ES7243E_CHANNELS_MAX > 2
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#define ES7243E_MIC_ARRAY_AIN3_PGA PGA_33DB
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#define ES7243E_MIC_ARRAY_AIN4_PGA PGA_33DB
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#endif
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#if ES7243E_CHANNELS_MAX > 4
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#define ES7243E_MIC_ARRAY_AIN5_PGA PGA_33DB
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#define ES7243E_MIC_ARRAY_AIN6_PGA PGA_33DB
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#endif
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#if ES7243E_CHANNELS_MAX > 6
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#define ES7243E_MIC_ARRAY_AIN7_PGA PGA_0DB
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#define ES7243E_MIC_ARRAY_AIN8_PGA PGA_0DB
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#endif
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#if ES7243E_CHANNELS_MAX > 8
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#define ES7243E_MIC_ARRAY_AIN9_PGA PGA_33DB
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#define ES7243E_MIC_ARRAY_AIN10_PGA PGA_33DB
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#endif
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#if ES7243E_CHANNELS_MAX > 10
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#define ES7243E_MIC_ARRAY_AIN11_PGA PGA_33DB
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#define ES7243E_MIC_ARRAY_AIN12_PGA PGA_33DB
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#endif
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#if ES7243E_CHANNELS_MAX > 12
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#define ES7243E_MIC_ARRAY_AIN13_PGA PGA_33DB
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#define ES7243E_MIC_ARRAY_AIN14_PGA PGA_33DB
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#endif
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#if ES7243E_CHANNELS_MAX > 14
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#define ES7243E_MIC_ARRAY_AIN15_PGA PGA_33DB
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#define ES7243E_MIC_ARRAY_AIN16_PGA PGA_33DB
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#endif
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/*
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* here is the definition of digital volume.
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* the digital volume is 0dB by default. User can update it
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* ES7243E_DIGITAL_VOLUME_1 to ES7243E_DIGITAL_VOLUME_16 is used for digital volume
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* digital volume is 0db default.
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*/
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#if ES7243E_CHANNELS_MAX > 0
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#define DIG_VOL_1 0 // DB
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#define ES7243E_DIGITAL_VOLUME_1 0xbf + (DIG_VOL_1 * 2)
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#define DIG_VOL_2 0 // DB
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#define ES7243E_DIGITAL_VOLUME_2 0xbf + (DIG_VOL_2 * 2)
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#endif
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#if ES7243E_CHANNELS_MAX > 2
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#define DIG_VOL_3 0 // DB
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#define ES7243E_DIGITAL_VOLUME_3 0xbf + (DIG_VOL_3 * 2)
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#define DIG_VOL_4 0 // DB
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#define ES7243E_DIGITAL_VOLUME_4 0xbf + (DIG_VOL_4 * 2)
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#endif
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#if ES7243E_CHANNELS_MAX > 4
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#define DIG_VOL_5 0 // DB
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#define ES7243E_DIGITAL_VOLUME_5 0xbf + (DIG_VOL_5 * 2)
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#define DIG_VOL_6 0 // DB
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#define ES7243E_DIGITAL_VOLUME_6 0xbf + (DIG_VOL_6 * 2)
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#endif
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#if ES7243E_CHANNELS_MAX > 6
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#define DIG_VOL_7 0 // DB
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#define ES7243E_DIGITAL_VOLUME_7 0xbf + (DIG_VOL_7 * 2)
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#define DIG_VOL_8 0 // DB
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#define ES7243E_DIGITAL_VOLUME_8 0xbf + (DIG_VOL_8 * 2)
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#endif
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#if ES7243E_CHANNELS_MAX > 8
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#define DIG_VOL_9 0 // DB
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#define ES7243E_DIGITAL_VOLUME_9 0xbf + (DIG_VOL_9 * 2)
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#define DIG_VOL_10 0 // DB
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#define ES7243E_DIGITAL_VOLUME_10 0xbf + (DIG_VOL_10 * 2)
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#endif
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#if ES7243E_CHANNELS_MAX > 10
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#define DIG_VOL_11 0 // DB
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#define ES7243E_DIGITAL_VOLUME_11 0xbf + (DIG_VOL_11 * 2)
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#define DIG_VOL_12 0 // DB
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#define ES7243E_DIGITAL_VOLUME_12 0xbf + (DIG_VOL_12 * 2)
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#endif
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#if ES7243E_CHANNELS_MAX > 12
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#define DIG_VOL_13 0 // DB
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#define ES7243E_DIGITAL_VOLUME_13 0xbf + (DIG_VOL_13 * 2)
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#define DIG_VOL_14 0 // DB
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#define ES7243E_DIGITAL_VOLUME_14 0xbf + (DIG_VOL_14 * 2)
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#endif
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#if ES7243E_CHANNELS_MAX > 14
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#define DIG_VOL_15 0 // DB
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#define ES7243E_DIGITAL_VOLUME_15 0xbf + (DIG_VOL_15 * 2)
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#define DIG_VOL_16 0 // DB
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#define ES7243E_DIGITAL_VOLUME_16 0xbf + (DIG_VOL_16 * 2)
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#endif
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/*
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* set the I2C chip address for each es7243e device in TDM linkloop
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* user can update the chip address according their system circuit
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*/
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#define I2C_CHIP_ADDR_10H 0x10 // AD0 and AD1 pulled down, ASDOUT pulled down or float
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#define I2C_CHIP_ADDR_11H 0x11 // AD0 pulled up, AD1 pulled down, ASDOUT pulled down or float
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#define I2C_CHIP_ADDR_12H 0x12 // AD0 pulled down, AD1 pulled up, ASDOUT pulled down or float
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#define I2C_CHIP_ADDR_13H 0x13 // AD0 and AD1 pulled up, ASDOUT pulled down or float
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#define I2C_CHIP_ADDR_14H 0x14 // AD0 and AD1 pulled down, ASDOUT pulled up
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#define I2C_CHIP_ADDR_15H 0x15 // AD0 pulled up, AD1 pulled down, ASDOUT pulled up
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#define I2C_CHIP_ADDR_16H 0x16 // AD0 pulled down, AD1 pulled up, ASDOUT pulled up
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#define I2C_CHIP_ADDR_17H 0x17 // AD0 and AD1 pulled up, ASDOUT pulled up
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#if ES7243E_CHANNELS_MAX > 0
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#define ES7243E_I2C_CHIP_ADDRESS_0 I2C_CHIP_ADDR_10H
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#endif
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#if ES7243E_CHANNELS_MAX > 2
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#define ES7243E_I2C_CHIP_ADDRESS_1 I2C_CHIP_ADDR_13H
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#endif
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#if ES7243E_CHANNELS_MAX > 4
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#define ES7243E_I2C_CHIP_ADDRESS_2 I2C_CHIP_ADDR_12H
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#endif
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#if ES7243E_CHANNELS_MAX > 6
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#define ES7243E_I2C_CHIP_ADDRESS_3 I2C_CHIP_ADDR_11H
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#endif
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#if ES7243E_CHANNELS_MAX > 8
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#define ES7243E_I2C_CHIP_ADDRESS_4 I2C_CHIP_ADDR_14H
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#endif
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#if ES7243E_CHANNELS_MAX > 10
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#define ES7243E_I2C_CHIP_ADDRESS_5 I2C_CHIP_ADDR_15H
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#endif
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#if ES7243E_CHANNELS_MAX > 12
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#define ES7243E_I2C_CHIP_ADDRESS_6 I2C_CHIP_ADDR_16H
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#endif
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#if ES7243E_CHANNELS_MAX > 14
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#define ES7243E_I2C_CHIP_ADDRESS_7 I2C_CHIP_ADDR_17H
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#endif
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#define ES7243E_I2C_BUS_NUM 3
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#define ES7243E_CODEC_RW_TEST_EN 0
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#define ES7243E_IDLE_RESET_EN 1 //reset ES7243 when in idle time
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#define ES7243E_MATCH_DTS_EN 1 //ES7243 match method select: 0: i2c_detect, 1:of_device_id
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#define VDDA_1V8 1
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#define VDDA_3V3 0
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#define VDDA_VOLTAGE VDDA_1V8
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