294 lines
8.9 KiB
C
Executable file
294 lines
8.9 KiB
C
Executable file
/*
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* Intel Smart Sound Technology (SST) Core
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*
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* Copyright (C) 2013, Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __SOUND_SOC_SST_DSP_H
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#define __SOUND_SOC_SST_DSP_H
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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/* SST Device IDs */
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#define SST_DEV_ID_LYNX_POINT 0x33C8
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#define SST_DEV_ID_WILDCAT_POINT 0x3438
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#define SST_DEV_ID_BYT 0x0F28
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/* Supported SST DMA Devices */
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#define SST_DMA_TYPE_DW 1
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/* autosuspend delay 5s*/
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#define SST_RUNTIME_SUSPEND_DELAY (5 * 1000)
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/* SST Shim register map
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* The register naming can differ between products. Some products also
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* contain extra functionality.
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*/
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#define SST_CSR 0x00
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#define SST_PISR 0x08
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#define SST_PIMR 0x10
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#define SST_ISRX 0x18
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#define SST_ISRD 0x20
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#define SST_IMRX 0x28
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#define SST_IMRD 0x30
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#define SST_IPCX 0x38 /* IPC IA -> SST */
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#define SST_IPCD 0x40 /* IPC SST -> IA */
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#define SST_ISRSC 0x48
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#define SST_ISRLPESC 0x50
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#define SST_IMRSC 0x58
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#define SST_IMRLPESC 0x60
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#define SST_IPCSC 0x68
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#define SST_IPCLPESC 0x70
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#define SST_CLKCTL 0x78
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#define SST_CSR2 0x80
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#define SST_LTRC 0xE0
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#define SST_HMDC 0xE8
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#define SST_SHIM_BEGIN SST_CSR
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#define SST_SHIM_END SST_HDMC
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#define SST_DBGO 0xF0
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#define SST_SHIM_SIZE 0x100
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#define SST_PWMCTRL 0x1000
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/* SST Shim Register bits
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* The register bit naming can differ between products. Some products also
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* contain extra functionality.
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*/
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/* CSR / CS */
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#define SST_CSR_RST (0x1 << 1)
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#define SST_CSR_SBCS0 (0x1 << 2)
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#define SST_CSR_SBCS1 (0x1 << 3)
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#define SST_CSR_DCS(x) (x << 4)
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#define SST_CSR_DCS_MASK (0x7 << 4)
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#define SST_CSR_STALL (0x1 << 10)
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#define SST_CSR_S0IOCS (0x1 << 21)
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#define SST_CSR_S1IOCS (0x1 << 23)
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#define SST_CSR_LPCS (0x1 << 31)
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#define SST_CSR_24MHZ_LPCS (SST_CSR_SBCS0 | SST_CSR_SBCS1 | SST_CSR_LPCS)
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#define SST_CSR_24MHZ_NO_LPCS (SST_CSR_SBCS0 | SST_CSR_SBCS1)
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#define SST_BYT_CSR_RST (0x1 << 0)
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#define SST_BYT_CSR_VECTOR_SEL (0x1 << 1)
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#define SST_BYT_CSR_STALL (0x1 << 2)
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#define SST_BYT_CSR_PWAITMODE (0x1 << 3)
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/* ISRX / ISC */
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#define SST_ISRX_BUSY (0x1 << 1)
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#define SST_ISRX_DONE (0x1 << 0)
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#define SST_BYT_ISRX_REQUEST (0x1 << 1)
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/* ISRD / ISD */
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#define SST_ISRD_BUSY (0x1 << 1)
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#define SST_ISRD_DONE (0x1 << 0)
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/* IMRX / IMC */
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#define SST_IMRX_BUSY (0x1 << 1)
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#define SST_IMRX_DONE (0x1 << 0)
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#define SST_BYT_IMRX_REQUEST (0x1 << 1)
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/* IMRD / IMD */
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#define SST_IMRD_DONE (0x1 << 0)
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#define SST_IMRD_BUSY (0x1 << 1)
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#define SST_IMRD_SSP0 (0x1 << 16)
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#define SST_IMRD_DMAC0 (0x1 << 21)
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#define SST_IMRD_DMAC1 (0x1 << 22)
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#define SST_IMRD_DMAC (SST_IMRD_DMAC0 | SST_IMRD_DMAC1)
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/* IPCX / IPCC */
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#define SST_IPCX_DONE (0x1 << 30)
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#define SST_IPCX_BUSY (0x1 << 31)
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#define SST_BYT_IPCX_DONE ((u64)0x1 << 62)
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#define SST_BYT_IPCX_BUSY ((u64)0x1 << 63)
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/* IPCD */
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#define SST_IPCD_DONE (0x1 << 30)
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#define SST_IPCD_BUSY (0x1 << 31)
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#define SST_BYT_IPCD_DONE ((u64)0x1 << 62)
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#define SST_BYT_IPCD_BUSY ((u64)0x1 << 63)
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/* CLKCTL */
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#define SST_CLKCTL_SMOS(x) (x << 24)
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#define SST_CLKCTL_MASK (3 << 24)
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#define SST_CLKCTL_DCPLCG (1 << 18)
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#define SST_CLKCTL_SCOE1 (1 << 17)
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#define SST_CLKCTL_SCOE0 (1 << 16)
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/* CSR2 / CS2 */
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#define SST_CSR2_SDFD_SSP0 (1 << 1)
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#define SST_CSR2_SDFD_SSP1 (1 << 2)
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/* LTRC */
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#define SST_LTRC_VAL(x) (x << 0)
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/* HMDC */
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#define SST_HMDC_HDDA0(x) (x << 0)
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#define SST_HMDC_HDDA1(x) (x << 7)
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#define SST_HMDC_HDDA_E0_CH0 1
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#define SST_HMDC_HDDA_E0_CH1 2
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#define SST_HMDC_HDDA_E0_CH2 4
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#define SST_HMDC_HDDA_E0_CH3 8
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#define SST_HMDC_HDDA_E1_CH0 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH0)
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#define SST_HMDC_HDDA_E1_CH1 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH1)
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#define SST_HMDC_HDDA_E1_CH2 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH2)
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#define SST_HMDC_HDDA_E1_CH3 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH3)
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#define SST_HMDC_HDDA_E0_ALLCH (SST_HMDC_HDDA_E0_CH0 | SST_HMDC_HDDA_E0_CH1 | \
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SST_HMDC_HDDA_E0_CH2 | SST_HMDC_HDDA_E0_CH3)
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#define SST_HMDC_HDDA_E1_ALLCH (SST_HMDC_HDDA_E1_CH0 | SST_HMDC_HDDA_E1_CH1 | \
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SST_HMDC_HDDA_E1_CH2 | SST_HMDC_HDDA_E1_CH3)
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/* SST Vendor Defined Registers and bits */
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#define SST_VDRTCTL0 0xa0
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#define SST_VDRTCTL1 0xa4
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#define SST_VDRTCTL2 0xa8
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#define SST_VDRTCTL3 0xaC
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/* VDRTCTL0 */
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#define SST_VDRTCL0_D3PGD (1 << 0)
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#define SST_VDRTCL0_D3SRAMPGD (1 << 1)
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#define SST_VDRTCL0_DSRAMPGE_SHIFT 12
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#define SST_VDRTCL0_DSRAMPGE_MASK (0xfffff << SST_VDRTCL0_DSRAMPGE_SHIFT)
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#define SST_VDRTCL0_ISRAMPGE_SHIFT 2
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#define SST_VDRTCL0_ISRAMPGE_MASK (0x3ff << SST_VDRTCL0_ISRAMPGE_SHIFT)
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/* VDRTCTL2 */
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#define SST_VDRTCL2_DCLCGE (1 << 1)
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#define SST_VDRTCL2_DTCGE (1 << 10)
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#define SST_VDRTCL2_APLLSE_MASK (1 << 31)
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/* PMCS */
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#define SST_PMCS 0x84
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#define SST_PMCS_PS_MASK 0x3
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struct sst_dsp;
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/*
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* SST Device.
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*
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* This structure is populated by the SST core driver.
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*/
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struct sst_dsp_device {
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/* Mandatory fields */
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struct sst_ops *ops;
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irqreturn_t (*thread)(int irq, void *context);
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void *thread_context;
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};
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/*
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* SST Platform Data.
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*/
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struct sst_pdata {
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/* ACPI data */
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u32 lpe_base;
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u32 lpe_size;
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u32 pcicfg_base;
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u32 pcicfg_size;
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u32 fw_base;
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u32 fw_size;
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int irq;
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/* Firmware */
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const struct firmware *fw;
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/* DMA */
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int resindex_dma_base; /* other fields invalid if equals to -1 */
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u32 dma_base;
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u32 dma_size;
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int dma_engine;
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struct device *dma_dev;
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/* DSP */
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u32 id;
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void *dsp;
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};
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#if IS_ENABLED(CONFIG_DW_DMAC_CORE)
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/* Initialization */
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struct sst_dsp *sst_dsp_new(struct device *dev,
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struct sst_dsp_device *sst_dev, struct sst_pdata *pdata);
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void sst_dsp_free(struct sst_dsp *sst);
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#endif
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/* SHIM Read / Write */
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void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value);
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u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset);
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int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
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u32 mask, u32 value);
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void sst_dsp_shim_write64(struct sst_dsp *sst, u32 offset, u64 value);
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u64 sst_dsp_shim_read64(struct sst_dsp *sst, u32 offset);
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int sst_dsp_shim_update_bits64(struct sst_dsp *sst, u32 offset,
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u64 mask, u64 value);
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void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
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u32 mask, u32 value);
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/* SHIM Read / Write Unlocked for callers already holding sst lock */
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void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value);
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u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset);
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int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
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u32 mask, u32 value);
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void sst_dsp_shim_write64_unlocked(struct sst_dsp *sst, u32 offset, u64 value);
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u64 sst_dsp_shim_read64_unlocked(struct sst_dsp *sst, u32 offset);
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int sst_dsp_shim_update_bits64_unlocked(struct sst_dsp *sst, u32 offset,
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u64 mask, u64 value);
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void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset,
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u32 mask, u32 value);
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/* Internal generic low-level SST IO functions - can be overidden */
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void sst_shim32_write(void __iomem *addr, u32 offset, u32 value);
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u32 sst_shim32_read(void __iomem *addr, u32 offset);
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void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value);
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u64 sst_shim32_read64(void __iomem *addr, u32 offset);
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void sst_memcpy_toio_32(struct sst_dsp *sst,
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void __iomem *dest, void *src, size_t bytes);
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void sst_memcpy_fromio_32(struct sst_dsp *sst,
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void *dest, void __iomem *src, size_t bytes);
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/* DSP reset & boot */
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void sst_dsp_reset(struct sst_dsp *sst);
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int sst_dsp_boot(struct sst_dsp *sst);
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int sst_dsp_wake(struct sst_dsp *sst);
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void sst_dsp_sleep(struct sst_dsp *sst);
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void sst_dsp_stall(struct sst_dsp *sst);
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/* DMA */
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int sst_dsp_dma_get_channel(struct sst_dsp *dsp, int chan_id);
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void sst_dsp_dma_put_channel(struct sst_dsp *dsp);
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int sst_dsp_dma_copyfrom(struct sst_dsp *sst, dma_addr_t dest_addr,
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dma_addr_t src_addr, size_t size);
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int sst_dsp_dma_copyto(struct sst_dsp *sst, dma_addr_t dest_addr,
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dma_addr_t src_addr, size_t size);
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/* Msg IO */
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void sst_dsp_ipc_msg_tx(struct sst_dsp *dsp, u32 msg);
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u32 sst_dsp_ipc_msg_rx(struct sst_dsp *dsp);
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/* Mailbox management */
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int sst_dsp_mailbox_init(struct sst_dsp *dsp, u32 inbox_offset,
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size_t inbox_size, u32 outbox_offset, size_t outbox_size);
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void sst_dsp_inbox_write(struct sst_dsp *dsp, void *message, size_t bytes);
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void sst_dsp_inbox_read(struct sst_dsp *dsp, void *message, size_t bytes);
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void sst_dsp_outbox_write(struct sst_dsp *dsp, void *message, size_t bytes);
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void sst_dsp_outbox_read(struct sst_dsp *dsp, void *message, size_t bytes);
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void sst_dsp_mailbox_dump(struct sst_dsp *dsp, size_t bytes);
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int sst_dsp_register_poll(struct sst_dsp *dsp, u32 offset, u32 mask,
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u32 expected_value, u32 timeout, char *operation);
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/* Debug */
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void sst_dsp_dump(struct sst_dsp *sst);
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#endif
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