268 lines
13 KiB
C
Executable file
268 lines
13 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Michael Hsiao <michael.hsiao@mediatek.com>
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*/
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/******************************************************************************
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*
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* Filename:
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* ---------
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* AudDrv_Ana.h
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*
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* Project:
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* --------
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* MT6797 Audio Driver Ana
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*
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* Description:
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* ------------
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* Audio register
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*
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* Author:
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* -------
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* Chipeng Chang (mtk02308)
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*
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*-----------------------------------------------------------------------------
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*
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*
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*****************************************************************************/
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#ifndef _AUDDRV_ANA_H_
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#define _AUDDRV_ANA_H_
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/*****************************************************************************
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* C O M P I L E R F L A G S
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*****************************************************************************/
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/*****************************************************************************
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* E X T E R N A L R E F E R E N C E S
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*****************************************************************************/
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#include "mtk-auddrv-def.h"
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#include "mtk-soc-analog-type.h"
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/*****************************************************************************
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* D A T A T Y P E S
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*****************************************************************************/
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/*****************************************************************************
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* M A C R O
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*****************************************************************************/
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/*****************************************************************************
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* R E G I S T E R D E F I N I T I O N
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*****************************************************************************/
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#define PMIC_REG_BASE (0x0)
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#define AUD_PMIC_REG_BASE (0x0+0x2080)
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#define AUD_TOP_ID ((unsigned int)(AUD_PMIC_REG_BASE+0x0000))
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#define AUD_TOP_REV0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0002))
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#define AUD_TOP_REV1 ((unsigned int)(AUD_PMIC_REG_BASE+0x0004))
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#define AUD_TOP_DXI ((unsigned int)(AUD_PMIC_REG_BASE+0x0006))
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#define AUD_TOP_CKPDN_PM0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0008))
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#define AUD_TOP_CKPDN_PM1 ((unsigned int)(AUD_PMIC_REG_BASE+0x000A))
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#ifdef AUD_TOP_CKPDN_CON0
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#undef AUD_TOP_CKPDN_CON0
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#endif
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#define AUD_TOP_CKPDN_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x000C))
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#define AUD_TOP_CKPDN_CON0_SET ((unsigned int)(AUD_PMIC_REG_BASE+0x000E))
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#define AUD_TOP_CKPDN_CON0_CLR ((unsigned int)(AUD_PMIC_REG_BASE+0x0010))
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#define AUD_TOP_CKSEL_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0012))
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#define AUD_TOP_CKSEL_CON0_SET ((unsigned int)(AUD_PMIC_REG_BASE+0x0014))
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#ifdef AUD_TOP_RST_CON0
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#undef AUD_TOP_RST_CON0
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#endif
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#define AUD_TOP_CKSEL_CON0_CLR ((unsigned int)(AUD_PMIC_REG_BASE+0x0016))
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#define AUD_TOP_CKTST_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0018))
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#ifdef AUD_TOP_INT_CON0
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#undef AUD_TOP_INT_CON0
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#endif
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#define AUD_TOP_RST_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x001A))
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#ifdef AUD_TOP_INT_CON0_SET
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#undef AUD_TOP_INT_CON0_SET
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#endif
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#define AUD_TOP_RST_CON0_SET ((unsigned int)(AUD_PMIC_REG_BASE+0x001C))
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#ifdef AUD_TOP_INT_CON0_CLR
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#undef AUD_TOP_INT_CON0_CLR
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#endif
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#define AUD_TOP_RST_CON0_CLR ((unsigned int)(AUD_PMIC_REG_BASE+0x001E))
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#ifdef AUD_TOP_INT_MASK_CON0
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#undef AUD_TOP_INT_MASK_CON0
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#endif
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#define AUD_TOP_RST_BANK_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0020))
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#define AUD_TOP_INT_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0022))
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#define AUD_TOP_INT_CON0_SET ((unsigned int)(AUD_PMIC_REG_BASE+0x0024))
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#define AUD_TOP_INT_CON0_CLR ((unsigned int)(AUD_PMIC_REG_BASE+0x0026))
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#define AUD_TOP_INT_MASK_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0028))
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#ifdef AUD_TOP_INT_MASK_CON0_SET
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#undef AUD_TOP_INT_MASK_CON0_SET
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#endif
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#define AUD_TOP_INT_MASK_CON0_SET ((unsigned int)(AUD_PMIC_REG_BASE+0x002A))
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#ifdef AUD_TOP_INT_MASK_CON0_CLR
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#undef AUD_TOP_INT_MASK_CON0_CLR
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#endif
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#define AUD_TOP_INT_MASK_CON0_CLR ((unsigned int)(AUD_PMIC_REG_BASE+0x002C))
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#ifdef AUD_TOP_INT_STATUS0
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#undef AUD_TOP_INT_STATUS0
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#endif
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#define AUD_TOP_INT_STATUS0 ((unsigned int)(AUD_PMIC_REG_BASE+0x002E))
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#define AUD_TOP_INT_RAW_STATUS0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0030))
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#define AUD_TOP_INT_MISC_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0032))
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#define AUDNCP_CLKDIV_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0034))
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#define AUDNCP_CLKDIV_CON1 ((unsigned int)(AUD_PMIC_REG_BASE+0x0036))
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#define AUDNCP_CLKDIV_CON2 ((unsigned int)(AUD_PMIC_REG_BASE+0x0038))
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#define AUDNCP_CLKDIV_CON3 ((unsigned int)(AUD_PMIC_REG_BASE+0x003A))
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#define AUDNCP_CLKDIV_CON4 ((unsigned int)(AUD_PMIC_REG_BASE+0x003C))
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#define AUD_TOP_MON_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x003E))
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#define AUDIO_DIG_ID ((unsigned int)(PMIC_REG_BASE + 0x1580))
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#define AUDIO_DIG_REV0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0082))
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#define AUDIO_DIG_REV1 ((unsigned int)(AUD_PMIC_REG_BASE+0x0084))
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#define AUDIO_DIG_DSN_DXI ((unsigned int)(AUD_PMIC_REG_BASE+0x0086))
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#define AFE_UL_DL_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0088))
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#define AFE_DL_SRC2_CON0_L ((unsigned int)(AUD_PMIC_REG_BASE+0x008A))
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#define AFE_UL_SRC_CON0_H ((unsigned int)(AUD_PMIC_REG_BASE+0x008C))
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#define AFE_UL_SRC_CON0_L ((unsigned int)(AUD_PMIC_REG_BASE+0x008E))
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#define PMIC_AFE_TOP_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0090))
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#define PMIC_AUDIO_TOP_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0092))
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#define AFE_MON_DEBUG0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0094))
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#define AFUNC_AUD_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0096))
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#define AFUNC_AUD_CON1 ((unsigned int)(AUD_PMIC_REG_BASE+0x0098))
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#define AFUNC_AUD_CON2 ((unsigned int)(AUD_PMIC_REG_BASE+0x009A))
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#define AFUNC_AUD_CON3 ((unsigned int)(AUD_PMIC_REG_BASE+0x009C))
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#define AFUNC_AUD_CON4 ((unsigned int)(AUD_PMIC_REG_BASE+0x009E))
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#define AFUNC_AUD_CON5 ((unsigned int)(AUD_PMIC_REG_BASE+0x00A0))
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#define AFUNC_AUD_CON6 ((unsigned int)(AUD_PMIC_REG_BASE+0x00A2))
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#define AFUNC_AUD_MON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x00A4))
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#define AUDRC_TUNE_MON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x00A6))
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#define AFE_ADDA_MTKAIF_FIFO_CFG0 ((unsigned int)(AUD_PMIC_REG_BASE+0x00A8))
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#define AFE_ADDA_MTKAIF_FIFO_LOG_MON1 ((unsigned int)(AUD_PMIC_REG_BASE+0x00AA))
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#define PMIC_AFE_ADDA_MTKAIF_MON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x00AC))
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#define PMIC_AFE_ADDA_MTKAIF_MON1 ((unsigned int)(AUD_PMIC_REG_BASE+0x00AE))
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#define PMIC_AFE_ADDA_MTKAIF_MON2 ((unsigned int)(AUD_PMIC_REG_BASE+0x00B0))
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#define PMIC_AFE_ADDA_MTKAIF_MON3 ((unsigned int)(AUD_PMIC_REG_BASE+0x00B2))
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#define PMIC_AFE_ADDA_MTKAIF_CFG0 ((unsigned int)(AUD_PMIC_REG_BASE+0x00B4))
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#define PMIC_AFE_ADDA_MTKAIF_RX_CFG0 ((unsigned int)(AUD_PMIC_REG_BASE+0x00B6))
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#define PMIC_AFE_ADDA_MTKAIF_RX_CFG1 ((unsigned int)(AUD_PMIC_REG_BASE+0x00B8))
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#define PMIC_AFE_ADDA_MTKAIF_RX_CFG2 ((unsigned int)(AUD_PMIC_REG_BASE+0x00BA))
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#define PMIC_AFE_ADDA_MTKAIF_RX_CFG3 ((unsigned int)(AUD_PMIC_REG_BASE+0x00BC))
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#define PMIC_AFE_ADDA_MTKAIF_TX_CFG1 ((unsigned int)(AUD_PMIC_REG_BASE+0x00BE))
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#define AFE_SGEN_CFG0 ((unsigned int)(AUD_PMIC_REG_BASE+0x00C0))
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#define AFE_SGEN_CFG1 ((unsigned int)(AUD_PMIC_REG_BASE+0x00C2))
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#define AFE_ADC_ASYNC_FIFO_CFG ((unsigned int)(AUD_PMIC_REG_BASE+0x00C4))
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#define AFE_DCCLK_CFG0 ((unsigned int)(AUD_PMIC_REG_BASE+0x00C6))
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#define AFE_DCCLK_CFG1 ((unsigned int)(AUD_PMIC_REG_BASE+0x00C8))
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#define AUDIO_DIG_CFG ((unsigned int)(AUD_PMIC_REG_BASE+0x00CA))
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#define AFE_AUD_PAD_TOP ((unsigned int)(AUD_PMIC_REG_BASE+0x00CC))
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#define AFE_AUD_PAD_TOP_MON ((unsigned int)(AUD_PMIC_REG_BASE+0x00CE))
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#define AFE_AUD_PAD_TOP_MON1 ((unsigned int)(AUD_PMIC_REG_BASE+0x00D0))
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#define AUDENC_DSN_ID ((unsigned int)(AUD_PMIC_REG_BASE+0x0100))
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#define AUDENC_DSN_REV0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0102))
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#define AUDENC_DSN_REV1 ((unsigned int)(AUD_PMIC_REG_BASE+0x0104))
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#define AUDENC_DSN_FPI ((unsigned int)(AUD_PMIC_REG_BASE+0x0106))
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#define AUDENC_ANA_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0108))
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#define AUDENC_ANA_CON1 ((unsigned int)(AUD_PMIC_REG_BASE+0x010A))
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#define AUDENC_ANA_CON2 ((unsigned int)(AUD_PMIC_REG_BASE+0x010C))
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#define AUDENC_ANA_CON3 ((unsigned int)(AUD_PMIC_REG_BASE+0x010E))
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#define AUDENC_ANA_CON4 ((unsigned int)(AUD_PMIC_REG_BASE+0x0110))
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#define AUDENC_ANA_CON5 ((unsigned int)(AUD_PMIC_REG_BASE+0x0112))
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#ifdef AUDENC_ANA_CON6
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#undef AUDENC_ANA_CON6
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#endif
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#define AUDENC_ANA_CON6 ((unsigned int)(AUD_PMIC_REG_BASE+0x0114))
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#define AUDENC_ANA_CON7 ((unsigned int)(AUD_PMIC_REG_BASE+0x0116))
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#define AUDENC_ANA_CON8 ((unsigned int)(AUD_PMIC_REG_BASE+0x0118))
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#ifdef AUDENC_ANA_CON9
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#undef AUDENC_ANA_CON9
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#endif
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#define AUDENC_ANA_CON9 ((unsigned int)(AUD_PMIC_REG_BASE+0x011A))
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#ifdef AUDENC_ANA_CON10
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#undef AUDENC_ANA_CON10
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#endif
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#define AUDENC_ANA_CON10 ((unsigned int)(AUD_PMIC_REG_BASE+0x011C))
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#ifdef AUDENC_ANA_CON11
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#undef AUDENC_ANA_CON11
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#endif
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#define AUDENC_ANA_CON11 ((unsigned int)(AUD_PMIC_REG_BASE+0x011E))
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#define AUDDEC_DSN_ID ((unsigned int)(AUD_PMIC_REG_BASE+0x0180))
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#define AUDDEC_DSN_REV0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0182))
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#define AUDDEC_DSN_REV1 ((unsigned int)(AUD_PMIC_REG_BASE+0x0184))
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#define AUDDEC_DSN_FPI ((unsigned int)(AUD_PMIC_REG_BASE+0x0186))
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#define AUDDEC_ANA_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0188))
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#define AUDDEC_ANA_CON1 ((unsigned int)(AUD_PMIC_REG_BASE+0x018A))
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#define AUDDEC_ANA_CON2 ((unsigned int)(AUD_PMIC_REG_BASE+0x018C))
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#define AUDDEC_ANA_CON3 ((unsigned int)(AUD_PMIC_REG_BASE+0x018E))
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#define AUDDEC_ANA_CON4 ((unsigned int)(AUD_PMIC_REG_BASE+0x0190))
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#define AUDDEC_ANA_CON5 ((unsigned int)(AUD_PMIC_REG_BASE+0x0192))
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#define AUDDEC_ANA_CON6 ((unsigned int)(AUD_PMIC_REG_BASE+0x0194))
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#define AUDDEC_ANA_CON7 ((unsigned int)(AUD_PMIC_REG_BASE+0x0196))
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#define AUDDEC_ANA_CON8 ((unsigned int)(AUD_PMIC_REG_BASE+0x0198))
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#define AUDDEC_ANA_CON9 ((unsigned int)(AUD_PMIC_REG_BASE+0x019A))
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#define AUDDEC_ANA_CON10 ((unsigned int)(AUD_PMIC_REG_BASE+0x019C))
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#define AUDDEC_ANA_CON11 ((unsigned int)(AUD_PMIC_REG_BASE+0x019E))
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#define AUDDEC_ANA_CON12 ((unsigned int)(AUD_PMIC_REG_BASE+0x01A0))
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#define AUDDEC_ANA_CON13 ((unsigned int)(AUD_PMIC_REG_BASE+0x01A2))
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#define AUDDEC_ELR_NUM ((unsigned int)(AUD_PMIC_REG_BASE+0x01A4))
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#define AUDDEC_ELR_0 ((unsigned int)(AUD_PMIC_REG_BASE+0x01A6))
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#define AUDZCDID ((unsigned int)(AUD_PMIC_REG_BASE+0x0200))
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#define AUDZCDREV0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0202))
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#define AUDZCDREV1 ((unsigned int)(AUD_PMIC_REG_BASE+0x0204))
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#define AUDZCD_DSN_FPI ((unsigned int)(AUD_PMIC_REG_BASE+0x0206))
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#define ZCD_CON0 ((unsigned int)(AUD_PMIC_REG_BASE+0x0208))
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#define ZCD_CON1 ((unsigned int)(AUD_PMIC_REG_BASE+0x020A))
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#define ZCD_CON2 ((unsigned int)(AUD_PMIC_REG_BASE+0x020C))
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#define ZCD_CON3 ((unsigned int)(AUD_PMIC_REG_BASE+0x020E))
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#define ZCD_CON4 ((unsigned int)(AUD_PMIC_REG_BASE+0x0210))
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#define ZCD_CON5 ((unsigned int)(AUD_PMIC_REG_BASE+0x0212))
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#ifdef TOP_CKPDN_CON0
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#undef TOP_CKPDN_CON0
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#endif
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#define TOP_CKPDN_CON0 ((unsigned int)(PMIC_REG_BASE+0x0000+0x010C))
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#ifdef TOP_CKPDN_CON0_SET
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#undef TOP_CKPDN_CON0_SET
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#endif
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#define TOP_CKPDN_CON0_SET ((unsigned int)(PMIC_REG_BASE+0x0000+0x010E))
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#ifdef TOP_CKPDN_CON0_CLR
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#undef TOP_CKPDN_CON0_CLR
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#endif
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#define TOP_CKPDN_CON0_CLR ((unsigned int)(PMIC_REG_BASE+0x0000+0x0110))
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#define TOP_CKHWEN_CON0 ((unsigned int)(PMIC_REG_BASE+0x0000+0x012A))
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#define TOP_CKHWEN_CON0_SET ((unsigned int)(PMIC_REG_BASE+0x0000+0x012C))
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#define TOP_CKHWEN_CON0_CLR ((unsigned int)(PMIC_REG_BASE+0x0000+0x012E))
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#define OTP_CON0 ((unsigned int)(PMIC_REG_BASE+0x0380+0x0010))
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#define OTP_CON8 ((unsigned int)(PMIC_REG_BASE+0x0380+0x0020))
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#define OTP_CON11 ((unsigned int)(PMIC_REG_BASE+0x0380+0x0026))
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#define OTP_CON12 ((unsigned int)(PMIC_REG_BASE+0x0380+0x0028))
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#define OTP_CON13 ((unsigned int)(PMIC_REG_BASE+0x0380+0x002A))
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#define DRV_CON3 ((unsigned int)(PMIC_REG_BASE+0x0000+0x0038))
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#define GPIO_DIR0 ((unsigned int)(PMIC_REG_BASE+0x0000+0x0088))
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/* mosi */
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#define GPIO_MODE2 ((unsigned int)(PMIC_REG_BASE+0x0000+0x00B6))
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#define GPIO_MODE2_SET ((unsigned int)(PMIC_REG_BASE+0x0000+0x00B8))
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#define GPIO_MODE2_CLR ((unsigned int)(PMIC_REG_BASE+0x0000+0x00BA))
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#define SMT_CON1 ((unsigned int)(PMIC_REG_BASE+0x0000+0x002c))
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/* miso */
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#define GPIO_MODE3 ((unsigned int)(PMIC_REG_BASE+0x0000+0x00BC))
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#define GPIO_MODE3_SET ((unsigned int)(PMIC_REG_BASE+0x0000+0x00BE))
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#define GPIO_MODE3_CLR ((unsigned int)(PMIC_REG_BASE+0x0000+0x00C0))
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#define DCXO_CW14 ((unsigned int)(PMIC_REG_BASE+0x0780+0x002C))
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#define AUXADC_CON10 ((unsigned int)(PMIC_REG_BASE+0x0F80+0x01B8))
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void Ana_Set_Reg(unsigned int offset, unsigned int value, unsigned int mask);
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unsigned int Ana_Get_Reg(unsigned int offset);
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/* for debug usage */
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void Ana_Log_Print(void);
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int Ana_Debug_Read(char *buffer, const int size);
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int mt63xx_set_local_priv(struct mt6357_priv *priv);
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#endif
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