771 lines
20 KiB
C
Executable file
771 lines
20 KiB
C
Executable file
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Michael Hsiao <michael.hsiao@mediatek.com>
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*/
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/*******************************************************************************
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*
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* Filename:
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* ---------
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* mt_soc_pcm_afe.c
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*
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* Project:
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* --------
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* Audio Driver Kernel Function
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*
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* Description:
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* ------------
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* Audio dl1 data1 playback
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*
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* Author:
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* -------
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* Chipeng Chang
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*
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*------------------------------------------------------------------------------
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*
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******************************************************************************
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*/
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/*****************************************************************************
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* C O M P I L E R F L A G S
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*****************************************************************************/
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/*****************************************************************************
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* E X T E R N A L R E F E R E N C E S
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*****************************************************************************/
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#include "mtk-auddrv-afe.h"
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#include "mtk-auddrv-ana.h"
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#include "mtk-auddrv-clk.h"
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#include "mtk-auddrv-common.h"
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#include "mtk-auddrv-def.h"
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#include "mtk-auddrv-gpio.h"
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#include "mtk-auddrv-kernel.h"
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#include "mtk-soc-afe-control.h"
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#include "mtk-soc-pcm-common.h"
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#include "mtk-soc-pcm-platform.h"
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#include "mtk-auddrv-gpio.h"
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#include <asm/div64.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/fs.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/miscdevice.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/proc_fs.h>
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#include <linux/sched.h>
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#include <linux/semaphore.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/uaccess.h>
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#include <linux/vmalloc.h>
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#include <linux/wait.h>
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#include <sound/core.h>
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#include <sound/soc.h>
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#include <sound/pcm_params.h>
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#include <sound/soc-dapm.h>
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#ifdef CONFIG_OF
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#endif
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static struct afe_mem_control_t *pMemControl;
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static unsigned int mPlaybackDramState;
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static struct snd_dma_buffer *Dl1_Playback_dma_buf;
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static DEFINE_SPINLOCK(auddrv_DLCtl_lock);
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static struct device *mDev;
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/*
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* function implementation
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*/
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/*void StartAudioPcmHardware(void);*/
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/*void StopAudioPcmHardware(void);*/
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static int mtk_soc_dl1_probe(struct platform_device *pdev);
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static int mtk_soc_pcm_dl1_close(struct snd_pcm_substream *substream);
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static int mtk_asoc_dl1_component_probe(struct snd_soc_component *component);
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static bool mPrepareDone;
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#define USE_RATE (SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000)
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#define USE_RATE_MIN 8000
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#define USE_RATE_MAX 192000
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#define USE_CHANNELS_MIN 1
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#define USE_CHANNELS_MAX 2
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#define USE_PERIODS_MIN 512
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#define USE_PERIODS_MAX 8192
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static struct snd_pcm_hardware mtk_pcm_dl1_hardware = {
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.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
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.formats = SND_SOC_ADV_MT_FMTS,
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.rates = SOC_HIGH_USE_RATE,
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.rate_min = SOC_HIGH_USE_RATE_MIN,
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.rate_max = SOC_HIGH_USE_RATE_MAX,
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.channels_min = SOC_NORMAL_USE_CHANNELS_MIN,
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.channels_max = SOC_NORMAL_USE_CHANNELS_MAX,
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.buffer_bytes_max = Dl1_MAX_BUFFER_SIZE,
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.period_bytes_max = Dl1_MAX_PERIOD_SIZE,
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.periods_min = SOC_NORMAL_USE_PERIODS_MIN,
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.periods_max = SOC_NORMAL_USE_PERIODS_MAX,
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.fifo_size = 0,
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};
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static int mtk_pcm_dl1_stop(struct snd_pcm_substream *substream)
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{
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pr_debug("%s\n", __func__);
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irq_remove_user(substream,
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irq_request_number(Soc_Aud_Digital_Block_MEM_DL1));
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SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, false);
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/* here start digital part */
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SetIntfConnection(Soc_Aud_InterCon_DisConnect,
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Soc_Aud_AFE_IO_Block_MEM_DL1,
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Soc_Aud_AFE_IO_Block_I2S1_DAC);
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SetIntfConnection(Soc_Aud_InterCon_DisConnect,
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Soc_Aud_AFE_IO_Block_MEM_DL1,
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Soc_Aud_AFE_IO_Block_I2S1_DAC_2);
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ClearMemBlock(Soc_Aud_Digital_Block_MEM_DL1);
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return 0;
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}
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static snd_pcm_uframes_t mtk_pcm_pointer(struct snd_pcm_substream *substream)
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{
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return get_mem_frame_index(substream, pMemControl,
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Soc_Aud_Digital_Block_MEM_DL1);
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}
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static int mtk_pcm_dl1_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *hw_params)
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{
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/* struct snd_dma_buffer *dma_buf = &substream->dma_buffer; */
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int ret = 0;
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/* runtime->dma_bytes has to be set manually to allow mmap */
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substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
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if (AllocateAudioSram(&substream->runtime->dma_addr,
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&substream->runtime->dma_area,
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substream->runtime->dma_bytes, substream,
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params_format(hw_params), false) == 0) {
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SetHighAddr(Soc_Aud_Digital_Block_MEM_DL1, false,
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substream->runtime->dma_addr);
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} else {
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substream->runtime->dma_area = Dl1_Playback_dma_buf->area;
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substream->runtime->dma_addr = Dl1_Playback_dma_buf->addr;
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SetHighAddr(Soc_Aud_Digital_Block_MEM_DL1, true,
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substream->runtime->dma_addr);
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mPlaybackDramState = true;
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AudDrv_Emi_Clk_On();
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}
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set_mem_block(substream, hw_params, pMemControl,
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Soc_Aud_Digital_Block_MEM_DL1);
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#if defined(DL1_DEBUG_LOG)
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pr_debug("dma_bytes = %zu dma_area = %p dma_addr = 0x%lx\n",
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substream->runtime->dma_bytes,
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substream->runtime->dma_area,
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(long)substream->runtime->dma_addr);
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#endif
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return ret;
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}
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static int mtk_pcm_dl1_hw_free(struct snd_pcm_substream *substream)
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{
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pr_debug("%s substream = %p\n", __func__, substream);
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if (mPlaybackDramState == true) {
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AudDrv_Emi_Clk_Off();
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mPlaybackDramState = false;
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} else
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freeAudioSram((void *)substream);
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return 0;
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}
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static struct snd_pcm_hw_constraint_list constraints_sample_rates = {
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.count = ARRAY_SIZE(soc_high_supported_sample_rates),
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.list = soc_high_supported_sample_rates,
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.mask = 0,
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};
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static int mtk_pcm_dl1_open(struct snd_pcm_substream *substream)
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{
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int ret = 0;
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struct snd_pcm_runtime *runtime = substream->runtime;
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mPlaybackDramState = false;
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mtk_pcm_dl1_hardware.buffer_bytes_max = GetPLaybackSramFullSize();
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pr_debug("mtk_pcm_dl1_hardware.buffer_bytes_max = %zu mPlaybackDramState = %d\n",
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mtk_pcm_dl1_hardware.buffer_bytes_max, mPlaybackDramState);
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runtime->hw = mtk_pcm_dl1_hardware;
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AudDrv_Clk_On();
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memcpy((void *)(&(runtime->hw)), (void *)&mtk_pcm_dl1_hardware,
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sizeof(struct snd_pcm_hardware));
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pMemControl = Get_Mem_ControlT(Soc_Aud_Digital_Block_MEM_DL1);
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ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
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&constraints_sample_rates);
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if (ret < 0) {
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pr_err("ret < 0 mtk_soc_pcm_dl1_close\n");
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mtk_soc_pcm_dl1_close(substream);
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return ret;
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}
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return 0;
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}
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static int mtk_soc_pcm_dl1_close(struct snd_pcm_substream *substream)
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{
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pr_debug("%s\n", __func__);
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if (mPrepareDone == true) {
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/* stop DAC output */
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SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false);
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if (GetI2SDacEnable() == false)
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SetI2SDacEnable(false);
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RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream);
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EnableAfe(false);
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mPrepareDone = false;
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}
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AudDrv_Clk_Off();
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return 0;
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}
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static int mtk_pcm_prepare(struct snd_pcm_substream *substream)
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{
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bool mI2SWLen;
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struct snd_pcm_runtime *runtime = substream->runtime;
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if (mPrepareDone == false) {
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pr_debug("%s format = %d\n", __func__, runtime->format);
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SetMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream);
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if (runtime->format == SNDRV_PCM_FORMAT_S32_LE ||
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runtime->format == SNDRV_PCM_FORMAT_U32_LE) {
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SetMemIfFetchFormatPerSample(
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Soc_Aud_Digital_Block_MEM_DL1,
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AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA);
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SetConnectionFormat(OUTPUT_DATA_FORMAT_24BIT,
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Soc_Aud_AFE_IO_Block_I2S1_DAC);
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SetConnectionFormat(OUTPUT_DATA_FORMAT_24BIT,
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Soc_Aud_AFE_IO_Block_I2S1_DAC_2);
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mI2SWLen = Soc_Aud_I2S_WLEN_WLEN_32BITS;
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} else {
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SetMemIfFetchFormatPerSample(
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Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_16_BIT);
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SetConnectionFormat(OUTPUT_DATA_FORMAT_16BIT,
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Soc_Aud_AFE_IO_Block_I2S1_DAC);
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SetConnectionFormat(OUTPUT_DATA_FORMAT_16BIT,
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Soc_Aud_AFE_IO_Block_I2S1_DAC_2);
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mI2SWLen = Soc_Aud_I2S_WLEN_WLEN_16BITS;
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}
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/* start I2S DAC out */
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if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC) ==
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false) {
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SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC,
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true);
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SetI2SDacOut(substream->runtime->rate, false, mI2SWLen);
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SetI2SDacEnable(true);
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} else {
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SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC,
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true);
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}
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EnableAfe(true);
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mPrepareDone = true;
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}
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return 0;
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}
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static int mtk_pcm_dl1_start(struct snd_pcm_substream *substream)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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pr_debug("%s\n", __func__);
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/* here start digital part */
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SetIntfConnection(Soc_Aud_InterCon_Connection,
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Soc_Aud_AFE_IO_Block_MEM_DL1,
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Soc_Aud_AFE_IO_Block_I2S1_DAC);
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SetIntfConnection(Soc_Aud_InterCon_Connection,
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Soc_Aud_AFE_IO_Block_MEM_DL1,
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Soc_Aud_AFE_IO_Block_I2S1_DAC_2);
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/* here to set interrupt */
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irq_add_user(substream,
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irq_request_number(Soc_Aud_Digital_Block_MEM_DL1),
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substream->runtime->rate, substream->runtime->period_size);
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SetSampleRate(Soc_Aud_Digital_Block_MEM_DL1, runtime->rate);
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SetChannels(Soc_Aud_Digital_Block_MEM_DL1, runtime->channels);
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SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, true);
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EnableAfe(true);
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return 0;
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}
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static int mtk_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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{
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#if defined(DL1_DEBUG_LOG)
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pr_debug("%s(), cmd = %d\n", __func__, cmd);
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#endif
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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return mtk_pcm_dl1_start(substream);
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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return mtk_pcm_dl1_stop(substream);
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}
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return -EINVAL;
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}
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static int mtk_pcm_copy(struct snd_pcm_substream *substream,
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int channel,
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unsigned long pos,
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void __user *buf,
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unsigned long bytes)
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{
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struct afe_block_t *Afe_Block = NULL;
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int copy_size = 0, Afe_WriteIdx_tmp;
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unsigned long flags;
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/* struct snd_pcm_runtime *runtime = substream->runtime; */
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char *data_w_ptr = (char *)buf;
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/* get total bytes to copy */
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unsigned long count = bytes;
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#ifdef DL1_DEBUG_LOG
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pr_debug("%s(), pos = %lu, count = %lu\n",
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_func__,
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pos,
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count);
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#endif
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/* check which memif nned to be write */
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Afe_Block = &pMemControl->rBlock;
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#ifdef DL1_DEBUG_LOG
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pr_debug(
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"AudDrv_write WriteIdx=0x%x, ReadIdx=0x%x, DataRemained=0x%x\n",
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Afe_Block->u4WriteIdx, Afe_Block->u4DMAReadIdx,
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Afe_Block->u4DataRemained);
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#endif
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if (Afe_Block->u4BufferSize == 0) {
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pr_err("AudDrv_write: u4BufferSize=0 Error");
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return 0;
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}
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AudDrv_checkDLISRStatus();
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spin_lock_irqsave(&auddrv_DLCtl_lock, flags);
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copy_size = Afe_Block->u4BufferSize -
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Afe_Block->u4DataRemained; /* free space of the buffer */
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spin_unlock_irqrestore(&auddrv_DLCtl_lock, flags);
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if (count <= copy_size) {
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if (copy_size < 0)
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copy_size = 0;
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else
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copy_size = count;
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}
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copy_size = word_size_align(copy_size);
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#ifdef DL1_DEBUG_LOG
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pr_debug("copy_size=0x%x, count=0x%x\n", copy_size,
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(unsigned int)count);
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#endif
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if (copy_size != 0) {
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spin_lock_irqsave(&auddrv_DLCtl_lock, flags);
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Afe_WriteIdx_tmp = Afe_Block->u4WriteIdx;
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spin_unlock_irqrestore(&auddrv_DLCtl_lock, flags);
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/* copy once */
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if (Afe_WriteIdx_tmp + copy_size < Afe_Block->u4BufferSize) {
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if (!access_ok(VERIFY_READ, data_w_ptr, copy_size)) {
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#if defined(DL1_DEBUG_LOG)
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pr_debug(
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"AudDrv_write 0ptr invalid data_w_ptr=%p, size=%d u4BufferSize=%d, u4DataRemained=%d",
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data_w_ptr, copy_size,
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Afe_Block->u4BufferSize,
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Afe_Block->u4DataRemained);
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#endif
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} else {
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#ifdef DL1_DEBUG_LOG
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pr_debug(
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"memcpy VirtBufAddr+Afe_WriteIdx= %p,data_w_ptr = %p copy_size = 0x%x\n",
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Afe_Block->pucVirtBufAddr +
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Afe_WriteIdx_tmp,
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data_w_ptr, copy_size);
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#endif
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if (copy_from_user((Afe_Block->pucVirtBufAddr +
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Afe_WriteIdx_tmp),
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data_w_ptr, copy_size)) {
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#if defined(DL1_DEBUG_LOG)
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pr_debug(
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"AudDrv_write Fail copy from user\n");
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#endif
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return -1;
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}
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}
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spin_lock_irqsave(&auddrv_DLCtl_lock, flags);
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Afe_Block->u4DataRemained += copy_size;
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Afe_Block->u4WriteIdx = Afe_WriteIdx_tmp + copy_size;
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Afe_Block->u4WriteIdx %= Afe_Block->u4BufferSize;
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spin_unlock_irqrestore(&auddrv_DLCtl_lock, flags);
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data_w_ptr += copy_size;
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count -= copy_size;
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#ifdef DL1_DEBUG_LOG
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pr_debug(
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"AudDrv_write finish1, copy:%x, WriteIdx:%x,ReadIdx=%x,Remained:%x, count=%d \r\n",
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copy_size, Afe_Block->u4WriteIdx,
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Afe_Block->u4DMAReadIdx,
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Afe_Block->u4DataRemained, (int)count);
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#endif
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} else {
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/* copy twice */
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kal_uint32 size_1 = 0, size_2 = 0;
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size_1 = word_size_align(
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(Afe_Block->u4BufferSize - Afe_WriteIdx_tmp));
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size_2 = word_size_align((copy_size - size_1));
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#ifdef DL1_DEBUG_LOG
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pr_debug("size_1=0x%x, size_2=0x%x\n", size_1,
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size_2);
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#endif
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if (!access_ok(VERIFY_READ, data_w_ptr, size_1)) {
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pr_err("AudDrv_write 1ptr invalid data_w_ptr=%p, size_1=%d u4BufferSize=%d, u4DataRemained=%d",
|
|
data_w_ptr, size_1,
|
|
Afe_Block->u4BufferSize,
|
|
Afe_Block->u4DataRemained);
|
|
} else {
|
|
#ifdef DL1_DEBUG_LOG
|
|
pr_debug(
|
|
"mcmcpy Afe_Block->pucVirtBufAddr+Afe_WriteIdx= %p data_w_ptr = %p size_1 = %x\n",
|
|
Afe_Block->pucVirtBufAddr +
|
|
Afe_WriteIdx_tmp,
|
|
data_w_ptr, size_1);
|
|
#endif
|
|
if ((copy_from_user((Afe_Block->pucVirtBufAddr +
|
|
Afe_WriteIdx_tmp),
|
|
data_w_ptr,
|
|
(unsigned int)size_1))) {
|
|
#if defined(DL1_DEBUG_LOG)
|
|
pr_debug(
|
|
"AudDrv_write Fail 1 copy from user");
|
|
#endif
|
|
return -1;
|
|
}
|
|
}
|
|
spin_lock_irqsave(&auddrv_DLCtl_lock, flags);
|
|
Afe_Block->u4DataRemained += size_1;
|
|
Afe_Block->u4WriteIdx = Afe_WriteIdx_tmp + size_1;
|
|
Afe_Block->u4WriteIdx %= Afe_Block->u4BufferSize;
|
|
Afe_WriteIdx_tmp = Afe_Block->u4WriteIdx;
|
|
spin_unlock_irqrestore(&auddrv_DLCtl_lock, flags);
|
|
|
|
if (!access_ok(VERIFY_READ, data_w_ptr + size_1,
|
|
size_2)) {
|
|
#if defined(DL1_DEBUG_LOG)
|
|
pr_debug(
|
|
"AudDrv_write 2ptr invalid data_w_ptr=%p, size_1=%d, size_2=%d u4BufferSize=%d, u4DataRemained=%d",
|
|
data_w_ptr, size_1, size_2,
|
|
Afe_Block->u4BufferSize,
|
|
Afe_Block->u4DataRemained);
|
|
#endif
|
|
} else {
|
|
#ifdef DL1_DEBUG_LOG
|
|
pr_debug(
|
|
"mcmcpy VirtBufAddr+Afe_WriteIdx= %p,data_w_ptr+size_1 = %p size_2 = %x\n",
|
|
Afe_Block->pucVirtBufAddr +
|
|
Afe_WriteIdx_tmp,
|
|
data_w_ptr + size_1,
|
|
(unsigned int)size_2);
|
|
#endif
|
|
if ((copy_from_user((Afe_Block->pucVirtBufAddr +
|
|
Afe_WriteIdx_tmp),
|
|
(data_w_ptr + size_1),
|
|
size_2))) {
|
|
#if defined(DL1_DEBUG_LOG)
|
|
pr_debug(
|
|
"AudDrv_write Fail 2 copy from user");
|
|
#endif
|
|
return -1;
|
|
}
|
|
}
|
|
spin_lock_irqsave(&auddrv_DLCtl_lock, flags);
|
|
|
|
Afe_Block->u4DataRemained += size_2;
|
|
Afe_Block->u4WriteIdx = Afe_WriteIdx_tmp + size_2;
|
|
Afe_Block->u4WriteIdx %= Afe_Block->u4BufferSize;
|
|
spin_unlock_irqrestore(&auddrv_DLCtl_lock, flags);
|
|
count -= copy_size;
|
|
data_w_ptr += copy_size;
|
|
#ifdef DL1_DEBUG_LOG
|
|
|
|
pr_debug(
|
|
"AudDrv_write finish2, copy size:%x, WriteIdx:%x,ReadIdx=%x DataRemained:%x \r\n",
|
|
copy_size, Afe_Block->u4WriteIdx,
|
|
Afe_Block->u4DMAReadIdx,
|
|
Afe_Block->u4DataRemained);
|
|
#endif
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_pcm_silence(struct snd_pcm_substream *substream,
|
|
int channel,
|
|
unsigned long pos,
|
|
unsigned long bytes)
|
|
{
|
|
#if defined(DL1_DEBUG_LOG)
|
|
pr_debug("%s\n", __func__);
|
|
#endif
|
|
return 0; /* do nothing */
|
|
}
|
|
|
|
static void *dummy_page[2];
|
|
|
|
static struct page *mtk_pcm_page(struct snd_pcm_substream *substream,
|
|
unsigned long offset)
|
|
{
|
|
#if defined(DL1_DEBUG_LOG)
|
|
pr_debug("%s\n", __func__);
|
|
#endif
|
|
return virt_to_page(dummy_page[substream->stream]); /* the same page */
|
|
}
|
|
|
|
static struct snd_pcm_ops mtk_afe_ops = {
|
|
.open = mtk_pcm_dl1_open,
|
|
.close = mtk_soc_pcm_dl1_close,
|
|
.ioctl = snd_pcm_lib_ioctl,
|
|
.hw_params = mtk_pcm_dl1_params,
|
|
.hw_free = mtk_pcm_dl1_hw_free,
|
|
.prepare = mtk_pcm_prepare,
|
|
.trigger = mtk_pcm_trigger,
|
|
.pointer = mtk_pcm_pointer,
|
|
.copy_user = mtk_pcm_copy,
|
|
.fill_silence = mtk_pcm_silence,
|
|
.page = mtk_pcm_page,
|
|
};
|
|
|
|
static const struct snd_soc_component_driver mtk_soc_component = {
|
|
.name = AFE_PCM_NAME,
|
|
.ops = &mtk_afe_ops,
|
|
.probe = mtk_asoc_dl1_component_probe,
|
|
};
|
|
|
|
static int mtk_asoc_dl1_component_probe(struct snd_soc_component *component)
|
|
{
|
|
#if defined(DL1_DEBUG_LOG)
|
|
pr_debug("mtk_asoc_dl1_probe\n");
|
|
#endif
|
|
/* allocate dram */
|
|
AudDrv_Allocate_mem_Buffer(component->dev,
|
|
Soc_Aud_Digital_Block_MEM_DL1,
|
|
Dl1_MAX_BUFFER_SIZE);
|
|
|
|
Dl1_Playback_dma_buf = Get_Mem_Buffer(Soc_Aud_Digital_Block_MEM_DL1);
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_afe_remove(struct platform_device *pdev)
|
|
{
|
|
#if defined(DL1_DEBUG_LOG)
|
|
pr_debug("%s\n", __func__);
|
|
#endif
|
|
AudDrv_Clk_Deinit(&pdev->dev);
|
|
|
|
snd_soc_unregister_component(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
/*extern void *AFE_BASE_ADDRESS;*/
|
|
u32 afe_irq_number;
|
|
|
|
static const struct of_device_id mt_soc_pcm_dl1_of_ids[] = {
|
|
{
|
|
.compatible = "mediatek,mt_soc_pcm_dl1",
|
|
},
|
|
{} };
|
|
|
|
static int auddrv_get_irqline(void *dev)
|
|
{
|
|
struct device *pdev = dev;
|
|
|
|
if (!pdev->of_node) {
|
|
pr_err("%s invalid of_node\n", __func__);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/*get afe irq num */
|
|
afe_irq_number = irq_of_parse_and_map(pdev->of_node, 0);
|
|
|
|
pr_debug("[ge_mt_soc_pcm_dl1] afe_irq_number=%d\n", afe_irq_number);
|
|
|
|
if (!afe_irq_number) {
|
|
pr_err("[ge_mt_soc_pcm_dl1] get afe_irq_number failed!!!\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif
|
|
|
|
static void DL1GlobalVarInit(void)
|
|
{
|
|
pMemControl = NULL;
|
|
|
|
mPlaybackDramState = 0;
|
|
|
|
Dl1_Playback_dma_buf = NULL;
|
|
|
|
mDev = NULL;
|
|
|
|
mPrepareDone = false;
|
|
}
|
|
|
|
static int mtk_soc_dl1_probe(struct platform_device *pdev)
|
|
{
|
|
int ret = 0;
|
|
|
|
mDev = &pdev->dev;
|
|
#if defined(DL1_DEBUG_LOG)
|
|
pr_debug("%s\n", __func__);
|
|
#endif
|
|
pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
|
|
|
|
if (!pdev->dev.dma_mask)
|
|
pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
|
|
|
|
if (pdev->dev.of_node) {
|
|
dev_set_name(&pdev->dev, "%s", MT_SOC_DL1_PCM);
|
|
pdev->name = pdev->dev.kobj.name;
|
|
} else {
|
|
pr_err("%s invalid of_node\n", __func__);
|
|
return -ENODEV;
|
|
}
|
|
|
|
pr_debug("%s: dev name %s\n", __func__, dev_name(&pdev->dev));
|
|
|
|
DL1GlobalVarInit();
|
|
|
|
#ifdef CONFIG_OF
|
|
AudDrv_Clk_probe(&pdev->dev);
|
|
|
|
#ifndef CONFIG_MTK_LEGACY
|
|
AudDrv_GPIO_probe(&pdev->dev);
|
|
#endif
|
|
#endif
|
|
|
|
ret = InitAfeControl(&pdev->dev);
|
|
|
|
if (ret != 0)
|
|
return ret;
|
|
|
|
#ifdef CONFIG_OF
|
|
auddrv_get_irqline(&pdev->dev);
|
|
ret = Register_Aud_Irq(&pdev->dev, afe_irq_number);
|
|
#else
|
|
ret = Register_Aud_Irq(&pdev->dev, MT6735_AFE_MCU_IRQ_LINE);
|
|
#endif
|
|
|
|
if (ret != 0)
|
|
return ret;
|
|
|
|
/* config smartpa gpio pins, set initial state : SMARTPA_OFF */
|
|
AudDrv_GPIO_SMARTPA_Select(0);
|
|
|
|
return snd_soc_register_component(&pdev->dev,
|
|
&mtk_soc_component,
|
|
NULL,
|
|
0);
|
|
}
|
|
|
|
static struct platform_driver mtk_afe_driver = {
|
|
.driver = {
|
|
|
|
.name = MT_SOC_DL1_PCM,
|
|
.owner = THIS_MODULE,
|
|
#ifdef CONFIG_OF
|
|
.of_match_table = mt_soc_pcm_dl1_of_ids,
|
|
#endif
|
|
},
|
|
.probe = mtk_soc_dl1_probe,
|
|
.remove = mtk_afe_remove,
|
|
};
|
|
|
|
#ifndef CONFIG_OF
|
|
static struct platform_device *soc_mtkafe_dev;
|
|
#endif
|
|
|
|
static int __init mtk_soc_platform_init(void)
|
|
{
|
|
int ret;
|
|
#if defined(DL1_DEBUG_LOG)
|
|
pr_debug("%s\n", __func__);
|
|
#endif
|
|
#ifndef CONFIG_OF
|
|
|
|
soc_mtkafe_dev = platform_device_alloc(MT_SOC_DL1_PCM, -1);
|
|
|
|
if (!soc_mtkafe_dev)
|
|
return -ENOMEM;
|
|
|
|
ret = platform_device_add(soc_mtkafe_dev);
|
|
|
|
if (ret != 0) {
|
|
platform_device_put(soc_mtkafe_dev);
|
|
return ret;
|
|
}
|
|
#endif
|
|
ret = platform_driver_register(&mtk_afe_driver);
|
|
return ret;
|
|
}
|
|
module_init(mtk_soc_platform_init);
|
|
|
|
static void __exit mtk_soc_platform_exit(void)
|
|
{
|
|
platform_driver_unregister(&mtk_afe_driver);
|
|
}
|
|
module_exit(mtk_soc_platform_exit);
|
|
|
|
MODULE_DESCRIPTION("AFE PCM module platform driver");
|
|
MODULE_LICENSE("GPL");
|