283 lines
7.7 KiB
C
Executable file
283 lines
7.7 KiB
C
Executable file
/*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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/*! \file
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* \brief Declaration of library functions
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*
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* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
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*/
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#ifndef _CONNINFRA_H_
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#define _CONNINFRA_H_
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/*******************************************************************************
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* C O M P I L E R F L A G S
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********************************************************************************
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*/
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/*******************************************************************************
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* M A C R O S
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********************************************************************************
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*/
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/*******************************************************************************
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* C O N S T A N T S
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********************************************************************************
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*/
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/*******************************************************************************
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* D A T A T Y P E S
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********************************************************************************
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*/
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enum consys_drv_type {
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CONNDRV_TYPE_BT = 0,
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CONNDRV_TYPE_FM = 1,
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CONNDRV_TYPE_GPS = 2,
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CONNDRV_TYPE_WIFI = 3,
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CONNDRV_TYPE_CONNINFRA = 4,
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CONNDRV_TYPE_MAX
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};
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enum consys_adie_ctl_type {
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CONNSYS_ADIE_CTL_HOST_BT,
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CONNSYS_ADIE_CTL_HOST_FM,
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CONNSYS_ADIE_CTL_HOST_GPS,
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CONNSYS_ADIE_CTL_HOST_WIFI,
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CONNSYS_ADIE_CTL_HOST_CONNINFRA,
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CONNSYS_ADIE_CTL_FW_BT,
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CONNSYS_ADIE_CTL_FW_WIFI,
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CONNSYS_ADIE_CTL_MAX
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};
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/* HW-specific, need sync with FW. DO NOT MODIFY */
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enum sys_spi_subsystem
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{
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SYS_SPI_WF1 = 0x00,
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SYS_SPI_WF = 0x01,
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SYS_SPI_BT = 0x02,
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SYS_SPI_FM = 0x03,
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SYS_SPI_GPS = 0x04,
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SYS_SPI_TOP = 0x05,
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SYS_SPI_WF2 = 0x06,
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SYS_SPI_WF3 = 0x07,
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SYS_SPI_MAX
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};
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enum connsys_spi_speed_type {
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CONNSYS_SPI_SPEED_26M,
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CONNSYS_SPI_SPEED_64M,
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CONNSYS_SPI_SPEED_MAX
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};
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enum connsys_clock_schematic
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{
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CONNSYS_CLOCK_SCHEMATIC_26M_COTMS = 0,
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CONNSYS_CLOCK_SCHEMATIC_52M_COTMS,
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CONNSYS_CLOCK_SCHEMATIC_26M_EXTCXO,
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CONNSYS_CLOCK_SCHEMATIC_52M_EXTCXO,
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CONNSYS_CLOCK_SCHEMATIC_MAX,
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};
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/* Conninfra driver allocate EMI for FW
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* (FW includes: BT, WIFI and their MCU)
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* +-----------+
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* | |
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* | FW |
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* | |
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* +-----------+
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*
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* MCIF region is provided by MD
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* +-----------+
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* | |
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* | |
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* | MCIF |
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* | |
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* +-----------+
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*/
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enum connsys_emi_type
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{
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CONNSYS_EMI_FW,
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CONNSYS_EMI_MCIF,
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CONNSYS_EMI_MAX,
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};
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enum connsys_ic_info_type
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{
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CONNSYS_SOC_CHIPID,
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CONNSYS_HW_VER,
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CONNSYS_ADIE_CHIPID,
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CONNSYS_IC_INFO_MAX,
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};
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#define CONNINFRA_SPI_OP_FAIL 0x1
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#define CONNINFRA_CB_RET_CAL_PASS_POWER_OFF 0x0
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#define CONNINFRA_CB_RET_CAL_PASS_POWER_ON 0x2
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#define CONNINFRA_CB_RET_CAL_FAIL_POWER_OFF 0x1
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#define CONNINFRA_CB_RET_CAL_FAIL_POWER_ON 0x3
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#define CONNINFRA_BUS_CLOCK_WPLL 0x1
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#define CONNINFRA_BUS_CLOCK_BPLL 0x2
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#define CONNINFRA_BUS_CLOCK_ALL 0x3
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/* bus hang error define */
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#define CONNINFRA_INFRA_BUS_HANG 0x1
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#define CONNINFRA_AP2CONN_RX_SLP_PROT_ERR 0x2
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#define CONNINFRA_AP2CONN_TX_SLP_PROT_ERR 0x4
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#define CONNINFRA_AP2CONN_CLK_ERR 0x8
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#define CONNINFRA_INFRA_BUS_HANG_IRQ 0x10
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#define CONNINFRA_ERR_RST_ONGOING -0x7788
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#define CONNINFRA_ERR_WAKEUP_FAIL -0x5566
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#define CONNINFRA_POWER_ON_D_DIE_FAIL -0x1111
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#define CONNINFRA_POWER_ON_A_DIE_FAIL -0x2222
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#define CONNINFRA_POWER_ON_CONFIG_FAIL -0x3333
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/*******************************************************************************
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* E X T E R N A L R E F E R E N C E S
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********************************************************************************
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*/
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/*******************************************************************************
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* P U B L I C D A T A
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********************************************************************************
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*/
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/*******************************************************************************
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* P R I V A T E D A T A
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********************************************************************************
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*/
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/*******************************************************************************
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* F U N C T I O N D E C L A R A T I O N S
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********************************************************************************
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*/
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/* Conninfra bus clock control */
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int conninfra_bus_clock_ctrl(enum consys_drv_type drv_type, unsigned int bus_clock, int status);
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/* Clock schematic query */
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int conninfra_get_clock_schematic(void);
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/* IC info query */
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unsigned int conninfra_get_ic_info(enum connsys_ic_info_type type);
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/* SPI clock switch */
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int conninfra_spi_clock_switch(enum connsys_spi_speed_type type);
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/* A-die top_ck_en control */
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int conninfra_adie_top_ck_en_on(enum consys_adie_ctl_type type);
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int conninfra_adie_top_ck_en_off(enum consys_adie_ctl_type type);
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/* RFSPI */
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int conninfra_spi_read(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data);
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int conninfra_spi_write(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data);
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int conninfra_spi_update_bits(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data, unsigned int mask);
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/* EMI */
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void conninfra_get_phy_addr(unsigned int *addr, unsigned int *size);
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void conninfra_get_emi_phy_addr(enum connsys_emi_type type, phys_addr_t* base, unsigned int *size);
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/* power on/off */
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int conninfra_pwr_on(enum consys_drv_type drv_type);
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int conninfra_pwr_off(enum consys_drv_type drv_type);
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/* To setup config relative data, ex: debug flag */
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void conninfra_config_setup(void);
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/* reg */
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/*
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* 1 : can read
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* 0 : can't read
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*/
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int conninfra_reg_readable(void);
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/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
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/* reg readable */
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/* THIS API SHOULD NOT USED IN NORMAL CASE */
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/* IF YOU NEED THIS, PLEASE DISCUSS WITH OWNER */
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/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
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int conninfra_reg_readable_no_lock(void);
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int conninfra_reg_readable_for_coredump(void);
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/*
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* 0 : NO hang
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* > 0 : HANG!!
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* CONNINFRA_ERR_RST_ONGOING: whole chip reset is ongoing
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*/
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int conninfra_is_bus_hang(void);
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/* chip reset
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* return:
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* <0: error
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* =0: triggered
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* =1: ongoing
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*/
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int conninfra_trigger_whole_chip_rst(enum consys_drv_type drv, char *reason);
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/* whole chip reset callback
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* return:
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* =0: success
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* !0: fail
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*/
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struct whole_chip_rst_cb {
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int (*pre_whole_chip_rst)(enum consys_drv_type drv, char *reason);
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int (*post_whole_chip_rst)(void);
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};
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/* driver state query */
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/* VCN control */
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/* Thermal */
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/* Config */
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/* semaphore */
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/* calibration */
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/* subsys callback register */
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struct pre_calibration_cb {
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int (*pwr_on_cb)(void);
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int (*do_cal_cb)(void);
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};
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struct sub_drv_ops_cb {
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/* chip reset */
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struct whole_chip_rst_cb rst_cb;
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/* calibration */
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struct pre_calibration_cb pre_cal_cb;
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/* thermal query */
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int (*thermal_qry)(void);
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/* UTC time change callback */
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void (*time_change_notify)(void);
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};
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int conninfra_sub_drv_ops_register(enum consys_drv_type drv_type, struct sub_drv_ops_cb *cb);
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int conninfra_sub_drv_ops_unregister(enum consys_drv_type drv_type);
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/*******************************************************************************
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* F U N C T I O N S
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********************************************************************************
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*/
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#endif /* _CONNINFRA_H_ */
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