145 lines
3.3 KiB
C
145 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __ASM_ARCH_DMA_H
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#define __ASM_ARCH_DMA_H
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#define MAX_DMA_ADDRESS (0xFFFFFFFF)
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#define MAX_DMA_CHANNELS (0)
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#endif /* !__ASM_ARCH_DMA_H */
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#ifndef __MT_DMA_H__
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#define __MT_DMA_H__
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/* define DMA channels */
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enum {
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G_DMA_1 = 0, G_DMA_2,
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P_DMA_AP_HIF, P_DMA_MD_HIF,
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P_DMA_SIM1, P_DMA_SIM2,
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P_DMA_IRDA,
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P_DMA_UART1_TX, P_DMA_UART1_RX,
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P_DMA_UART2_TX, P_DMA_UART2_RX,
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P_DMA_UART3_TX, P_DMA_UART3_RX,
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};
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/* define DMA error code */
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enum {
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DMA_ERR_CH_BUSY = 1,
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DMA_ERR_INVALID_CH = 2,
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DMA_ERR_CH_FREE = 3,
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DMA_ERR_NO_FREE_CH = 4,
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DMA_ERR_INV_CONFIG = 5,
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};
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/* define DMA ISR callback function's prototype */
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typedef void (*DMA_ISR_CALLBACK) (void *);
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/*
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* NoteXXX: Implementation below is obsolete and deprecated.
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*/
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#include <linux/types.h>
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typedef u32 INFO;
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enum {
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DMA_FALSE = 0,
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DMA_TRUE
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};
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enum {
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DMA_OK = 0,
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DMA_FAIL
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};
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enum {
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REMAINING_LENGTH = 0, /* not valid for virtual FIFO */
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VF_READPTR, /* only valid for virtual FIFO */
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VF_WRITEPTR, /* only valid for virtual FIFO */
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VF_FFCNT, /* only valid for virtual FIFO */
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VF_ALERT, /* only valid for virtual FIFO */
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VF_EMPTY, /* only valid for virtual FIFO */
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VF_FULL, /* only valid for virtual FIFO */
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VF_PORT
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};
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enum {
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GDMA_1 = 0,
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GDMA_2,
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GDMA_ANY
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};
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enum {
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ALL = 0,
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SRC,
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DST,
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SRC_AND_DST
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};
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/* define GDMA configurations */
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struct mt_gdma_conf {
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unsigned int count;
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int iten;
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unsigned int burst;
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int dfix;
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int sfix;
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unsigned int limiter;
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dma_addr_t src;
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dma_addr_t dst;
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dma_addr_t jump;
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int wpen;
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int wpsd;
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unsigned int wplen;
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unsigned int wpto;
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/* unsigned int cohen; */
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unsigned int domain;
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void (*isr_cb)(void *param);
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void *data;
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};
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/* burst */
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#define DMA_CON_BURST_SINGLE (0x00000000)
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#define DMA_CON_BURST_2BEAT (0x00010000)
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#define DMA_CON_BURST_3BEAT (0x00020000)
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#define DMA_CON_BURST_4BEAT (0x00030000)
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#define DMA_CON_BURST_5BEAT (0x00040000)
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#define DMA_CON_BURST_6BEAT (0x00050000)
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#define DMA_CON_BURST_7BEAT (0x00060000)
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#define DMA_CON_BURST_8BEAT (0x00070000)
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/* size */
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/* keep for backward compatibility only */
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#define DMA_CON_SIZE_BYTE (0x00000000)
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#define DMA_CON_SIZE_SHORT (0x00000001)
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#define DMA_CON_SIZE_LONG (0x00000002)
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extern int mt65xx_free_gdma(int channel);
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extern int mt65xx_req_gdma(DMA_ISR_CALLBACK cb, void *data);
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extern int mt65xx_start_gdma(int channel);
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extern int mt65xx_stop_gdma(int channel);
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extern void mt_reset_dma(const unsigned int iChannel);
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extern void mt65xx_dma_running_status(void);
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extern void mt_reset_gdma_conf(const unsigned int iChannel);
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extern int mt_config_gdma(int channel, struct mt_gdma_conf *config, int flag);
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extern int mt_free_gdma(int channel);
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extern int mt_req_gdma(int chan);
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extern int mt_start_gdma(int channel);
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extern int mt_polling_gdma(int channel, unsigned long timeout);
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extern int mt_stop_gdma(int channel);
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extern int mt_dump_gdma(int channel);
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extern int mt_warm_reset_gdma(int channel);
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extern int mt_hard_reset_gdma(int channel);
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extern int mt_reset_gdma(int channel);
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extern void mt_dma_running_status(void);
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/* This channel is used for APDMA Dummy READ.
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* in MT6592 this channel will be used by Frequency hopping all the time
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* .Owner: Chieh-Jay Liu
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*/
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#define DFS_APDMA_CHANNEL 0
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#endif /* !__MT_DMA_H__ */
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