764 lines
26 KiB
C
764 lines
26 KiB
C
/*
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* linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
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*
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* Header file for Host Controller registers and I/O accessors.
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*
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* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#ifndef __SDHCI_HW_H
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#define __SDHCI_HW_H
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#include <linux/scatterlist.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/leds.h>
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#include <linux/interrupt.h>
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#include <linux/mmc/host.h>
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/*
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* Controller registers
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*/
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#define SDHCI_DMA_ADDRESS 0x00
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#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
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#define SDHCI_BLOCK_SIZE 0x04
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#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
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#define SDHCI_BLOCK_COUNT 0x06
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#define SDHCI_ARGUMENT 0x08
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#define SDHCI_TRANSFER_MODE 0x0C
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#define SDHCI_TRNS_DMA 0x01
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#define SDHCI_TRNS_BLK_CNT_EN 0x02
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#define SDHCI_TRNS_AUTO_CMD12 0x04
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#define SDHCI_TRNS_AUTO_CMD23 0x08
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#define SDHCI_TRNS_READ 0x10
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#define SDHCI_TRNS_MULTI 0x20
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#define SDHCI_COMMAND 0x0E
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#define SDHCI_CMD_RESP_MASK 0x03
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#define SDHCI_CMD_CRC 0x08
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#define SDHCI_CMD_INDEX 0x10
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#define SDHCI_CMD_DATA 0x20
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#define SDHCI_CMD_ABORTCMD 0xC0
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#define SDHCI_CMD_RESP_NONE 0x00
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#define SDHCI_CMD_RESP_LONG 0x01
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#define SDHCI_CMD_RESP_SHORT 0x02
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#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
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#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
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#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
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#define SDHCI_RESPONSE 0x10
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#define SDHCI_BUFFER 0x20
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#define SDHCI_PRESENT_STATE 0x24
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#define SDHCI_CMD_INHIBIT 0x00000001
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#define SDHCI_DATA_INHIBIT 0x00000002
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#define SDHCI_DOING_WRITE 0x00000100
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#define SDHCI_DOING_READ 0x00000200
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#define SDHCI_SPACE_AVAILABLE 0x00000400
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#define SDHCI_DATA_AVAILABLE 0x00000800
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#define SDHCI_CARD_PRESENT 0x00010000
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#define SDHCI_WRITE_PROTECT 0x00080000
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#define SDHCI_DATA_LVL_MASK 0x00F00000
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#define SDHCI_DATA_LVL_SHIFT 20
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#define SDHCI_DATA_0_LVL_MASK 0x00100000
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#define SDHCI_CMD_LVL 0x01000000
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#define SDHCI_HOST_CONTROL 0x28
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#define SDHCI_CTRL_LED 0x01
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#define SDHCI_CTRL_4BITBUS 0x02
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#define SDHCI_CTRL_HISPD 0x04
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#define SDHCI_CTRL_DMA_MASK 0x18
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#define SDHCI_CTRL_SDMA 0x00
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#define SDHCI_CTRL_ADMA1 0x08
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#define SDHCI_CTRL_ADMA32 0x10
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#define SDHCI_CTRL_ADMA64 0x18
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#define SDHCI_CTRL_8BITBUS 0x20
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#define SDHCI_CTRL_CDTEST_INS 0x40
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#define SDHCI_CTRL_CDTEST_EN 0x80
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#define SDHCI_POWER_CONTROL 0x29
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#define SDHCI_POWER_ON 0x01
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#define SDHCI_POWER_180 0x0A
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#define SDHCI_POWER_300 0x0C
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#define SDHCI_POWER_330 0x0E
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#define SDHCI_BLOCK_GAP_CONTROL 0x2A
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#define SDHCI_WAKE_UP_CONTROL 0x2B
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#define SDHCI_WAKE_ON_INT 0x01
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#define SDHCI_WAKE_ON_INSERT 0x02
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#define SDHCI_WAKE_ON_REMOVE 0x04
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#define SDHCI_CLOCK_CONTROL 0x2C
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#define SDHCI_DIVIDER_SHIFT 8
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#define SDHCI_DIVIDER_HI_SHIFT 6
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#define SDHCI_DIV_MASK 0xFF
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#define SDHCI_DIV_MASK_LEN 8
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#define SDHCI_DIV_HI_MASK 0x300
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#define SDHCI_PROG_CLOCK_MODE 0x0020
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#define SDHCI_CLOCK_CARD_EN 0x0004
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#define SDHCI_CLOCK_INT_STABLE 0x0002
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#define SDHCI_CLOCK_INT_EN 0x0001
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#define SDHCI_TIMEOUT_CONTROL 0x2E
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#define SDHCI_SOFTWARE_RESET 0x2F
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#define SDHCI_RESET_ALL 0x01
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#define SDHCI_RESET_CMD 0x02
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#define SDHCI_RESET_DATA 0x04
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#define SDHCI_INT_STATUS 0x30
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#define SDHCI_INT_ENABLE 0x34
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#define SDHCI_SIGNAL_ENABLE 0x38
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#define SDHCI_INT_RESPONSE 0x00000001
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#define SDHCI_INT_DATA_END 0x00000002
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#define SDHCI_INT_BLK_GAP 0x00000004
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#define SDHCI_INT_DMA_END 0x00000008
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#define SDHCI_INT_SPACE_AVAIL 0x00000010
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#define SDHCI_INT_DATA_AVAIL 0x00000020
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#define SDHCI_INT_CARD_INSERT 0x00000040
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#define SDHCI_INT_CARD_REMOVE 0x00000080
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#define SDHCI_INT_CARD_INT 0x00000100
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#define SDHCI_INT_RETUNE 0x00001000
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#define SDHCI_INT_CQE 0x00004000
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#define SDHCI_INT_ERROR 0x00008000
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#define SDHCI_INT_TIMEOUT 0x00010000
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#define SDHCI_INT_CRC 0x00020000
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#define SDHCI_INT_END_BIT 0x00040000
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#define SDHCI_INT_INDEX 0x00080000
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#define SDHCI_INT_DATA_TIMEOUT 0x00100000
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#define SDHCI_INT_DATA_CRC 0x00200000
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#define SDHCI_INT_DATA_END_BIT 0x00400000
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#define SDHCI_INT_BUS_POWER 0x00800000
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#define SDHCI_INT_AUTO_CMD_ERR 0x01000000
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#define SDHCI_INT_ADMA_ERROR 0x02000000
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#define SDHCI_INT_NORMAL_MASK 0x00007FFF
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#define SDHCI_INT_ERROR_MASK 0xFFFF8000
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#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
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SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \
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SDHCI_INT_AUTO_CMD_ERR)
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#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
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SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
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SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
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SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
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SDHCI_INT_BLK_GAP)
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#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
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#define SDHCI_CQE_INT_ERR_MASK ( \
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SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \
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SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \
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SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
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#define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)
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#define SDHCI_AUTO_CMD_STATUS 0x3C
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#define SDHCI_AUTO_CMD_TIMEOUT 0x00000002
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#define SDHCI_AUTO_CMD_CRC 0x00000004
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#define SDHCI_AUTO_CMD_END_BIT 0x00000008
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#define SDHCI_AUTO_CMD_INDEX 0x00000010
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#define SDHCI_HOST_CONTROL2 0x3E
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#define SDHCI_CTRL_UHS_MASK 0x0007
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#define SDHCI_CTRL_UHS_SDR12 0x0000
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#define SDHCI_CTRL_UHS_SDR25 0x0001
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#define SDHCI_CTRL_UHS_SDR50 0x0002
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#define SDHCI_CTRL_UHS_SDR104 0x0003
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#define SDHCI_CTRL_UHS_DDR50 0x0004
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#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
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#define SDHCI_CTRL_VDD_180 0x0008
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#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
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#define SDHCI_CTRL_DRV_TYPE_B 0x0000
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#define SDHCI_CTRL_DRV_TYPE_A 0x0010
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#define SDHCI_CTRL_DRV_TYPE_C 0x0020
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#define SDHCI_CTRL_DRV_TYPE_D 0x0030
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#define SDHCI_CTRL_EXEC_TUNING 0x0040
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#define SDHCI_CTRL_TUNED_CLK 0x0080
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#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
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#define SDHCI_CAPABILITIES 0x40
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#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
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#define SDHCI_TIMEOUT_CLK_SHIFT 0
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#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
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#define SDHCI_CLOCK_BASE_MASK 0x00003F00
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#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
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#define SDHCI_CLOCK_BASE_SHIFT 8
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#define SDHCI_MAX_BLOCK_MASK 0x00030000
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#define SDHCI_MAX_BLOCK_SHIFT 16
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#define SDHCI_CAN_DO_8BIT 0x00040000
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#define SDHCI_CAN_DO_ADMA2 0x00080000
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#define SDHCI_CAN_DO_ADMA1 0x00100000
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#define SDHCI_CAN_DO_HISPD 0x00200000
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#define SDHCI_CAN_DO_SDMA 0x00400000
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#define SDHCI_CAN_DO_SUSPEND 0x00800000
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#define SDHCI_CAN_VDD_330 0x01000000
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#define SDHCI_CAN_VDD_300 0x02000000
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#define SDHCI_CAN_VDD_180 0x04000000
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#define SDHCI_CAN_64BIT 0x10000000
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#define SDHCI_SUPPORT_SDR50 0x00000001
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#define SDHCI_SUPPORT_SDR104 0x00000002
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#define SDHCI_SUPPORT_DDR50 0x00000004
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#define SDHCI_DRIVER_TYPE_A 0x00000010
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#define SDHCI_DRIVER_TYPE_C 0x00000020
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#define SDHCI_DRIVER_TYPE_D 0x00000040
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#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00
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#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8
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#define SDHCI_USE_SDR50_TUNING 0x00002000
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#define SDHCI_RETUNING_MODE_MASK 0x0000C000
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#define SDHCI_RETUNING_MODE_SHIFT 14
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#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
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#define SDHCI_CLOCK_MUL_SHIFT 16
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#define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
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#define SDHCI_CAPABILITIES_1 0x44
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#define SDHCI_MAX_CURRENT 0x48
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#define SDHCI_MAX_CURRENT_LIMIT 0xFF
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#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF
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#define SDHCI_MAX_CURRENT_330_SHIFT 0
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#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00
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#define SDHCI_MAX_CURRENT_300_SHIFT 8
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#define SDHCI_MAX_CURRENT_180_MASK 0xFF0000
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#define SDHCI_MAX_CURRENT_180_SHIFT 16
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#define SDHCI_MAX_CURRENT_MULTIPLIER 4
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/* 4C-4F reserved for more max current */
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#define SDHCI_SET_ACMD12_ERROR 0x50
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#define SDHCI_SET_INT_ERROR 0x52
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#define SDHCI_ADMA_ERROR 0x54
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/* 55-57 reserved */
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#define SDHCI_ADMA_ADDRESS 0x58
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#define SDHCI_ADMA_ADDRESS_HI 0x5C
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/* 60-FB reserved */
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#define SDHCI_PRESET_FOR_SDR12 0x66
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#define SDHCI_PRESET_FOR_SDR25 0x68
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#define SDHCI_PRESET_FOR_SDR50 0x6A
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#define SDHCI_PRESET_FOR_SDR104 0x6C
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#define SDHCI_PRESET_FOR_DDR50 0x6E
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#define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
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#define SDHCI_PRESET_DRV_MASK 0xC000
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#define SDHCI_PRESET_DRV_SHIFT 14
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#define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400
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#define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10
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#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF
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#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0
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#define SDHCI_SLOT_INT_STATUS 0xFC
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#define SDHCI_HOST_VERSION 0xFE
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#define SDHCI_VENDOR_VER_MASK 0xFF00
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#define SDHCI_VENDOR_VER_SHIFT 8
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#define SDHCI_SPEC_VER_MASK 0x00FF
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#define SDHCI_SPEC_VER_SHIFT 0
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#define SDHCI_SPEC_100 0
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#define SDHCI_SPEC_200 1
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#define SDHCI_SPEC_300 2
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/*
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* End of controller registers.
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*/
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#define SDHCI_MAX_DIV_SPEC_200 256
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#define SDHCI_MAX_DIV_SPEC_300 2046
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/*
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* Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
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*/
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#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
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#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
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/* ADMA2 32-bit DMA descriptor size */
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#define SDHCI_ADMA2_32_DESC_SZ 8
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/* ADMA2 32-bit descriptor */
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struct sdhci_adma2_32_desc {
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__le16 cmd;
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__le16 len;
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__le32 addr;
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} __packed __aligned(4);
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/* ADMA2 data alignment */
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#define SDHCI_ADMA2_ALIGN 4
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#define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
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/*
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* ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte
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* alignment for the descriptor table even in 32-bit DMA mode. Memory
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* allocation is at least 8 byte aligned anyway, so just stipulate 8 always.
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*/
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#define SDHCI_ADMA2_DESC_ALIGN 8
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/* ADMA2 64-bit DMA descriptor size */
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#define SDHCI_ADMA2_64_DESC_SZ 12
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/*
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* ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
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* aligned.
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*/
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struct sdhci_adma2_64_desc {
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__le16 cmd;
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__le16 len;
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__le32 addr_lo;
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__le32 addr_hi;
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} __packed __aligned(4);
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#define ADMA2_TRAN_VALID 0x21
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#define ADMA2_NOP_END_VALID 0x3
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#define ADMA2_END 0x2
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/*
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* Maximum segments assuming a 512KiB maximum requisition size and a minimum
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* 4KiB page size.
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*/
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#define SDHCI_MAX_SEGS 128
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/* Allow for a a command request and a data request at the same time */
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#define SDHCI_MAX_MRQS 2
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/*
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* 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
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* However since the start time of the command, the time between
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* command and response, and the time between response and start of data is
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* not known, set the command transfer time to 10ms.
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*/
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#define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */
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enum sdhci_cookie {
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COOKIE_UNMAPPED,
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COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */
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COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */
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};
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struct sdhci_host {
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/* Data set by hardware interface driver */
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const char *hw_name; /* Hardware bus name */
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unsigned int quirks; /* Deviations from spec. */
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/* Controller doesn't honor resets unless we touch the clock register */
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#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
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/* Controller has bad caps bits, but really supports DMA */
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#define SDHCI_QUIRK_FORCE_DMA (1<<1)
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/* Controller doesn't like to be reset when there is no card inserted. */
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#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
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/* Controller doesn't like clearing the power reg before a change */
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#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
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/* Controller has flaky internal state so reset it on each ios change */
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#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
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/* Controller has an unusable DMA engine */
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#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
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/* Controller has an unusable ADMA engine */
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#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
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/* Controller can only DMA from 32-bit aligned addresses */
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#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
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/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
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#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
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/* Controller can only ADMA chunks that are a multiple of 32 bits */
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#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
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/* Controller needs to be reset after each request to stay stable */
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#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
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/* Controller needs voltage and power writes to happen separately */
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#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
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/* Controller provides an incorrect timeout value for transfers */
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#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
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/* Controller has an issue with buffer bits for small transfers */
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#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
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/* Controller does not provide transfer-complete interrupt when not busy */
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#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
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/* Controller has unreliable card detection */
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#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
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/* Controller reports inverted write-protect state */
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#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
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/* Controller has unusable command queue engine */
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#define SDHCI_QUIRK_BROKEN_CQE (1<<17)
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/* Controller does not like fast PIO transfers */
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#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
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/* Controller has to be forced to use block size of 2048 bytes */
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#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
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/* Controller cannot do multi-block transfers */
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#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
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/* Controller can only handle 1-bit data transfers */
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#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
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/* Controller needs 10ms delay between applying power and clock */
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#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
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/* Controller uses SDCLK instead of TMCLK for data timeouts */
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#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
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/* Controller reports wrong base clock capability */
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#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
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/* Controller cannot support End Attribute in NOP ADMA descriptor */
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#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
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/* Controller is missing device caps. Use caps provided by host */
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#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
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/* Controller uses Auto CMD12 command to stop the transfer */
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#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
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/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
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#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
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/* Controller treats ADMA descriptors with length 0000h incorrectly */
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#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
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/* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
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#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
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unsigned int quirks2; /* More deviations from spec. */
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#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
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#define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)
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/* The system physically doesn't support 1.8v, even if the host does */
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#define SDHCI_QUIRK2_NO_1_8_V (1<<2)
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#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
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#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
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/* Controller has a non-standard host control register */
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#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
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/* Controller does not support HS200 */
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#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
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/* Controller does not support DDR50 */
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#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
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/* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
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#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
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/* Controller does not support 64-bit DMA */
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#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
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/* need clear transfer mode register before send cmd */
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#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
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/* Capability register bit-63 indicates HS400 support */
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#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11)
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/* forced tuned clock */
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#define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12)
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/* disable the block count for single block transactions */
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#define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13)
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/* Controller broken with using ACMD23 */
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#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
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/* Broken Clock divider zero in controller */
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#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
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/* Controller has CRC in 136 bit Command Response */
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#define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16)
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/*
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* Disable HW timeout if the requested timeout is more than the maximum
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* obtainable timeout.
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*/
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#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17)
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int irq; /* Device IRQ */
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void __iomem *ioaddr; /* Mapped address */
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char *bounce_buffer; /* For packing SDMA reads/writes */
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dma_addr_t bounce_addr;
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unsigned int bounce_buffer_size;
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const struct sdhci_ops *ops; /* Low level hw interface */
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/* Internal data */
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struct mmc_host *mmc; /* MMC structure */
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struct mmc_host_ops mmc_host_ops; /* MMC host ops */
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u64 dma_mask; /* custom DMA mask */
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#if IS_ENABLED(CONFIG_LEDS_CLASS)
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struct led_classdev led; /* LED control */
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char led_name[32];
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#endif
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spinlock_t lock; /* Mutex */
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int flags; /* Host attributes */
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#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
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#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
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#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
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#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
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#define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
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#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
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#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
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#define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */
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#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
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#define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
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#define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */
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#define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */
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#define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */
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#define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */
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unsigned int version; /* SDHCI spec. version */
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unsigned int max_clk; /* Max possible freq (MHz) */
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unsigned int timeout_clk; /* Timeout freq (KHz) */
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unsigned int clk_mul; /* Clock Muliplier value */
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unsigned int clock; /* Current clock (MHz) */
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u8 pwr; /* Current voltage */
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bool runtime_suspended; /* Host is runtime suspended */
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bool bus_on; /* Bus power prevents runtime suspend */
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bool preset_enabled; /* Preset is enabled */
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bool pending_reset; /* Cmd/data reset is pending */
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bool irq_wake_enabled; /* IRQ wakeup is enabled */
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struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */
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struct mmc_command *cmd; /* Current command */
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struct mmc_command *data_cmd; /* Current data command */
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struct mmc_data *data; /* Current data request */
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unsigned int data_early:1; /* Data finished before cmd */
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struct sg_mapping_iter sg_miter; /* SG state for PIO */
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unsigned int blocks; /* remaining PIO blocks */
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int sg_count; /* Mapped sg entries */
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void *adma_table; /* ADMA descriptor table */
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void *align_buffer; /* Bounce buffer */
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size_t adma_table_sz; /* ADMA descriptor table size */
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size_t align_buffer_sz; /* Bounce buffer size */
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dma_addr_t adma_addr; /* Mapped ADMA descr. table */
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dma_addr_t align_addr; /* Mapped bounce buffer */
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unsigned int desc_sz; /* ADMA descriptor size */
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struct tasklet_struct finish_tasklet; /* Tasklet structures */
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struct timer_list timer; /* Timer for timeouts */
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struct timer_list data_timer; /* Timer for data timeouts */
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u32 caps; /* CAPABILITY_0 */
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u32 caps1; /* CAPABILITY_1 */
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bool read_caps; /* Capability flags have been read */
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unsigned int ocr_avail_sdio; /* OCR bit masks */
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unsigned int ocr_avail_sd;
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unsigned int ocr_avail_mmc;
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u32 ocr_mask; /* available voltages */
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unsigned timing; /* Current timing */
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u32 thread_isr;
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/* cached registers */
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u32 ier;
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bool cqe_on; /* CQE is operating */
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u32 cqe_ier; /* CQE interrupt mask */
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u32 cqe_err_ier; /* CQE error interrupt mask */
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wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
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unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
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unsigned int tuning_count; /* Timer count for re-tuning */
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unsigned int tuning_mode; /* Re-tuning mode supported by host */
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#define SDHCI_TUNING_MODE_1 0
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#define SDHCI_TUNING_MODE_2 1
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#define SDHCI_TUNING_MODE_3 2
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/* Delay (ms) between tuning commands */
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int tuning_delay;
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/* Host SDMA buffer boundary. */
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u32 sdma_boundary;
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u64 data_timeout;
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unsigned long private[0] ____cacheline_aligned;
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};
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struct sdhci_ops {
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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u32 (*read_l)(struct sdhci_host *host, int reg);
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u16 (*read_w)(struct sdhci_host *host, int reg);
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u8 (*read_b)(struct sdhci_host *host, int reg);
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void (*write_l)(struct sdhci_host *host, u32 val, int reg);
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void (*write_w)(struct sdhci_host *host, u16 val, int reg);
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void (*write_b)(struct sdhci_host *host, u8 val, int reg);
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#endif
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void (*set_clock)(struct sdhci_host *host, unsigned int clock);
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void (*set_power)(struct sdhci_host *host, unsigned char mode,
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unsigned short vdd);
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u32 (*irq)(struct sdhci_host *host, u32 intmask);
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|
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int (*enable_dma)(struct sdhci_host *host);
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unsigned int (*get_max_clock)(struct sdhci_host *host);
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|
unsigned int (*get_min_clock)(struct sdhci_host *host);
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|
/* get_timeout_clock should return clk rate in unit of Hz */
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unsigned int (*get_timeout_clock)(struct sdhci_host *host);
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unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
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|
void (*set_timeout)(struct sdhci_host *host,
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|
struct mmc_command *cmd);
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|
void (*set_bus_width)(struct sdhci_host *host, int width);
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|
void (*platform_send_init_74_clocks)(struct sdhci_host *host,
|
|
u8 power_mode);
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|
unsigned int (*get_ro)(struct sdhci_host *host);
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|
void (*reset)(struct sdhci_host *host, u8 mask);
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|
int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
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|
void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
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|
void (*hw_reset)(struct sdhci_host *host);
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|
void (*adma_workaround)(struct sdhci_host *host, u32 intmask);
|
|
void (*card_event)(struct sdhci_host *host);
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|
void (*voltage_switch)(struct sdhci_host *host);
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|
};
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|
|
|
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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|
|
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static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
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|
{
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|
if (unlikely(host->ops->write_l))
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|
host->ops->write_l(host, val, reg);
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|
else
|
|
writel(val, host->ioaddr + reg);
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|
}
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|
|
|
static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
|
|
{
|
|
if (unlikely(host->ops->write_w))
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host->ops->write_w(host, val, reg);
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|
else
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|
writew(val, host->ioaddr + reg);
|
|
}
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|
|
|
static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
|
|
{
|
|
if (unlikely(host->ops->write_b))
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|
host->ops->write_b(host, val, reg);
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|
else
|
|
writeb(val, host->ioaddr + reg);
|
|
}
|
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|
|
static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
|
|
{
|
|
if (unlikely(host->ops->read_l))
|
|
return host->ops->read_l(host, reg);
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|
else
|
|
return readl(host->ioaddr + reg);
|
|
}
|
|
|
|
static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
|
|
{
|
|
if (unlikely(host->ops->read_w))
|
|
return host->ops->read_w(host, reg);
|
|
else
|
|
return readw(host->ioaddr + reg);
|
|
}
|
|
|
|
static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
|
|
{
|
|
if (unlikely(host->ops->read_b))
|
|
return host->ops->read_b(host, reg);
|
|
else
|
|
return readb(host->ioaddr + reg);
|
|
}
|
|
|
|
#else
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|
|
|
static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
|
|
{
|
|
writel(val, host->ioaddr + reg);
|
|
}
|
|
|
|
static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
|
|
{
|
|
writew(val, host->ioaddr + reg);
|
|
}
|
|
|
|
static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
|
|
{
|
|
writeb(val, host->ioaddr + reg);
|
|
}
|
|
|
|
static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
|
|
{
|
|
return readl(host->ioaddr + reg);
|
|
}
|
|
|
|
static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
|
|
{
|
|
return readw(host->ioaddr + reg);
|
|
}
|
|
|
|
static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
|
|
{
|
|
return readb(host->ioaddr + reg);
|
|
}
|
|
|
|
#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
|
|
|
|
struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size);
|
|
void sdhci_free_host(struct sdhci_host *host);
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|
|
|
static inline void *sdhci_priv(struct sdhci_host *host)
|
|
{
|
|
return host->private;
|
|
}
|
|
|
|
void sdhci_card_detect(struct sdhci_host *host);
|
|
void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps,
|
|
u32 *caps1);
|
|
int sdhci_setup_host(struct sdhci_host *host);
|
|
void sdhci_cleanup_host(struct sdhci_host *host);
|
|
int __sdhci_add_host(struct sdhci_host *host);
|
|
int sdhci_add_host(struct sdhci_host *host);
|
|
void sdhci_remove_host(struct sdhci_host *host, int dead);
|
|
void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
|
|
|
|
static inline void sdhci_read_caps(struct sdhci_host *host)
|
|
{
|
|
__sdhci_read_caps(host, NULL, NULL, NULL);
|
|
}
|
|
|
|
static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
|
|
{
|
|
return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
|
|
}
|
|
|
|
u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
|
|
unsigned int *actual_clock);
|
|
void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
|
|
void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
|
|
void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
|
|
unsigned short vdd);
|
|
void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
|
|
unsigned short vdd);
|
|
void sdhci_set_bus_width(struct sdhci_host *host, int width);
|
|
void sdhci_reset(struct sdhci_host *host, u8 mask);
|
|
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
|
|
int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
|
|
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
|
|
int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
|
|
struct mmc_ios *ios);
|
|
void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
|
|
|
|
#ifdef CONFIG_PM
|
|
int sdhci_suspend_host(struct sdhci_host *host);
|
|
int sdhci_resume_host(struct sdhci_host *host);
|
|
int sdhci_runtime_suspend_host(struct sdhci_host *host);
|
|
int sdhci_runtime_resume_host(struct sdhci_host *host);
|
|
#endif
|
|
|
|
void sdhci_cqe_enable(struct mmc_host *mmc);
|
|
void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery);
|
|
bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
|
|
int *data_error);
|
|
|
|
void sdhci_dumpregs(struct sdhci_host *host);
|
|
|
|
void sdhci_start_tuning(struct sdhci_host *host);
|
|
void sdhci_end_tuning(struct sdhci_host *host);
|
|
void sdhci_reset_tuning(struct sdhci_host *host);
|
|
void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);
|
|
|
|
#endif /* __SDHCI_HW_H */
|