181 lines
6.9 KiB
C
181 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MATROXFB_DAC1064_H__
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#define __MATROXFB_DAC1064_H__
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#include "matroxfb_base.h"
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#ifdef CONFIG_FB_MATROX_MYSTIQUE
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extern struct matrox_switch matrox_mystique;
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#endif
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#ifdef CONFIG_FB_MATROX_G
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extern struct matrox_switch matrox_G100;
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#endif
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#ifdef NEED_DAC1064
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void DAC1064_global_init(struct matrox_fb_info *minfo);
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void DAC1064_global_restore(struct matrox_fb_info *minfo);
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#endif
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#define M1064_INDEX 0x00
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#define M1064_PALWRADD 0x00
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#define M1064_PALDATA 0x01
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#define M1064_PIXRDMSK 0x02
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#define M1064_PALRDADD 0x03
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#define M1064_X_DATAREG 0x0A
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#define M1064_CURPOSXL 0x0C /* can be accessed as DWORD */
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#define M1064_CURPOSXH 0x0D
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#define M1064_CURPOSYL 0x0E
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#define M1064_CURPOSYH 0x0F
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#define M1064_XCURADDL 0x04
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#define M1064_XCURADDH 0x05
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#define M1064_XCURCTRL 0x06
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#define M1064_XCURCTRL_DIS 0x00 /* transparent, transparent, transparent, transparent */
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#define M1064_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */
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#define M1064_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */
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#define M1064_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */
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/* drive DVI by standard(0)/DVI(1) PLL */
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/* if set(1), C?DVICLKEN and C?DVICLKSEL must be set(1) */
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#define M1064_XDVICLKCTRL_DVIDATAPATHSEL 0x01
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/* drive CRTC1 by standard(0)/DVI(1) PLL */
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#define M1064_XDVICLKCTRL_C1DVICLKSEL 0x02
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/* drive CRTC2 by standard(0)/DVI(1) PLL */
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#define M1064_XDVICLKCTRL_C2DVICLKSEL 0x04
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/* pixel clock allowed to(0)/blocked from(1) driving CRTC1 */
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#define M1064_XDVICLKCTRL_C1DVICLKEN 0x08
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/* DVI PLL loop filter bandwidth selection bits */
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#define M1064_XDVICLKCTRL_DVILOOPCTL 0x30
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/* CRTC2 pixel clock allowed to(0)/blocked from(1) driving CRTC2 */
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#define M1064_XDVICLKCTRL_C2DVICLKEN 0x40
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/* P1PLL loop filter bandwidth selection */
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#define M1064_XDVICLKCTRL_P1LOOPBWDTCTL 0x80
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#define M1064_XCURCOL0RED 0x08
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#define M1064_XCURCOL0GREEN 0x09
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#define M1064_XCURCOL0BLUE 0x0A
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#define M1064_XCURCOL1RED 0x0C
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#define M1064_XCURCOL1GREEN 0x0D
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#define M1064_XCURCOL1BLUE 0x0E
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#define M1064_XDVICLKCTRL 0x0F
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#define M1064_XCURCOL2RED 0x10
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#define M1064_XCURCOL2GREEN 0x11
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#define M1064_XCURCOL2BLUE 0x12
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#define DAC1064_XVREFCTRL 0x18
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#define DAC1064_XVREFCTRL_INTERNAL 0x3F
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#define DAC1064_XVREFCTRL_EXTERNAL 0x00
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#define DAC1064_XVREFCTRL_G100_DEFAULT 0x03
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#define M1064_XMULCTRL 0x19
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#define M1064_XMULCTRL_DEPTH_8BPP 0x00 /* 8 bpp paletized */
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#define M1064_XMULCTRL_DEPTH_15BPP_1BPP 0x01 /* 15 bpp paletized + 1 bpp overlay */
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#define M1064_XMULCTRL_DEPTH_16BPP 0x02 /* 16 bpp paletized */
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#define M1064_XMULCTRL_DEPTH_24BPP 0x03 /* 24 bpp paletized */
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#define M1064_XMULCTRL_DEPTH_24BPP_8BPP 0x04 /* 24 bpp direct + 8 bpp overlay paletized */
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#define M1064_XMULCTRL_2G8V16 0x05 /* 15 bpp video direct, half xres, 8bpp paletized */
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#define M1064_XMULCTRL_G16V16 0x06 /* 15 bpp video, 15bpp graphics, one of them paletized */
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#define M1064_XMULCTRL_DEPTH_32BPP 0x07 /* 24 bpp paletized + 8 bpp unused */
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#define M1064_XMULCTRL_GRAPHICS_PALETIZED 0x00
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#define M1064_XMULCTRL_VIDEO_PALETIZED 0x08
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#define M1064_XPIXCLKCTRL 0x1A
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#define M1064_XPIXCLKCTRL_SRC_PCI 0x00
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#define M1064_XPIXCLKCTRL_SRC_PLL 0x01
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#define M1064_XPIXCLKCTRL_SRC_EXT 0x02
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#define M1064_XPIXCLKCTRL_SRC_SYS 0x03 /* G200/G400 */
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#define M1064_XPIXCLKCTRL_SRC_PLL2 0x03 /* G450 */
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#define M1064_XPIXCLKCTRL_SRC_MASK 0x03
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#define M1064_XPIXCLKCTRL_EN 0x00
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#define M1064_XPIXCLKCTRL_DIS 0x04
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#define M1064_XPIXCLKCTRL_PLL_DOWN 0x00
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#define M1064_XPIXCLKCTRL_PLL_UP 0x08
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#define M1064_XGENCTRL 0x1D
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#define M1064_XGENCTRL_VS_0 0x00
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#define M1064_XGENCTRL_VS_1 0x01
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#define M1064_XGENCTRL_ALPHA_DIS 0x00
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#define M1064_XGENCTRL_ALPHA_EN 0x02
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#define M1064_XGENCTRL_BLACK_0IRE 0x00
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#define M1064_XGENCTRL_BLACK_75IRE 0x10
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#define M1064_XGENCTRL_SYNC_ON_GREEN 0x00
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#define M1064_XGENCTRL_NO_SYNC_ON_GREEN 0x20
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#define M1064_XGENCTRL_SYNC_ON_GREEN_MASK 0x20
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#define M1064_XMISCCTRL 0x1E
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#define M1064_XMISCCTRL_DAC_DIS 0x00
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#define M1064_XMISCCTRL_DAC_EN 0x01
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#define M1064_XMISCCTRL_MFC_VGA 0x00
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#define M1064_XMISCCTRL_MFC_MAFC 0x02
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#define M1064_XMISCCTRL_MFC_DIS 0x06
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#define GX00_XMISCCTRL_MFC_MAFC 0x02
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#define GX00_XMISCCTRL_MFC_PANELLINK 0x04
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#define GX00_XMISCCTRL_MFC_DIS 0x06
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#define GX00_XMISCCTRL_MFC_MASK 0x06
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#define M1064_XMISCCTRL_DAC_6BIT 0x00
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#define M1064_XMISCCTRL_DAC_8BIT 0x08
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#define M1064_XMISCCTRL_DAC_WIDTHMASK 0x08
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#define M1064_XMISCCTRL_LUT_DIS 0x00
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#define M1064_XMISCCTRL_LUT_EN 0x10
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#define G400_XMISCCTRL_VDO_MAFC12 0x00
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#define G400_XMISCCTRL_VDO_BYPASS656 0x40
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#define G400_XMISCCTRL_VDO_C2_MAFC12 0x80
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#define G400_XMISCCTRL_VDO_C2_BYPASS656 0xC0
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#define G400_XMISCCTRL_VDO_MASK 0xE0
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#define M1064_XGENIOCTRL 0x2A
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#define M1064_XGENIODATA 0x2B
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#define DAC1064_XSYSPLLM 0x2C
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#define DAC1064_XSYSPLLN 0x2D
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#define DAC1064_XSYSPLLP 0x2E
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#define DAC1064_XSYSPLLSTAT 0x2F
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#define M1064_XZOOMCTRL 0x38
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#define M1064_XZOOMCTRL_1 0x00
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#define M1064_XZOOMCTRL_2 0x01
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#define M1064_XZOOMCTRL_4 0x03
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#define M1064_XSENSETEST 0x3A
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#define M1064_XSENSETEST_BCOMP 0x01
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#define M1064_XSENSETEST_GCOMP 0x02
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#define M1064_XSENSETEST_RCOMP 0x04
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#define M1064_XSENSETEST_PDOWN 0x00
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#define M1064_XSENSETEST_PUP 0x80
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#define M1064_XCRCREML 0x3C
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#define M1064_XCRCREMH 0x3D
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#define M1064_XCRCBITSEL 0x3E
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#define M1064_XCOLKEYMASKL 0x40
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#define M1064_XCOLKEYMASKH 0x41
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#define M1064_XCOLKEYL 0x42
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#define M1064_XCOLKEYH 0x43
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#define M1064_XPIXPLLAM 0x44
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#define M1064_XPIXPLLAN 0x45
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#define M1064_XPIXPLLAP 0x46
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#define M1064_XPIXPLLBM 0x48
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#define M1064_XPIXPLLBN 0x49
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#define M1064_XPIXPLLBP 0x4A
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#define M1064_XPIXPLLCM 0x4C
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#define M1064_XPIXPLLCN 0x4D
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#define M1064_XPIXPLLCP 0x4E
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#define M1064_XPIXPLLSTAT 0x4F
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#define M1064_XTVO_IDX 0x87
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#define M1064_XTVO_DATA 0x88
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#define M1064_XOUTPUTCONN 0x8A
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#define M1064_XSYNCCTRL 0x8B
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#define M1064_XVIDPLLSTAT 0x8C
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#define M1064_XVIDPLLP 0x8D
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#define M1064_XVIDPLLM 0x8E
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#define M1064_XVIDPLLN 0x8F
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#define M1064_XPWRCTRL 0xA0
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#define M1064_XPWRCTRL_PANELPDN 0x04
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#define M1064_XPANMODE 0xA2
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enum POS1064 {
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POS1064_XCURADDL=0, POS1064_XCURADDH, POS1064_XCURCTRL,
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POS1064_XCURCOL0RED, POS1064_XCURCOL0GREEN, POS1064_XCURCOL0BLUE,
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POS1064_XCURCOL1RED, POS1064_XCURCOL1GREEN, POS1064_XCURCOL1BLUE,
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POS1064_XCURCOL2RED, POS1064_XCURCOL2GREEN, POS1064_XCURCOL2BLUE,
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POS1064_XVREFCTRL, POS1064_XMULCTRL, POS1064_XPIXCLKCTRL, POS1064_XGENCTRL,
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POS1064_XMISCCTRL,
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POS1064_XGENIOCTRL, POS1064_XGENIODATA, POS1064_XZOOMCTRL, POS1064_XSENSETEST,
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POS1064_XCRCBITSEL,
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POS1064_XCOLKEYMASKL, POS1064_XCOLKEYMASKH, POS1064_XCOLKEYL, POS1064_XCOLKEYH,
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POS1064_XOUTPUTCONN, POS1064_XPANMODE, POS1064_XPWRCTRL };
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#endif /* __MATROXFB_DAC1064_H__ */
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