58 lines
2 KiB
Plaintext
58 lines
2 KiB
Plaintext
* IMG Multi-threaded DMA Controller (MDC)
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Required properties:
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- compatible: Must be "img,pistachio-mdc-dma".
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- reg: Must contain the base address and length of the MDC registers.
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- interrupts: Must contain all the per-channel DMA interrupts.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clock/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- sys: MDC system interface clock.
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- img,cr-periph: Must contain a phandle to the peripheral control syscon
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node which contains the DMA request to channel mapping registers.
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- img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
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The maximum burst size is this value multiplied by the hardware-reported bus
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width.
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- #dma-cells: Must be 3:
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- The first cell is the peripheral's DMA request line.
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- The second cell is a bitmap specifying to which channels the DMA request
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line may be mapped (i.e. bit N set indicates channel N is usable).
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- The third cell is the thread ID to be used by the channel.
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Optional properties:
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- dma-channels: Number of supported DMA channels, up to 32. If not specified
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the number reported by the hardware is used.
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Example:
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mdc: dma-controller@18143000 {
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compatible = "img,pistachio-mdc-dma";
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reg = <0x18143000 0x1000>;
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interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&system_clk>;
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clock-names = "sys";
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img,max-burst-multiplier = <16>;
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img,cr-periph = <&cr_periph>;
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#dma-cells = <3>;
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};
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spi@18100f00 {
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...
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dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
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dma-names = "tx", "rx";
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...
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};
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