95 lines
3.2 KiB
Plaintext
95 lines
3.2 KiB
Plaintext
* STMicroelectronics STM32 MDMA controller
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The STM32 MDMA is a general-purpose direct memory access controller capable of
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supporting 64 independent DMA channels with 256 HW requests.
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Required properties:
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- compatible: Should be "st,stm32h7-mdma"
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- reg: Should contain MDMA registers location and length. This should include
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all of the per-channel registers.
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- interrupts: Should contain the MDMA interrupt.
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- clocks: Should contain the input clock of the DMA instance.
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- resets: Reference to a reset controller asserting the DMA controller.
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- #dma-cells : Must be <5>. See DMA client paragraph for more details.
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Optional properties:
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- dma-channels: Number of DMA channels supported by the controller.
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- dma-requests: Number of DMA request signals supported by the controller.
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- st,ahb-addr-masks: Array of u32 mask to list memory devices addressed via
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AHB bus.
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Example:
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mdma1: dma@52000000 {
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compatible = "st,stm32h7-mdma";
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reg = <0x52000000 0x1000>;
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interrupts = <122>;
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clocks = <&timer_clk>;
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resets = <&rcc 992>;
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#dma-cells = <5>;
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dma-channels = <16>;
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dma-requests = <32>;
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st,ahb-addr-masks = <0x20000000>, <0x00000000>;
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};
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* DMA client
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DMA clients connected to the STM32 MDMA controller must use the format
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described in the dma.txt file, using a five-cell specifier for each channel:
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a phandle to the MDMA controller plus the following five integer cells:
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1. The request line number
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2. The priority level
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0x00: Low
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0x01: Medium
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0x10: High
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0x11: Very high
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3. A 32bit mask specifying the DMA channel configuration
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-bit 0-1: Source increment mode
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0x00: Source address pointer is fixed
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0x10: Source address pointer is incremented after each data transfer
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0x11: Source address pointer is decremented after each data transfer
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-bit 2-3: Destination increment mode
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0x00: Destination address pointer is fixed
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0x10: Destination address pointer is incremented after each data
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transfer
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0x11: Destination address pointer is decremented after each data
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transfer
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-bit 8-9: Source increment offset size
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0x00: byte (8bit)
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0x01: half-word (16bit)
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0x10: word (32bit)
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0x11: double-word (64bit)
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-bit 10-11: Destination increment offset size
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0x00: byte (8bit)
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0x01: half-word (16bit)
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0x10: word (32bit)
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0x11: double-word (64bit)
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-bit 25-18: The number of bytes to be transferred in a single transfer
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(min = 1 byte, max = 128 bytes)
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-bit 29:28: Trigger Mode
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0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
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0x01: Each MDMA request triggers a block transfer (max 64K bytes)
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0x10: Each MDMA request triggers a repeated block transfer
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0x11: Each MDMA request triggers a linked list transfer
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4. A 32bit value specifying the register to be used to acknowledge the request
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if no HW ack signal is used by the MDMA client
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5. A 32bit mask specifying the value to be written to acknowledge the request
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if no HW ack signal is used by the MDMA client
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Example:
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i2c4: i2c@5c002000 {
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compatible = "st,stm32f7-i2c";
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reg = <0x5c002000 0x400>;
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interrupts = <95>,
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<96>;
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clocks = <&timer_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>,
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<&mdma1 37 0x0 0x40002 0x0 0x0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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