104 lines
3.5 KiB
Plaintext
104 lines
3.5 KiB
Plaintext
Qualcomm SuperSpeed DWC3 USB SoC controller
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Required properties:
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- compatible: Compatible list, contains
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"qcom,dwc3"
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"qcom,msm8996-dwc3" for msm8996 SOC.
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"qcom,sdm845-dwc3" for sdm845 SOC.
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- reg: Offset and length of register set for QSCRATCH wrapper
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- power-domains: specifies a phandle to PM domain provider node
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- clocks: A list of phandle + clock-specifier pairs for the
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clocks listed in clock-names
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- clock-names: Should contain the following:
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"core" Master/Core clock, have to be >= 125 MHz for SS
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operation and >= 60MHz for HS operation
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"mock_utmi" Mock utmi clock needed for ITP/SOF generation in
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host mode. Its frequency should be 19.2MHz.
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"sleep" Sleep clock, used for wakeup when USB3 core goes
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into low power mode (U3).
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Optional clocks:
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"iface" System bus AXI clock.
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Not present on "qcom,msm8996-dwc3" compatible.
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"cfg_noc" System Config NOC clock.
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Not present on "qcom,msm8996-dwc3" compatible.
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- assigned-clocks: Should be:
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MOCK_UTMI_CLK
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MASTER_CLK
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- assigned-clock-rates: Should be:
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19.2Mhz (192000000) for MOCK_UTMI_CLK
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>=125Mhz (125000000) for MASTER_CLK in SS mode
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>=60Mhz (60000000) for MASTER_CLK in HS mode
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Optional properties:
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- resets: Phandle to reset control that resets core and wrapper.
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- interrupts: specifies interrupts from controller wrapper used
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to wakeup from low power/susepnd state. Must contain
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one or more entry for interrupt-names property
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- interrupt-names: Must include the following entries:
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- "hs_phy_irq": The interrupt that is asserted when a
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wakeup event is received on USB2 bus
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- "ss_phy_irq": The interrupt that is asserted when a
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wakeup event is received on USB3 bus
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- "dm_hs_phy_irq" and "dp_hs_phy_irq": Separate
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interrupts for any wakeup event on DM and DP lines
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- qcom,select-utmi-as-pipe-clk: if present, disable USB3 pipe_clk requirement.
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Used when dwc3 operates without SSPHY and only
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HS/FS/LS modes are supported.
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Required child node:
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A child node must exist to represent the core DWC3 IP block. The name of
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the node is not important. The content of the node is defined in dwc3.txt.
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Phy documentation is provided in the following places:
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Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY
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Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt - USB2 QUSB2 PHY
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Example device nodes:
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hs_phy: phy@100f8800 {
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compatible = "qcom,qusb2-v2-phy";
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...
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};
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ss_phy: phy@100f8830 {
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compatible = "qcom,qmp-v3-usb3-phy";
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...
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};
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usb3_0: usb30@a6f8800 {
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compatible = "qcom,dwc3";
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reg = <0xa6f8800 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>;
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interrupt-names = "hs_phy_irq", "ss_phy_irq",
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"dm_hs_phy_irq", "dp_hs_phy_irq";
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
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clock-names = "core", "mock_utmi", "sleep";
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assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <133000000>;
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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power-domains = <&gcc USB30_PRIM_GDSC>;
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qcom,select-utmi-as-pipe-clk;
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dwc3@10000000 {
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compatible = "snps,dwc3";
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reg = <0x10000000 0xcd00>;
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interrupts = <0 205 0x4>;
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phys = <&hs_phy>, <&ss_phy>;
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phy-names = "usb2-phy", "usb3-phy";
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dr_mode = "host";
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};
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};
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