173 lines
4.8 KiB
C
173 lines
4.8 KiB
C
/*
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* gpio.h: GPIO Support for PNX833X.
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*
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* Copyright 2008 NXP Semiconductors
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* Chris Steel <chris.steel@nxp.com>
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* Daniel Laird <daniel.j.laird@nxp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H
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#define __ASM_MIPS_MACH_PNX833X_GPIO_H
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/* BIG FAT WARNING: races danger!
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No protections exist here. Current users are only early init code,
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when locking is not needed because no concurrency yet exists there,
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and GPIO IRQ dispatcher, which does locking.
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However, if many uses will ever happen, proper locking will be needed
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- including locking between different uses
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*/
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#include <asm/mach-pnx833x/pnx833x.h>
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#define SET_REG_BIT(reg, bit) do { (reg |= (1 << (bit))); } while (0)
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#define CLEAR_REG_BIT(reg, bit) do { (reg &= ~(1 << (bit))); } while (0)
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/* Initialize GPIO to a known state */
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static inline void pnx833x_gpio_init(void)
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{
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PNX833X_PIO_DIR = 0;
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PNX833X_PIO_DIR2 = 0;
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PNX833X_PIO_SEL = 0;
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PNX833X_PIO_SEL2 = 0;
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PNX833X_PIO_INT_EDGE = 0;
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PNX833X_PIO_INT_HI = 0;
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PNX833X_PIO_INT_LO = 0;
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/* clear any GPIO interrupt requests */
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PNX833X_PIO_INT_CLEAR = 0xffff;
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PNX833X_PIO_INT_CLEAR = 0;
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PNX833X_PIO_INT_ENABLE = 0;
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}
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/* Select GPIO direction for a pin */
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static inline void pnx833x_gpio_select_input(unsigned int pin)
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{
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if (pin < 32)
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CLEAR_REG_BIT(PNX833X_PIO_DIR, pin);
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else
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CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
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}
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static inline void pnx833x_gpio_select_output(unsigned int pin)
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{
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if (pin < 32)
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SET_REG_BIT(PNX833X_PIO_DIR, pin);
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else
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SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
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}
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/* Select GPIO or alternate function for a pin */
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static inline void pnx833x_gpio_select_function_io(unsigned int pin)
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{
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if (pin < 32)
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CLEAR_REG_BIT(PNX833X_PIO_SEL, pin);
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else
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CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
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}
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static inline void pnx833x_gpio_select_function_alt(unsigned int pin)
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{
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if (pin < 32)
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SET_REG_BIT(PNX833X_PIO_SEL, pin);
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else
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SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
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}
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/* Read GPIO pin */
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static inline int pnx833x_gpio_read(unsigned int pin)
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{
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if (pin < 32)
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return (PNX833X_PIO_IN >> pin) & 1;
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else
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return (PNX833X_PIO_IN2 >> (pin & 31)) & 1;
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}
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/* Write GPIO pin */
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static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin)
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{
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if (pin < 32) {
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if (val)
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SET_REG_BIT(PNX833X_PIO_OUT, pin);
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else
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CLEAR_REG_BIT(PNX833X_PIO_OUT, pin);
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} else {
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if (val)
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SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
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else
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CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
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}
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}
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/* Configure GPIO interrupt */
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#define GPIO_INT_NONE 0
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#define GPIO_INT_LEVEL_LOW 1
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#define GPIO_INT_LEVEL_HIGH 2
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#define GPIO_INT_EDGE_RISING 3
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#define GPIO_INT_EDGE_FALLING 4
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#define GPIO_INT_EDGE_BOTH 5
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static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin)
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{
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switch (when) {
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case GPIO_INT_LEVEL_LOW:
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CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
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SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
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break;
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case GPIO_INT_LEVEL_HIGH:
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CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
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SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
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break;
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case GPIO_INT_EDGE_RISING:
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SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
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SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
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break;
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case GPIO_INT_EDGE_FALLING:
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SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
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SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
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break;
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case GPIO_INT_EDGE_BOTH:
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SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
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SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
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SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
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break;
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default:
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CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
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break;
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}
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}
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/* Enable/disable GPIO interrupt */
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static inline void pnx833x_gpio_enable_irq(unsigned int pin)
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{
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SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
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}
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static inline void pnx833x_gpio_disable_irq(unsigned int pin)
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{
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CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
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}
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/* Clear GPIO interrupt request */
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static inline void pnx833x_gpio_clear_irq(unsigned int pin)
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{
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SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
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CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
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}
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#endif
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