807 lines
19 KiB
C
807 lines
19 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/fb.h>
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#include <linux/platform_device.h>
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#ifdef CONFIG_MEDIATEK_DRAMC
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#include <dramc.h>
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#endif
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#ifdef CONFIG_MTK_EMI
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#include <mt_emi_api.h>
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#endif
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#include <mt-plat/upmu_common.h>
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#include "helio-dvfsrc-ip-v2.h"
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#include <helio-dvfsrc-opp.h>
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#include <helio-dvfsrc-mt6853.h>
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#include <mt-plat/mtk_devinfo.h>
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#include <linux/regulator/consumer.h>
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#include "mmdvfs_pmqos.h"
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#include <linux/sysfs.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/sched/clock.h>
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#include <dbgtop.h>
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#define DVFSRC_FB_MD_TABLE_SWITCH
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/* #define AUTOK_ENABLE */
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#define dvfsrc_rmw(offset, val, mask, shift) \
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dvfsrc_write(offset, (dvfsrc_read(offset) & ~(mask << shift)) \
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| (val << shift))
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static struct reg_config dvfsrc_init_configs[][128] = {
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{
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{ DVFSRC_HRT_REQ_UNIT, 0x0000001E },
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{ DVFSRC_DEBOUNCE_TIME, 0x00001965 },
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{ DVFSRC_TIMEOUT_NEXTREQ, 0x00000015 },
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{ DVFSRC_LEVEL_MASK, 0x000EE000 },
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{ DVFSRC_DDR_QOS0, 0x00000019 },
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{ DVFSRC_DDR_QOS1, 0x00000026 },
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{ DVFSRC_DDR_QOS2, 0x00000033 },
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{ DVFSRC_DDR_QOS3, 0x0000003B },
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{ DVFSRC_DDR_QOS4, 0x0000004C },
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{ DVFSRC_DDR_QOS5, 0x00000066 },
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{ DVFSRC_DDR_QOS6, 0x00000066 },
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{ DVFSRC_LEVEL_LABEL_0_1, 0x50436053 },
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{ DVFSRC_LEVEL_LABEL_2_3, 0x40335042 },
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{ DVFSRC_LEVEL_LABEL_4_5, 0x40314032 },
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{ DVFSRC_LEVEL_LABEL_6_7, 0x30223023 },
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{ DVFSRC_LEVEL_LABEL_8_9, 0x20133021 },
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{ DVFSRC_LEVEL_LABEL_10_11, 0x20112012 },
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{ DVFSRC_LEVEL_LABEL_12_13, 0x10032010 },
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{ DVFSRC_LEVEL_LABEL_14_15, 0x10011002 },
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{ DVFSRC_LEVEL_LABEL_16_17, 0x00131000 },
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{ DVFSRC_LEVEL_LABEL_18_19, 0x00110012},
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{ DVFSRC_LEVEL_LABEL_20_21, 0x00000010 },
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{ DVFSRC_MD_LATENCY_IMPROVE, 0x00000040 },
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{ DVFSRC_HRT_BW_BASE, 0x00000004 },
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{ DVSFRC_HRT_REQ_MD_URG, 0x000D20D2 },
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{ DVFSRC_HRT_REQ_MD_BW_0, 0x00200802 },
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{ DVFSRC_HRT_REQ_MD_BW_1, 0x00200802 },
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{ DVFSRC_HRT_REQ_MD_BW_2, 0x00200800 },
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{ DVFSRC_HRT_REQ_MD_BW_3, 0x00400802 },
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{ DVFSRC_HRT_REQ_MD_BW_4, 0x00601404 },
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{ DVFSRC_HRT_REQ_MD_BW_5, 0x00D02C09 },
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{ DVFSRC_HRT_REQ_MD_BW_6, 0x00000012 },
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{ DVFSRC_HRT_REQ_MD_BW_7, 0x00000024 },
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{ DVFSRC_HRT_REQ_MD_BW_8, 0x00000000 },
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{ DVFSRC_HRT_REQ_MD_BW_9, 0x00000000 },
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{ DVFSRC_HRT_REQ_MD_BW_10, 0x00034800 },
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{ DVFSRC_HRT1_REQ_MD_BW_0, 0x04B12C4B },
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{ DVFSRC_HRT1_REQ_MD_BW_1, 0x04B12C4B },
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{ DVFSRC_HRT1_REQ_MD_BW_2, 0x04B12C00 },
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{ DVFSRC_HRT1_REQ_MD_BW_3, 0x04B12C4B },
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{ DVFSRC_HRT1_REQ_MD_BW_4, 0x04B12C4B },
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{ DVFSRC_HRT1_REQ_MD_BW_5, 0x04B12C4B },
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{ DVFSRC_HRT1_REQ_MD_BW_6, 0x0000004B },
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{ DVFSRC_HRT1_REQ_MD_BW_7, 0x0000005C },
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{ DVFSRC_HRT1_REQ_MD_BW_8, 0x00000000 },
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{ DVFSRC_HRT1_REQ_MD_BW_9, 0x00000000 },
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{ DVFSRC_HRT1_REQ_MD_BW_10, 0x00034800 },
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#ifdef DVFSRC_FB_MD_TABLE_SWITCH
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{ DVFSRC_95MD_SCEN_BW0_T, 0x40444440 },
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{ DVFSRC_95MD_SCEN_BW1_T, 0x22244444 },
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{ DVFSRC_95MD_SCEN_BW2_T, 0x00400444 },
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{ DVFSRC_95MD_SCEN_BW3_T, 0x60000000 },
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{ DVFSRC_95MD_SCEN_BW0, 0x20222220 },
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{ DVFSRC_95MD_SCEN_BW1, 0x00022222},
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{ DVFSRC_95MD_SCEN_BW2, 0x00200222 },
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{ DVFSRC_95MD_SCEN_BW3, 0x60000000 },
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{ DVFSRC_95MD_SCEN_BW4, 0x00000006 },
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{ DVFSRC_RSRV_5, 0x00000001 },
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#else
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{ DVFSRC_95MD_SCEN_BW0_T, 0x40444440 },
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{ DVFSRC_95MD_SCEN_BW1_T, 0x22244444},
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{ DVFSRC_95MD_SCEN_BW2_T, 0x00400444 },
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{ DVFSRC_95MD_SCEN_BW3_T, 0x60000000 },
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{ DVFSRC_95MD_SCEN_BW0, 0x20222220 },
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{ DVFSRC_95MD_SCEN_BW1, 0x00022222 },
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{ DVFSRC_95MD_SCEN_BW2, 0x00200222 },
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{ DVFSRC_95MD_SCEN_BW3, 0x60000000 },
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{ DVFSRC_95MD_SCEN_BW4, 0x00000006 },
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{ DVFSRC_RSRV_5, 0x00000001 },
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#endif
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{ DVFSRC_DDR_REQUEST, 0x00004321 },
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{ DVFSRC_DDR_REQUEST3, 0x00000065 },
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{ DVFSRC_DDR_ADD_REQUEST, 0x66543210 },
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{ DVFSRC_HRT_REQUEST, 0x66654321 },
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{ DVFSRC_DDR_REQUEST5, 0x54321000 },
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{ DVFSRC_DDR_REQUEST7, 0x66000000 },
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{ DVFSRC_EMI_MON_DEBOUNCE_TIME, 0x4C2D0000 },
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{ DVFSRC_DDR_REQUEST6, 0x66543210 },
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{ DVFSRC_VCORE_USER_REQ, 0x00010A29 },
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{ DVFSRC_HRT_HIGH_3, 0x18A618A6 },
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{ DVFSRC_HRT_HIGH_2, 0x18A61183 },
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{ DVFSRC_HRT_HIGH_1, 0x0D690B80 },
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{ DVFSRC_HRT_HIGH, 0x070804B0 },
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{ DVFSRC_HRT_LOW_3, 0x18A518A5 },
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{ DVFSRC_HRT_LOW_2, 0x18A51182 },
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{ DVFSRC_HRT_LOW_1, 0x0D680B7F},
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{ DVFSRC_HRT_LOW, 0x070704AF },
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{ DVFSRC_BASIC_CONTROL_3, 0x00000006 },
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{ DVFSRC_INT_EN, 0x00000002 },
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{ DVFSRC_QOS_EN, 0x0000407C },
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{ DVFSRC_CURRENT_FORCE, 0x00000001 },
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{ DVFSRC_BASIC_CONTROL, 0x6698444B },
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{ DVFSRC_BASIC_CONTROL, 0x6698054B },
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{ DVFSRC_CURRENT_FORCE, 0x00000000 },
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{ -1, 0 },
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},
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/* NULL */
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{
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{ -1, 0 },
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},
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};
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static ssize_t dvfsrc_level_mask_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sprintf(buf, "%x\n", helio_dvfsrc_level_mask_get());
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}
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static ssize_t dvfsrc_level_mask_store(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t count)
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{
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int level = 0, en = 0;
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if (sscanf(buf, "%d %d", &level, &en) != 2)
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return -EINVAL;
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helio_dvfsrc_level_mask_set(en, level);
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return count;
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}
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static DEVICE_ATTR(dvfsrc_level_mask, 0644,
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dvfsrc_level_mask_show, dvfsrc_level_mask_store);
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static ssize_t dvfsrc_vcore_settle_time_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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/* DE's comment: settle time was hard code in fw (15,30) */
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return sprintf(buf, "rising 15 uS, falling 30 uS for mt6853\n");
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}
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static DEVICE_ATTR(dvfsrc_vcore_settle_time, 0444,
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dvfsrc_vcore_settle_time_show, NULL);
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static ssize_t dvfsrc_md_imp_gear_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sprintf(buf, "%x\n", dvfsrc_read(DVFSRC_MD_LATENCY_IMPROVE));
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}
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static ssize_t dvfsrc_md_imp_gear_store(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t count)
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{
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int gear = 0;
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if (kstrtoint(buf, 10, &gear))
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return -EINVAL;
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if (gear >= DDR_OPP_NUM || gear < 0)
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return -EINVAL;
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dvfsrc_rmw(DVFSRC_MD_LATENCY_IMPROVE, gear, 0x7, 4);
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return count;
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}
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static DEVICE_ATTR(dvfsrc_md_imp_gear, 0644,
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dvfsrc_md_imp_gear_show, dvfsrc_md_imp_gear_store);
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static ssize_t dvfsrc_md_qos_performance_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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int len = 0;
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len += snprintf(buf + len, PAGE_SIZE - 1 - len,
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"%-12s: 0x%08x\n",
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"RSRV_5",
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dvfsrc_read(DVFSRC_RSRV_5));
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len += snprintf(buf + len, PAGE_SIZE - 1 - len,
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"%-12s: 0x%08x\n",
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"DVFSRC_MD_TURBO",
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dvfsrc_read(DVFSRC_MD_TURBO));
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len += snprintf(buf + len, PAGE_SIZE - 1 - len,
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"%-12s: 0x%08x\n",
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"SCEN_URGENT",
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dvfsrc_read(DVFSRC_95MD_SCEN_BW4));
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len += snprintf(buf + len, PAGE_SIZE - 1 - len,
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"%-12s: 0x%08x, %08x, %08x, %08x\n",
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"SCEN_BW_T",
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dvfsrc_read(DVFSRC_95MD_SCEN_BW0_T),
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dvfsrc_read(DVFSRC_95MD_SCEN_BW1_T),
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dvfsrc_read(DVFSRC_95MD_SCEN_BW2_T),
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dvfsrc_read(DVFSRC_95MD_SCEN_BW3_T));
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len += snprintf(buf + len, PAGE_SIZE - 1 - len,
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"%-12s: 0x%08x, %08x, %08x, %08x\n",
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"SCEN_BW",
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dvfsrc_read(DVFSRC_95MD_SCEN_BW0),
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dvfsrc_read(DVFSRC_95MD_SCEN_BW1),
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dvfsrc_read(DVFSRC_95MD_SCEN_BW2),
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dvfsrc_read(DVFSRC_95MD_SCEN_BW3));
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return len;
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}
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static DEVICE_ATTR(dvfsrc_md_qos_performance, 0444,
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dvfsrc_md_qos_performance_show, NULL);
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static struct attribute *mt6853_helio_dvfsrc_attrs[] = {
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&dev_attr_dvfsrc_level_mask.attr,
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&dev_attr_dvfsrc_vcore_settle_time.attr,
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&dev_attr_dvfsrc_md_imp_gear.attr,
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&dev_attr_dvfsrc_md_qos_performance.attr,
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NULL,
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};
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static struct attribute_group mt6853_helio_dvfsrc_attr_group = {
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.name = "helio-dvfsrc",
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.attrs = mt6853_helio_dvfsrc_attrs,
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};
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#define dvfsrc_rmw(offset, val, mask, shift) \
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dvfsrc_write(offset, (dvfsrc_read(offset) & ~(mask << shift)) \
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| (val << shift))
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u32 dvfsrc_get_ddr_qos(void)
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{
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unsigned int qos_total_bw = dvfsrc_read(DVFSRC_SW_BW_0) +
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dvfsrc_read(DVFSRC_SW_BW_1) +
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dvfsrc_read(DVFSRC_SW_BW_2) +
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dvfsrc_read(DVFSRC_SW_BW_3) +
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dvfsrc_read(DVFSRC_SW_BW_4);
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if (qos_total_bw < 0x19)
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return 0;
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else if (qos_total_bw < 0x26)
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return 1;
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else if (qos_total_bw < 0x33)
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return 2;
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else if (qos_total_bw < 0x3B)
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return 3;
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else if (qos_total_bw < 0x4C)
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return 4;
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else if (qos_total_bw < 0x66)
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return 5;
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else
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return 6;
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return 0;
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}
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static int dvfsrc_get_emi_mon_gear(void)
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{
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unsigned int total_bw_status;
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int i;
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total_bw_status = vcorefs_get_total_emi_status() & 0x3F;
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for (i = 5; i >= 0 ; i--) {
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if ((total_bw_status >> i) > 0)
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return i + 1;
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}
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return 0;
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}
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static u32 dvfsrc_calc_hrt_opp(int data)
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{
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if (data < 0x04B0)
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return DDR_OPP_6;
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else if (data < 0x0708)
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return DDR_OPP_5;
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else if (data < 0x0B80)
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return DDR_OPP_4;
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else if (data < 0x0D69)
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return DDR_OPP_3;
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else if (data < 0x1183)
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return DDR_OPP_2;
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else if (data < 0x18A6)
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return DDR_OPP_1;
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else
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return DDR_OPP_0;
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}
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void dvfsrc_set_isp_hrt_bw(int data)
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{
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data = (data + 29) / 30;
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if (data > 0x3FF)
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data = 0x3FF;
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dvfsrc_write(DVFSRC_ISP_HRT, data);
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}
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u32 dvfsrc_calc_isp_hrt_opp(int data)
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{
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return dvfsrc_calc_hrt_opp(((data + 29) / 30) * 30);
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}
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u32 dvfsrc_get_pcie_vcore_status(void)
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{
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u32 val, pcie_en;
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val = dvfsrc_read(DVFSRC_DEBUG_STA_2);
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pcie_en = (val >> DEBUG_STA2_PCIE_SHIFT) & DEBUG_STA2_PCIE_MASK;
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if (pcie_en)
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return 1;
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else
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return 0;
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}
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struct regulator *dvfsrc_vcore_requlator(struct device *dev)
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{
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return regulator_get(dev, "vcore");
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}
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#ifdef AUTOK_ENABLE
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__weak int emmc_autok(void)
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{
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pr_info("NOT SUPPORT EMMC AUTOK\n");
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return 0;
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}
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__weak int sd_autok(void)
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{
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pr_info("NOT SUPPORT SD AUTOK\n");
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return 0;
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}
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__weak int sdio_autok(void)
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{
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pr_info("NOT SUPPORT SDIO AUTOK\n");
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return 0;
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}
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void begin_autok_task(void)
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{
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/* notify MM DVFS for msdc autok start */
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mmdvfs_prepare_action(MMDVFS_PREPARE_CALIBRATION_START);
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}
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void finish_autok_task(void)
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{
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/* check if dvfs force is released */
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int force = mtk_pm_qos_request(MTK_PM_QOS_VCORE_DVFS_FORCE_OPP);
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/* notify MM DVFS for msdc autok finish */
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mmdvfs_prepare_action(MMDVFS_PREPARE_CALIBRATION_END);
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if (force >= 0 && force < VCORE_DVFS_OPP_NUM)
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pr_info("autok task not release force opp: %d\n", force);
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}
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static void dvfsrc_autok_manager(void)
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{
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int r = 0;
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begin_autok_task();
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r = emmc_autok();
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pr_info("EMMC autok done: %s\n", (r == 0) ? "Yes" : "No");
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r = sd_autok();
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pr_info("SD autok done: %s\n", (r == 0) ? "Yes" : "No");
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r = sdio_autok();
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pr_info("SDIO autok done: %s\n", (r == 0) ? "Yes" : "No");
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finish_autok_task();
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}
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#endif
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static void dvfsrc_update_md_scenario(bool blank)
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{
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#ifdef DVFSRC_FB_MD_TABLE_SWITCH
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if (blank)
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dvfsrc_write(DVFSRC_95MD_SCEN_BW1_T, 0x22244444);
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else
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dvfsrc_write(DVFSRC_95MD_SCEN_BW1_T, 0x22244444);
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#endif
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}
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static int dvfsrc_fb_notifier_call(struct notifier_block *self,
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unsigned long event, void *data)
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{
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struct fb_event *evdata = data;
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int blank;
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if (event != FB_EVENT_BLANK)
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return 0;
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blank = *(int *)evdata->data;
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switch (blank) {
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case FB_BLANK_UNBLANK:
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dvfsrc_update_md_scenario(false);
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break;
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case FB_BLANK_POWERDOWN:
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dvfsrc_update_md_scenario(true);
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break;
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default:
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break;
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}
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return 0;
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}
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static struct notifier_block dvfsrc_fb_notifier = {
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.notifier_call = dvfsrc_fb_notifier_call,
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};
|
|
|
|
void helio_dvfsrc_platform_pre_init(struct helio_dvfsrc *dvfsrc)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dvfsrc->dev);
|
|
struct resource *res;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
|
|
dvfsrc->spm_regs = devm_ioremap(&pdev->dev,
|
|
res->start, resource_size(res));
|
|
if (IS_ERR(dvfsrc->spm_regs))
|
|
pr_info("not get spm register\n");
|
|
|
|
}
|
|
|
|
__weak void mtk_pm_qos_trace_dbg_dump(int mtk_pm_qos_class)
|
|
{
|
|
}
|
|
|
|
void dvfsrc_suspend_cb(struct helio_dvfsrc *dvfsrc)
|
|
{
|
|
int sw_req;
|
|
|
|
sw_req = dvfsrc_read(DVFSRC_SW_REQ3);
|
|
pr_info("[DVFSRC] V:%d, F_OPP:%d, RG:%08x, %08x, %08x, %08x\n",
|
|
get_cur_vcore_uv(),
|
|
mtk_pm_qos_request(MTK_PM_QOS_VCORE_DVFS_FORCE_OPP),
|
|
dvfsrc_read(DVFSRC_CURRENT_LEVEL),
|
|
dvfsrc_read(DVFSRC_SW_REQ2),
|
|
sw_req,
|
|
dvfsrc_read(DVFSRC_DEBUG_STA_0));
|
|
|
|
if (sw_req & (DDR_SW_AP_MASK << DDR_SW_AP_SHIFT))
|
|
mtk_pm_qos_trace_dbg_dump(MTK_PM_QOS_DDR_OPP);
|
|
|
|
if (sw_req & (VCORE_SW_AP_MASK << VCORE_SW_AP_SHIFT))
|
|
mtk_pm_qos_trace_dbg_dump(MTK_PM_QOS_VCORE_OPP);
|
|
}
|
|
|
|
void dvfsrc_resume_cb(struct helio_dvfsrc *dvfsrc)
|
|
{
|
|
|
|
}
|
|
|
|
void helio_dvfsrc_platform_init(struct helio_dvfsrc *dvfsrc)
|
|
{
|
|
int spmfw_idx = 0;
|
|
struct reg_config *config;
|
|
int idx = 0;
|
|
|
|
sysfs_merge_group(&dvfsrc->dev->kobj, &mt6853_helio_dvfsrc_attr_group);
|
|
|
|
config = dvfsrc_init_configs[spmfw_idx];
|
|
|
|
while (config[idx].offset != -1) {
|
|
dvfsrc_write(config[idx].offset, config[idx].val);
|
|
idx++;
|
|
}
|
|
#ifdef AUTOK_ENABLE
|
|
dvfsrc_autok_manager();
|
|
#endif
|
|
|
|
fb_register_client(&dvfsrc_fb_notifier);
|
|
}
|
|
|
|
int vcore_pmic_to_uv(int pmic_val)
|
|
{
|
|
return __vcore_pmic_to_uv(pmic_val);
|
|
}
|
|
int vcore_uv_to_pmic(int vcore_uv)
|
|
{
|
|
return __vcore_uv_to_pmic(vcore_uv);
|
|
}
|
|
|
|
void get_spm_reg(char *p)
|
|
{
|
|
p += sprintf(p, "%-24s: 0x%08x\n",
|
|
"POWERON_CONFIG_EN",
|
|
spm_reg_read(POWERON_CONFIG_EN));
|
|
p += sprintf(p, "%-24s: 0x%08x\n",
|
|
"SPM_SW_FLAG_0",
|
|
spm_reg_read(SPM_SW_FLAG_0));
|
|
p += sprintf(p, "%-24s: 0x%08x\n",
|
|
"SPM_PC_STA",
|
|
spm_reg_read(SPM_PC_STA));
|
|
p += sprintf(p, "%-24s: 0x%08x\n",
|
|
"SPM_DVFS_LEVEL",
|
|
spm_reg_read(SPM_DVFS_LEVEL));
|
|
p += sprintf(p, "%-24s: 0x%08x\n",
|
|
"SPM_DVS_DFS_LEVEL",
|
|
spm_reg_read(SPM_DVS_DFS_LEVEL));
|
|
p += sprintf(p, "%-24s: 0x%08x\n",
|
|
"SPM_DVFS_STA",
|
|
spm_reg_read(SPM_DVFS_STA));
|
|
p += sprintf(p, "%-24s: 0x%08x\n",
|
|
"SPM_DVFS_MISC",
|
|
spm_reg_read(SPM_DVFS_MISC));
|
|
p += sprintf(p, "%-24s: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
|
|
"SPM_DVFS_CMD0~4",
|
|
spm_reg_read(SPM_DVFS_CMD0),
|
|
spm_reg_read(SPM_DVFS_CMD1),
|
|
spm_reg_read(SPM_DVFS_CMD2),
|
|
spm_reg_read(SPM_DVFS_CMD3),
|
|
spm_reg_read(SPM_DVFS_CMD4));
|
|
}
|
|
|
|
void get_opp_info(char *p)
|
|
{
|
|
#if defined(CONFIG_FPGA_EARLY_PORTING) || !defined(CONFIG_MTK_PMIC_COMMON)
|
|
int pmic_val = 0;
|
|
#else
|
|
int pmic_val = pmic_get_register_value(PMIC_VCORE_ADDR);
|
|
#endif
|
|
#ifdef CONFIG_MEDIATEK_DRAMC
|
|
int ddr_khz = mtk_dramc_get_data_rate() * 1000;
|
|
#else
|
|
int ddr_khz = 0;
|
|
#endif
|
|
int vcore_uv = vcore_pmic_to_uv(pmic_val);
|
|
|
|
p += sprintf(p, "%-10s: %-8u uv (PMIC: 0x%x)\n",
|
|
"Vcore", vcore_uv, vcore_uv_to_pmic(vcore_uv));
|
|
p += sprintf(p, "%-10s: %-8u khz\n", "DDR", ddr_khz);
|
|
p += sprintf(p, "%-10s: %d\n", "CT_MODE", dvfsrc_ct_mode());
|
|
p += sprintf(p, "%-10s: %x\n", "V_MODE", dvfsrc_vcore_mode());
|
|
}
|
|
|
|
|
|
/* met profile table */
|
|
static unsigned int met_vcorefs_src[SRC_MAX];
|
|
|
|
static char *met_src_name[SRC_MAX] = {
|
|
"MD2SPM",
|
|
"SRC_DDR_OPP",
|
|
"DDR__SW_REQ1_SPM",
|
|
"DDR__SW_REQ2_CM",
|
|
"DDR__SW_REQ3_PMQOS",
|
|
"DDR__QOS_BW",
|
|
"DDR__EMI_TOTAL",
|
|
"DDR__HRT_BW",
|
|
"DDR__HIFI",
|
|
"DDR__HIFI_LATENCY",
|
|
"DDR__MD_LATENCY",
|
|
"DDR__MD_DDR",
|
|
"DDR__MD_LEVEL_MASK",
|
|
"SRC_VCORE_OPP",
|
|
"VCORE__SW_REQ3_PMQOS",
|
|
"VCORE__SCP",
|
|
"VCORE__HIFI",
|
|
"VCORE__PCIE",
|
|
"SCP_REQ",
|
|
"PMQOS_TATOL",
|
|
"PMQOS_BW0",
|
|
"PMQOS_BW1",
|
|
"PMQOS_BW2",
|
|
"PMQOS_BW3",
|
|
"PMQOS_BW4",
|
|
"TOTAL_EMI_BW",
|
|
"HRT_MD_BW",
|
|
"HRT_DISP_BW",
|
|
"HRT_ISP_BW",
|
|
"MD_SCENARIO",
|
|
"HIFI_SCENARIO_IDX",
|
|
"MD_EMI_LATENCY",
|
|
};
|
|
|
|
/* met profile function */
|
|
int vcorefs_get_src_req_num(void)
|
|
{
|
|
return SRC_MAX;
|
|
}
|
|
EXPORT_SYMBOL(vcorefs_get_src_req_num);
|
|
|
|
char **vcorefs_get_src_req_name(void)
|
|
{
|
|
return met_src_name;
|
|
}
|
|
EXPORT_SYMBOL(vcorefs_get_src_req_name);
|
|
|
|
static u32 vcorefs_get_md_level_mask_ddr(void)
|
|
{
|
|
int md_srclk, vopp;
|
|
|
|
if (dvfsrc_read(DVFSRC_BASIC_CONTROL_3) & 0x8) {
|
|
md_srclk = dvfsrc_read(DVFSRC_DEBUG_STA_0);
|
|
vopp = get_cur_vcore_opp();
|
|
md_srclk = (md_srclk >> MD_SRC_CLK_DEBUG_SHIFT)
|
|
& MD_SRC_CLK_DEBUG_MASK;
|
|
|
|
if (vopp != 3 && md_srclk == 1)
|
|
return 2;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void vcorefs_get_src_ddr_req(void)
|
|
{
|
|
unsigned int sw_req;
|
|
|
|
met_vcorefs_src[DDR_OPP_IDX] =
|
|
get_cur_ddr_opp();
|
|
|
|
sw_req = dvfsrc_read(DVFSRC_SW_REQ1);
|
|
met_vcorefs_src[DDR_SW_REQ1_SPM_IDX] =
|
|
(sw_req >> DDR_SW_AP_SHIFT) & DDR_SW_AP_MASK;
|
|
|
|
sw_req = dvfsrc_read(DVFSRC_SW_REQ2);
|
|
met_vcorefs_src[DDR_SW_REQ2_CM_IDX] =
|
|
(sw_req >> DDR_SW_AP_SHIFT) & DDR_SW_AP_MASK;
|
|
|
|
sw_req = dvfsrc_read(DVFSRC_SW_REQ3);
|
|
met_vcorefs_src[DDR_SW_REQ3_PMQOS_IDX] =
|
|
(sw_req >> DDR_SW_AP_SHIFT) & DDR_SW_AP_MASK;
|
|
|
|
met_vcorefs_src[DDR_QOS_BW_IDX] =
|
|
dvfsrc_get_ddr_qos();
|
|
|
|
met_vcorefs_src[DDR_EMI_TOTAL_IDX] =
|
|
dvfsrc_get_emi_mon_gear();
|
|
|
|
met_vcorefs_src[DDR_HRT_BW_IDX] =
|
|
vcorefs_get_hrt_bw_ddr();
|
|
|
|
met_vcorefs_src[DDR_HIFI_IDX] =
|
|
vcorefs_get_hifi_ddr_status();
|
|
|
|
met_vcorefs_src[DDR_HIFI_LATENCY_IDX] =
|
|
vcorefs_get_hifi_rising_ddr();
|
|
|
|
met_vcorefs_src[DDR_MD_LATENCY_IDX] =
|
|
vcorefs_get_md_imp_ddr();
|
|
|
|
met_vcorefs_src[DDR_MD_DDR_IDX] =
|
|
vcorefs_get_md_scenario_ddr();
|
|
|
|
met_vcorefs_src[DDR_MD_SRCLK_IDX] =
|
|
vcorefs_get_md_level_mask_ddr();
|
|
}
|
|
|
|
static void vcorefs_get_src_vcore_req(void)
|
|
{
|
|
u32 sw_req;
|
|
u32 scp_en;
|
|
|
|
scp_en = vcorefs_get_scp_req_status();
|
|
|
|
met_vcorefs_src[VCORE_OPP_IDX] =
|
|
get_cur_vcore_opp();
|
|
|
|
sw_req = dvfsrc_read(DVFSRC_SW_REQ3);
|
|
met_vcorefs_src[VCORE_SW_REQ3_PMQOS_IDX] =
|
|
(sw_req >> VCORE_SW_AP_SHIFT) & VCORE_SW_AP_MASK;
|
|
|
|
if (scp_en) {
|
|
sw_req = dvfsrc_read(DVFSRC_VCORE_REQUEST);
|
|
met_vcorefs_src[VCORE_SCP_IDX] =
|
|
(sw_req >> VCORE_SCP_GEAR_SHIFT) & VCORE_SCP_GEAR_MASK;
|
|
} else
|
|
met_vcorefs_src[VCORE_SCP_IDX] = 0;
|
|
|
|
met_vcorefs_src[VCORE_HIFI_IDX] =
|
|
vcorefs_get_hifi_vcore_status();
|
|
|
|
met_vcorefs_src[VCORE_PCIE_IDX] =
|
|
dvfsrc_get_pcie_vcore_status();
|
|
}
|
|
|
|
static void vcorefs_get_src_misc_info(void)
|
|
{
|
|
u32 qos_bw0, qos_bw1, qos_bw2, qos_bw3, qos_bw4;
|
|
|
|
qos_bw0 = dvfsrc_read(DVFSRC_SW_BW_0);
|
|
qos_bw1 = dvfsrc_read(DVFSRC_SW_BW_1);
|
|
qos_bw2 = dvfsrc_read(DVFSRC_SW_BW_2);
|
|
qos_bw3 = dvfsrc_read(DVFSRC_SW_BW_3);
|
|
qos_bw4 = dvfsrc_read(DVFSRC_SW_BW_4);
|
|
|
|
met_vcorefs_src[SRC_MD2SPM_IDX] =
|
|
vcorefs_get_md_scenario() & 0x1FFFF;
|
|
|
|
met_vcorefs_src[SRC_SCP_REQ_IDX] =
|
|
vcorefs_get_scp_req_status();
|
|
|
|
met_vcorefs_src[SRC_PMQOS_TATOL_IDX] =
|
|
qos_bw0 + qos_bw1 + qos_bw2 + qos_bw3 + qos_bw4;
|
|
|
|
met_vcorefs_src[SRC_PMQOS_BW0_IDX] =
|
|
qos_bw0;
|
|
|
|
met_vcorefs_src[SRC_PMQOS_BW1_IDX] =
|
|
qos_bw1;
|
|
|
|
met_vcorefs_src[SRC_PMQOS_BW2_IDX] =
|
|
qos_bw2;
|
|
|
|
met_vcorefs_src[SRC_PMQOS_BW3_IDX] =
|
|
qos_bw3;
|
|
|
|
met_vcorefs_src[SRC_PMQOS_BW4_IDX] =
|
|
qos_bw4;
|
|
|
|
met_vcorefs_src[SRC_HRT_MD_BW_IDX] =
|
|
dvfsrc_get_md_bw();
|
|
|
|
met_vcorefs_src[SRC_HRT_ISP_BW_IDX] =
|
|
dvfsrc_read(DVFSRC_ISP_HRT);
|
|
|
|
met_vcorefs_src[SRC_MD_SCENARIO_IDX] =
|
|
vcorefs_get_md_scenario();
|
|
|
|
met_vcorefs_src[SRC_HIFI_SCENARIO_IDX] =
|
|
vcorefs_get_hifi_scenario();
|
|
|
|
met_vcorefs_src[SRC_MD_EMI_LATENCY_IDX] =
|
|
vcorefs_get_md_emi_latency_status();
|
|
|
|
}
|
|
|
|
|
|
int dvfsrc_latch_register(int enable)
|
|
{
|
|
#ifdef CONFIG_MTK_DBGTOP
|
|
return mtk_dbgtop_cfg_dvfsrc(1);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
unsigned int *vcorefs_get_src_req(void)
|
|
{
|
|
vcorefs_get_src_ddr_req();
|
|
vcorefs_get_src_vcore_req();
|
|
vcorefs_get_src_misc_info();
|
|
|
|
vcorefs_trace_qos();
|
|
|
|
return met_vcorefs_src;
|
|
}
|
|
EXPORT_SYMBOL(vcorefs_get_src_req);
|
|
|
|
|
|
int get_cur_ddr_ratio(void)
|
|
{
|
|
int idx;
|
|
|
|
if (!is_dvfsrc_enabled())
|
|
return 0;
|
|
|
|
idx = get_cur_vcore_dvfs_opp();
|
|
|
|
if (idx >= VCORE_DVFS_OPP_NUM)
|
|
return 0;
|
|
|
|
if (get_ddr_opp(idx) < DDR_OPP_6)
|
|
return 8;
|
|
else
|
|
return 4;
|
|
}
|
|
EXPORT_SYMBOL(get_cur_ddr_ratio);
|
|
|