151 lines
4.1 KiB
C
151 lines
4.1 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Ke Yu
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* Zhiyuan Lv <zhiyuan.lv@intel.com>
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*
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* Contributors:
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* Terrence Xu <terrence.xu@intel.com>
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* Changbin Du <changbin.du@intel.com>
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* Bing Niu <bing.niu@intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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*/
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#ifndef _GVT_EDID_H_
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#define _GVT_EDID_H_
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#define EDID_SIZE 128
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#define EDID_ADDR 0x50 /* Linux hvm EDID addr */
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#define GVT_AUX_NATIVE_WRITE 0x8
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#define GVT_AUX_NATIVE_READ 0x9
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#define GVT_AUX_I2C_WRITE 0x0
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#define GVT_AUX_I2C_READ 0x1
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#define GVT_AUX_I2C_STATUS 0x2
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#define GVT_AUX_I2C_MOT 0x4
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#define GVT_AUX_I2C_REPLY_ACK 0x0
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struct intel_vgpu_edid_data {
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bool data_valid;
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unsigned char edid_block[EDID_SIZE];
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};
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enum gmbus_cycle_type {
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GMBUS_NOCYCLE = 0x0,
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NIDX_NS_W = 0x1,
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IDX_NS_W = 0x3,
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GMBUS_STOP = 0x4,
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NIDX_STOP = 0x5,
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IDX_STOP = 0x7
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};
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/*
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* States of GMBUS
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*
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* GMBUS0-3 could be related to the EDID virtualization. Another two GMBUS
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* registers, GMBUS4 (interrupt mask) and GMBUS5 (2 byte indes register), are
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* not considered here. Below describes the usage of GMBUS registers that are
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* cared by the EDID virtualization
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*
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* GMBUS0:
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* R/W
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* port selection. value of bit0 - bit2 corresponds to the GPIO registers.
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*
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* GMBUS1:
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* R/W Protect
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* Command and Status.
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* bit0 is the direction bit: 1 is read; 0 is write.
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* bit1 - bit7 is slave 7-bit address.
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* bit16 - bit24 total byte count (ignore?)
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*
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* GMBUS2:
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* Most of bits are read only except bit 15 (IN_USE)
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* Status register
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* bit0 - bit8 current byte count
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* bit 11: hardware ready;
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*
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* GMBUS3:
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* Read/Write
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* Data for transfer
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*/
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/* From hw specs, Other phases like START, ADDRESS, INDEX
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* are invisible to GMBUS MMIO interface. So no definitions
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* in below enum types
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*/
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enum gvt_gmbus_phase {
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GMBUS_IDLE_PHASE = 0,
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GMBUS_DATA_PHASE,
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GMBUS_WAIT_PHASE,
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//GMBUS_STOP_PHASE,
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GMBUS_MAX_PHASE
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};
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struct intel_vgpu_i2c_gmbus {
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unsigned int total_byte_count; /* from GMBUS1 */
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enum gmbus_cycle_type cycle_type;
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enum gvt_gmbus_phase phase;
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};
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struct intel_vgpu_i2c_aux_ch {
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bool i2c_over_aux_ch;
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bool aux_ch_mot;
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};
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enum i2c_state {
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I2C_NOT_SPECIFIED = 0,
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I2C_GMBUS = 1,
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I2C_AUX_CH = 2
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};
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/* I2C sequences cannot interleave.
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* GMBUS and AUX_CH sequences cannot interleave.
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*/
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struct intel_vgpu_i2c_edid {
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enum i2c_state state;
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unsigned int port;
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bool slave_selected;
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bool edid_available;
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unsigned int current_edid_read;
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struct intel_vgpu_i2c_gmbus gmbus;
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struct intel_vgpu_i2c_aux_ch aux_ch;
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};
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void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu);
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int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes);
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int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes);
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void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
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int port_idx,
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unsigned int offset,
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void *p_data);
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#endif /*_GVT_EDID_H_*/
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