105 lines
3.6 KiB
C
105 lines
3.6 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Ke Yu
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* Kevin Tian <kevin.tian@intel.com>
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* Dexuan Cui
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*
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* Contributors:
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* Tina Zhang <tina.zhang@intel.com>
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* Min He <min.he@intel.com>
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* Niu Bing <bing.niu@intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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*/
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#ifndef _GVT_MMIO_H_
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#define _GVT_MMIO_H_
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struct intel_gvt;
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struct intel_vgpu;
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#define D_BDW (1 << 0)
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#define D_SKL (1 << 1)
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#define D_KBL (1 << 2)
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#define D_BXT (1 << 3)
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#define D_GEN9PLUS (D_SKL | D_KBL | D_BXT)
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#define D_GEN8PLUS (D_BDW | D_SKL | D_KBL | D_BXT)
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#define D_SKL_PLUS (D_SKL | D_KBL | D_BXT)
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#define D_BDW_PLUS (D_BDW | D_SKL | D_KBL | D_BXT)
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#define D_PRE_SKL (D_BDW)
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#define D_ALL (D_BDW | D_SKL | D_KBL | D_BXT)
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typedef int (*gvt_mmio_func)(struct intel_vgpu *, unsigned int, void *,
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unsigned int);
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struct intel_gvt_mmio_info {
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u32 offset;
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u64 ro_mask;
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u32 device;
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gvt_mmio_func read;
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gvt_mmio_func write;
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u32 addr_range;
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struct hlist_node node;
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};
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int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
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unsigned int reg);
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unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt);
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bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device);
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int intel_gvt_setup_mmio_info(struct intel_gvt *gvt);
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void intel_gvt_clean_mmio_info(struct intel_gvt *gvt);
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int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
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int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
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void *data);
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int intel_vgpu_init_mmio(struct intel_vgpu *vgpu);
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void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr);
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void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu);
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int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa);
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int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
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void *p_data, unsigned int bytes);
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int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
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void *p_data, unsigned int bytes);
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int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes);
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int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes);
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bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
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unsigned int offset);
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int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
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void *pdata, unsigned int bytes, bool is_read);
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int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes);
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#endif
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