568 lines
14 KiB
C
568 lines
14 KiB
C
/* cx25840 audio functions
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/videodev2.h>
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#include <linux/i2c.h>
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#include <media/v4l2-common.h>
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#include <media/drv-intf/cx25840.h>
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#include "cx25840-core.h"
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/*
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* Note: The PLL and SRC parameters are based on a reference frequency that
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* would ideally be:
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*
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* NTSC Color subcarrier freq * 8 = 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
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*
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* However, it's not the exact reference frequency that matters, only that the
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* firmware and modules that comprise the driver for a particular board all
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* use the same value (close to the ideal value).
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*
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* Comments below will note which reference frequency is assumed for various
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* parameters. They will usually be one of
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*
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* ref_freq = 28.636360 MHz
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* or
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* ref_freq = 28.636363 MHz
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*/
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static int cx25840_set_audclk_freq(struct i2c_client *client, u32 freq)
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{
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struct cx25840_state *state = to_state(i2c_get_clientdata(client));
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if (state->aud_input != CX25840_AUDIO_SERIAL) {
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switch (freq) {
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case 32000:
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10
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*/
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cx25840_write4(client, 0x108, 0x1006040f);
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/*
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* VID_PLL Fraction (register 0x10c) = 0x2be2fe
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* 28636360 * 0xf.15f17f0/4 = 108 MHz
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* 432 MHz pre-postdivide
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*/
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/*
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* AUX_PLL Fraction = 0x1bb39ee
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* 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384
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* 196.6 MHz pre-postdivide
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* FIXME < 200 MHz is out of specified valid range
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* FIXME 28636363 ref_freq doesn't match VID PLL ref
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*/
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cx25840_write4(client, 0x110, 0x01bb39ee);
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/*
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* SA_MCLK_SEL = 1
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* SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider
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*/
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cx25840_write(client, 0x127, 0x50);
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if (is_cx2583x(state))
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break;
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/* src3/4/6_ctl */
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/* 0x1.f77f = (4 * 28636360/8 * 2/455) / 32000 */
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cx25840_write4(client, 0x900, 0x0801f77f);
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cx25840_write4(client, 0x904, 0x0801f77f);
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cx25840_write4(client, 0x90c, 0x0801f77f);
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break;
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case 44100:
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x10
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*/
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cx25840_write4(client, 0x108, 0x1009040f);
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/*
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* VID_PLL Fraction (register 0x10c) = 0x2be2fe
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* 28636360 * 0xf.15f17f0/4 = 108 MHz
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* 432 MHz pre-postdivide
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*/
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/*
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* AUX_PLL Fraction = 0x0ec6bd6
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* 28636363 * 0x9.7635eb0/0x10 = 44100 * 384
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* 271 MHz pre-postdivide
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* FIXME 28636363 ref_freq doesn't match VID PLL ref
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*/
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cx25840_write4(client, 0x110, 0x00ec6bd6);
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/*
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* SA_MCLK_SEL = 1
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* SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider
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*/
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cx25840_write(client, 0x127, 0x50);
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if (is_cx2583x(state))
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break;
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/* src3/4/6_ctl */
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/* 0x1.6d59 = (4 * 28636360/8 * 2/455) / 44100 */
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cx25840_write4(client, 0x900, 0x08016d59);
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cx25840_write4(client, 0x904, 0x08016d59);
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cx25840_write4(client, 0x90c, 0x08016d59);
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break;
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case 48000:
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x10
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*/
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cx25840_write4(client, 0x108, 0x100a040f);
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/*
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* VID_PLL Fraction (register 0x10c) = 0x2be2fe
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* 28636360 * 0xf.15f17f0/4 = 108 MHz
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* 432 MHz pre-postdivide
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*/
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/*
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* AUX_PLL Fraction = 0x098d6e5
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* 28636363 * 0xa.4c6b728/0x10 = 48000 * 384
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* 295 MHz pre-postdivide
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* FIXME 28636363 ref_freq doesn't match VID PLL ref
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*/
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cx25840_write4(client, 0x110, 0x0098d6e5);
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/*
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* SA_MCLK_SEL = 1
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* SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider
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*/
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cx25840_write(client, 0x127, 0x50);
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if (is_cx2583x(state))
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break;
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/* src3/4/6_ctl */
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/* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
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cx25840_write4(client, 0x900, 0x08014faa);
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cx25840_write4(client, 0x904, 0x08014faa);
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cx25840_write4(client, 0x90c, 0x08014faa);
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break;
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}
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} else {
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switch (freq) {
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case 32000:
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x08, AUX PLL Post Divider = 0x1e
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*/
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cx25840_write4(client, 0x108, 0x1e08040f);
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/*
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* VID_PLL Fraction (register 0x10c) = 0x2be2fe
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* 28636360 * 0xf.15f17f0/4 = 108 MHz
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* 432 MHz pre-postdivide
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*/
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/*
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* AUX_PLL Fraction = 0x12a0869
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* 28636363 * 0x8.9504348/0x1e = 32000 * 256
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* 246 MHz pre-postdivide
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* FIXME 28636363 ref_freq doesn't match VID PLL ref
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*/
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cx25840_write4(client, 0x110, 0x012a0869);
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/*
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* SA_MCLK_SEL = 1
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* SA_MCLK_DIV = 0x14 = 256/384 * AUX_PLL post dvivider
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*/
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cx25840_write(client, 0x127, 0x54);
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if (is_cx2583x(state))
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break;
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/* src1_ctl */
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/* 0x1.0000 = 32000/32000 */
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cx25840_write4(client, 0x8f8, 0x08010000);
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/* src3/4/6_ctl */
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/* 0x2.0000 = 2 * (32000/32000) */
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cx25840_write4(client, 0x900, 0x08020000);
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cx25840_write4(client, 0x904, 0x08020000);
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cx25840_write4(client, 0x90c, 0x08020000);
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break;
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case 44100:
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x18
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*/
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cx25840_write4(client, 0x108, 0x1809040f);
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/*
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* VID_PLL Fraction (register 0x10c) = 0x2be2fe
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* 28636360 * 0xf.15f17f0/4 = 108 MHz
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* 432 MHz pre-postdivide
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*/
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/*
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* AUX_PLL Fraction = 0x0ec6bd6
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* 28636363 * 0x9.7635eb0/0x18 = 44100 * 256
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* 271 MHz pre-postdivide
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* FIXME 28636363 ref_freq doesn't match VID PLL ref
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*/
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cx25840_write4(client, 0x110, 0x00ec6bd6);
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/*
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* SA_MCLK_SEL = 1
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* SA_MCLK_DIV = 0x10 = 256/384 * AUX_PLL post dvivider
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*/
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cx25840_write(client, 0x127, 0x50);
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if (is_cx2583x(state))
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break;
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/* src1_ctl */
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/* 0x1.60cd = 44100/32000 */
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cx25840_write4(client, 0x8f8, 0x080160cd);
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/* src3/4/6_ctl */
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/* 0x1.7385 = 2 * (32000/44100) */
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cx25840_write4(client, 0x900, 0x08017385);
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cx25840_write4(client, 0x904, 0x08017385);
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cx25840_write4(client, 0x90c, 0x08017385);
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break;
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case 48000:
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/*
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* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
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* AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x18
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*/
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cx25840_write4(client, 0x108, 0x180a040f);
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/*
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* VID_PLL Fraction (register 0x10c) = 0x2be2fe
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* 28636360 * 0xf.15f17f0/4 = 108 MHz
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* 432 MHz pre-postdivide
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*/
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/*
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* AUX_PLL Fraction = 0x098d6e5
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* 28636363 * 0xa.4c6b728/0x18 = 48000 * 256
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* 295 MHz pre-postdivide
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* FIXME 28636363 ref_freq doesn't match VID PLL ref
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*/
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cx25840_write4(client, 0x110, 0x0098d6e5);
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/*
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* SA_MCLK_SEL = 1
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* SA_MCLK_DIV = 0x10 = 256/384 * AUX_PLL post dvivider
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*/
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cx25840_write(client, 0x127, 0x50);
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if (is_cx2583x(state))
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break;
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/* src1_ctl */
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/* 0x1.8000 = 48000/32000 */
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cx25840_write4(client, 0x8f8, 0x08018000);
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/* src3/4/6_ctl */
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/* 0x1.5555 = 2 * (32000/48000) */
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cx25840_write4(client, 0x900, 0x08015555);
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cx25840_write4(client, 0x904, 0x08015555);
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cx25840_write4(client, 0x90c, 0x08015555);
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break;
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}
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}
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state->audclk_freq = freq;
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return 0;
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}
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static inline int cx25836_set_audclk_freq(struct i2c_client *client, u32 freq)
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{
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return cx25840_set_audclk_freq(client, freq);
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}
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static int cx23885_set_audclk_freq(struct i2c_client *client, u32 freq)
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{
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struct cx25840_state *state = to_state(i2c_get_clientdata(client));
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if (state->aud_input != CX25840_AUDIO_SERIAL) {
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switch (freq) {
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case 32000:
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case 44100:
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case 48000:
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/* We don't have register values
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* so avoid destroying registers. */
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/* FIXME return -EINVAL; */
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break;
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}
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} else {
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switch (freq) {
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case 32000:
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case 44100:
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/* We don't have register values
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* so avoid destroying registers. */
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/* FIXME return -EINVAL; */
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break;
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case 48000:
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/* src1_ctl */
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/* 0x1.867c = 48000 / (2 * 28636360/8 * 2/455) */
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cx25840_write4(client, 0x8f8, 0x0801867c);
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/* src3/4/6_ctl */
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/* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
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cx25840_write4(client, 0x900, 0x08014faa);
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cx25840_write4(client, 0x904, 0x08014faa);
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cx25840_write4(client, 0x90c, 0x08014faa);
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break;
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}
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}
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state->audclk_freq = freq;
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return 0;
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}
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static int cx231xx_set_audclk_freq(struct i2c_client *client, u32 freq)
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{
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struct cx25840_state *state = to_state(i2c_get_clientdata(client));
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if (state->aud_input != CX25840_AUDIO_SERIAL) {
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switch (freq) {
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case 32000:
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/* src3/4/6_ctl */
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/* 0x1.f77f = (4 * 28636360/8 * 2/455) / 32000 */
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cx25840_write4(client, 0x900, 0x0801f77f);
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cx25840_write4(client, 0x904, 0x0801f77f);
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cx25840_write4(client, 0x90c, 0x0801f77f);
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break;
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case 44100:
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/* src3/4/6_ctl */
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/* 0x1.6d59 = (4 * 28636360/8 * 2/455) / 44100 */
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cx25840_write4(client, 0x900, 0x08016d59);
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cx25840_write4(client, 0x904, 0x08016d59);
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cx25840_write4(client, 0x90c, 0x08016d59);
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break;
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case 48000:
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/* src3/4/6_ctl */
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/* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
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cx25840_write4(client, 0x900, 0x08014faa);
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cx25840_write4(client, 0x904, 0x08014faa);
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cx25840_write4(client, 0x90c, 0x08014faa);
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break;
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}
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} else {
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switch (freq) {
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/* FIXME These cases make different assumptions about audclk */
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case 32000:
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/* src1_ctl */
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/* 0x1.0000 = 32000/32000 */
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cx25840_write4(client, 0x8f8, 0x08010000);
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/* src3/4/6_ctl */
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/* 0x2.0000 = 2 * (32000/32000) */
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cx25840_write4(client, 0x900, 0x08020000);
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cx25840_write4(client, 0x904, 0x08020000);
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cx25840_write4(client, 0x90c, 0x08020000);
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break;
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case 44100:
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/* src1_ctl */
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/* 0x1.60cd = 44100/32000 */
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cx25840_write4(client, 0x8f8, 0x080160cd);
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/* src3/4/6_ctl */
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/* 0x1.7385 = 2 * (32000/44100) */
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cx25840_write4(client, 0x900, 0x08017385);
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cx25840_write4(client, 0x904, 0x08017385);
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cx25840_write4(client, 0x90c, 0x08017385);
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break;
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case 48000:
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/* src1_ctl */
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/* 0x1.867c = 48000 / (2 * 28636360/8 * 2/455) */
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cx25840_write4(client, 0x8f8, 0x0801867c);
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/* src3/4/6_ctl */
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/* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
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cx25840_write4(client, 0x900, 0x08014faa);
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cx25840_write4(client, 0x904, 0x08014faa);
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cx25840_write4(client, 0x90c, 0x08014faa);
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break;
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}
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}
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state->audclk_freq = freq;
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return 0;
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}
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static int set_audclk_freq(struct i2c_client *client, u32 freq)
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{
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struct cx25840_state *state = to_state(i2c_get_clientdata(client));
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if (freq != 32000 && freq != 44100 && freq != 48000)
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return -EINVAL;
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if (is_cx231xx(state))
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return cx231xx_set_audclk_freq(client, freq);
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if (is_cx2388x(state))
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return cx23885_set_audclk_freq(client, freq);
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if (is_cx2583x(state))
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return cx25836_set_audclk_freq(client, freq);
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return cx25840_set_audclk_freq(client, freq);
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}
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void cx25840_audio_set_path(struct i2c_client *client)
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{
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struct cx25840_state *state = to_state(i2c_get_clientdata(client));
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if (!is_cx2583x(state)) {
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/* assert soft reset */
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cx25840_and_or(client, 0x810, ~0x1, 0x01);
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/* stop microcontroller */
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cx25840_and_or(client, 0x803, ~0x10, 0);
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/* Mute everything to prevent the PFFT! */
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cx25840_write(client, 0x8d3, 0x1f);
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if (state->aud_input == CX25840_AUDIO_SERIAL) {
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/* Set Path1 to Serial Audio Input */
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cx25840_write4(client, 0x8d0, 0x01011012);
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/* The microcontroller should not be started for the
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* non-tuner inputs: autodetection is specific for
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* TV audio. */
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} else {
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/* Set Path1 to Analog Demod Main Channel */
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cx25840_write4(client, 0x8d0, 0x1f063870);
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}
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}
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set_audclk_freq(client, state->audclk_freq);
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if (!is_cx2583x(state)) {
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if (state->aud_input != CX25840_AUDIO_SERIAL) {
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/* When the microcontroller detects the
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* audio format, it will unmute the lines */
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cx25840_and_or(client, 0x803, ~0x10, 0x10);
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}
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/* deassert soft reset */
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cx25840_and_or(client, 0x810, ~0x1, 0x00);
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/* Ensure the controller is running when we exit */
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if (is_cx2388x(state) || is_cx231xx(state))
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cx25840_and_or(client, 0x803, ~0x10, 0x10);
|
|
}
|
|
}
|
|
|
|
static void set_volume(struct i2c_client *client, int volume)
|
|
{
|
|
int vol;
|
|
|
|
/* Convert the volume to msp3400 values (0-127) */
|
|
vol = volume >> 9;
|
|
|
|
/* now scale it up to cx25840 values
|
|
* -114dB to -96dB maps to 0
|
|
* this should be 19, but in my testing that was 4dB too loud */
|
|
if (vol <= 23) {
|
|
vol = 0;
|
|
} else {
|
|
vol -= 23;
|
|
}
|
|
|
|
/* PATH1_VOLUME */
|
|
cx25840_write(client, 0x8d4, 228 - (vol * 2));
|
|
}
|
|
|
|
static void set_balance(struct i2c_client *client, int balance)
|
|
{
|
|
int bal = balance >> 8;
|
|
if (bal > 0x80) {
|
|
/* PATH1_BAL_LEFT */
|
|
cx25840_and_or(client, 0x8d5, 0x7f, 0x80);
|
|
/* PATH1_BAL_LEVEL */
|
|
cx25840_and_or(client, 0x8d5, ~0x7f, bal & 0x7f);
|
|
} else {
|
|
/* PATH1_BAL_LEFT */
|
|
cx25840_and_or(client, 0x8d5, 0x7f, 0x00);
|
|
/* PATH1_BAL_LEVEL */
|
|
cx25840_and_or(client, 0x8d5, ~0x7f, 0x80 - bal);
|
|
}
|
|
}
|
|
|
|
int cx25840_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
|
|
{
|
|
struct i2c_client *client = v4l2_get_subdevdata(sd);
|
|
struct cx25840_state *state = to_state(sd);
|
|
int retval;
|
|
|
|
if (!is_cx2583x(state))
|
|
cx25840_and_or(client, 0x810, ~0x1, 1);
|
|
if (state->aud_input != CX25840_AUDIO_SERIAL) {
|
|
cx25840_and_or(client, 0x803, ~0x10, 0);
|
|
cx25840_write(client, 0x8d3, 0x1f);
|
|
}
|
|
retval = set_audclk_freq(client, freq);
|
|
if (state->aud_input != CX25840_AUDIO_SERIAL)
|
|
cx25840_and_or(client, 0x803, ~0x10, 0x10);
|
|
if (!is_cx2583x(state))
|
|
cx25840_and_or(client, 0x810, ~0x1, 0);
|
|
return retval;
|
|
}
|
|
|
|
static int cx25840_audio_s_ctrl(struct v4l2_ctrl *ctrl)
|
|
{
|
|
struct v4l2_subdev *sd = to_sd(ctrl);
|
|
struct cx25840_state *state = to_state(sd);
|
|
struct i2c_client *client = v4l2_get_subdevdata(sd);
|
|
|
|
switch (ctrl->id) {
|
|
case V4L2_CID_AUDIO_VOLUME:
|
|
if (state->mute->val)
|
|
set_volume(client, 0);
|
|
else
|
|
set_volume(client, state->volume->val);
|
|
break;
|
|
case V4L2_CID_AUDIO_BASS:
|
|
/* PATH1_EQ_BASS_VOL */
|
|
cx25840_and_or(client, 0x8d9, ~0x3f,
|
|
48 - (ctrl->val * 48 / 0xffff));
|
|
break;
|
|
case V4L2_CID_AUDIO_TREBLE:
|
|
/* PATH1_EQ_TREBLE_VOL */
|
|
cx25840_and_or(client, 0x8db, ~0x3f,
|
|
48 - (ctrl->val * 48 / 0xffff));
|
|
break;
|
|
case V4L2_CID_AUDIO_BALANCE:
|
|
set_balance(client, ctrl->val);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
const struct v4l2_ctrl_ops cx25840_audio_ctrl_ops = {
|
|
.s_ctrl = cx25840_audio_s_ctrl,
|
|
};
|