Bring a range of PCIe fixes across the X Elite platform, as well as
marking the NVMe power supply boot-on to avoid glitching the power
supply during boot.
The X Elite CRD audio configuration sees a spelling mistake corrected.
On SM8450 the PCIe 1 PIPE clock definition is corrected, to fix a
regression where this isn't able to acquire it's clocks.
-----BEGIN PGP SIGNATURE-----
iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmck5h0VHGFuZGVyc3Nv
bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FdUQQANXyPoA6x2C0JBQIHI9Kwl0XkvGM
0PoEXHc4szGhmBLdiUyvSyc8TNcTNRszjXDY8eEudvRos/jZgmlLqLMyO0F0VmH7
BfNREqecVU8NbsZ3Hm8DuuZZhmxp9DSDheXyc3KgI443RiVEB5BOXuLOW7uRlTlB
bDZMRd+wqdupB1Yo5oq/wUDIstX1B9+T5zsRfd550nXIRYF0Wc2jLb3TGLXYItGB
lnms3lbJtpp8lLBlbFJRPDy+oqH0FlR9CiMFh3gdFrhSrmNEjvEMqbvH4PqliWxw
ddNlF8p2I0630QM+7Hzwz8SX0AQx2vceAENxAhIfCgLq/cMc8eL7YDSjys09fT7e
VZcLUnItne30YkPIhBxxhHtgRWiFkAutCl08b4QSoTohY9p+EJD9F4hKlxJ/0jKH
SYUCW99MSP4qy4VXiblCBjEkwz5v6NXXev/2imkwqJe9uPMEjeydi5SyzGeFkjWM
81LRkF/nn3B48UR/6VYeNuiToTg1Qin1wmZzefkP+tzOwREh1/afWZbWgQOktD3u
tWJUlWVCU5SQF88xkIMw4CV3qwcQUDbMn1YsbtDBQlKfIykOa7NOFEGELlk3lyyR
5yoXXHNfDDQBm/OYFvG6ly3/dBBpHqzleb89F8cG5lOiEkvqIxslaAQOszsb3W3G
SdugxcKod39acvZR
=gD69
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmck734ACgkQYKtH/8kJ
UiejvA//edyTKEHQyY0rfTnQ8/aD2/l1DL2gTKPFIEB70i2UPdcxPBaWa74JBJVK
7C5zq5H4NpdW1J5NCcbZpmQZYfGnQ9ZtcaJt07fC/sdMl6lFwCiKVfAAPnwQwep1
QCrfbzEI1x44mYzZ+n4yrZXlL5k7stSuQ30ZdXuzVg5DquADSQsRgSkg88Xs923+
3laEX2J9iX5YbcqqgZ+wDhj/US6IPHBUasfHZjdsciUKMwH3yMiyfRLmB/sHxG/0
QTah4UUBVyonT3L43ECD/z1ElxFjHS6h/RKJmF8zHgIyxCbbabIYKGH0CR3LGUfZ
tm+DursZYILoJ7ccYYcKzJgybruqCweKwD13W6OaztluxMVyveSD2b+xU6aR+xYU
xQQQpwbMi4w9y9CDdjEBjQkTXVYH6RHPuYwsqu7rRsHcezmH8SITgWJi9/Y/6xA/
WTq3X6sOzJZwUhAo3I7usLjX7zLZkOkbHieBPti1M1V21EQrxFUxSEI1pMkAP42o
xiZ4jBHBCyGACsAbzXo1QxpdgfuPc9UYa5tlZ4Rajc7SFHQZUSvDBbVpcnp/rLh3
Bl74GN5SzVLb8sPrrLiFYTf9mzubURO3nNAikZ0TIsp3b4czZJ+o8NZLrkwID2iZ
Bfuq0vBd1rJdd1ChfGPfFtlR6aJrDFH9N3Ak/03v16LRsf1zc5A=
=1j8j
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-fixes-for-6.12-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into HEAD
More Qualcomm Arm64 DeviceTree fixes for v6.12
Bring a range of PCIe fixes across the X Elite platform, as well as
marking the NVMe power supply boot-on to avoid glitching the power
supply during boot.
The X Elite CRD audio configuration sees a spelling mistake corrected.
On SM8450 the PCIe 1 PIPE clock definition is corrected, to fix a
regression where this isn't able to acquire it's clocks.
* tag 'qcom-arm64-fixes-for-6.12-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
arm64: dts: qcom: x1e80100: fix PCIe5 interconnect
arm64: dts: qcom: x1e80100: fix PCIe4 interconnect
arm64: dts: qcom: x1e80100: Fix up BAR spaces
arm64: dts: qcom: x1e80100-qcp: fix nvme regulator boot glitch
arm64: dts: qcom: x1e80100-microsoft-romulus: fix nvme regulator boot glitch
arm64: dts: qcom: x1e80100-yoga-slim7x: fix nvme regulator boot glitch
arm64: dts: qcom: x1e80100-vivobook-s15: fix nvme regulator boot glitch
arm64: dts: qcom: x1e80100-crd: fix nvme regulator boot glitch
arm64: dts: qcom: x1e78100-t14s: fix nvme regulator boot glitch
arm64: dts: qcom: x1e80100-crd Rename "Twitter" to "Tweeter"
arm64: dts: qcom: x1e80100: Fix PCIe 6a lanes description
arm64: dts: qcom: sm8450 fix PIPE clock specification for pcie1
arm64: dts: qcom: x1e80100: Add Broadcast_AND region in LLCC block
arm64: dts: qcom: x1e80100: fix PCIe5 PHY clocks
arm64: dts: qcom: x1e80100: fix PCIe4 and PCIe6a PHY clocks
Link: https://lore.kernel.org/r/20241101143206.738617-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
566064e570