36 lines
1.1 KiB
Plaintext
36 lines
1.1 KiB
Plaintext
|
These bindings should be considered EXPERIMENTAL for now.
|
||
|
|
|
||
|
|
* Renesas SH73A0 Clock Pulse Generator (CPG)
|
||
|
|
|
||
|
|
The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs
|
||
|
|
and several fixed ratio dividers.
|
||
|
|
|
||
|
|
Required Properties:
|
||
|
|
|
||
|
|
- compatible: Must be "renesas,sh73a0-cpg-clocks"
|
||
|
|
|
||
|
|
- reg: Base address and length of the memory resource used by the CPG
|
||
|
|
|
||
|
|
- clocks: Reference to the parent clocks ("extal1" and "extal2")
|
||
|
|
|
||
|
|
- #clock-cells: Must be 1
|
||
|
|
|
||
|
|
- clock-output-names: The names of the clocks. Supported clocks are "main",
|
||
|
|
"pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
|
||
|
|
"m1", "m2", "z", "zx", and "hp".
|
||
|
|
|
||
|
|
|
||
|
|
Example
|
||
|
|
-------
|
||
|
|
|
||
|
|
cpg_clocks: cpg_clocks@e6150000 {
|
||
|
|
compatible = "renesas,sh73a0-cpg-clocks";
|
||
|
|
reg = <0 0xe6150000 0 0x10000>;
|
||
|
|
clocks = <&extal1_clk>, <&extal2_clk>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
clock-output-names = "main", "pll0", "pll1", "pll2",
|
||
|
|
"pll3", "dsi0phy", "dsi1phy",
|
||
|
|
"zg", "m3", "b", "m1", "m2",
|
||
|
|
"z", "zx", "hp";
|
||
|
|
};
|