36 lines
1.1 KiB
Plaintext
36 lines
1.1 KiB
Plaintext
These bindings should be considered EXPERIMENTAL for now.
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* Renesas SH73A0 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs
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and several fixed ratio dividers.
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Required Properties:
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- compatible: Must be "renesas,sh73a0-cpg-clocks"
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: Reference to the parent clocks ("extal1" and "extal2")
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "main",
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"pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
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"m1", "m2", "z", "zx", and "hp".
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Example
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-------
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,sh73a0-cpg-clocks";
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reg = <0 0xe6150000 0 0x10000>;
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clocks = <&extal1_clk>, <&extal2_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0", "pll1", "pll2",
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"pll3", "dsi0phy", "dsi1phy",
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"zg", "m3", "b", "m1", "m2",
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"z", "zx", "hp";
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};
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