48 lines
1.3 KiB
C
48 lines
1.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _DT_BINDINGS_MMC_MT6739_H
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#define _DT_BINDINGS_MMC_MT6739_H
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#define MSDC_EMMC (0)
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#define MSDC_SD (1)
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#define MSDC_SDIO (2)
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#define MSDC_CD_HIGH (1)
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#define MSDC_CD_LOW (0)
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#define MSDC0_CLKSRC_26MHZ (0)
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#define MSDC0_CLKSRC_400MHZ (1)
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#define MSDC0_CLKSRC_800MHZ (2)
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#define MSDC0_CLKSRC_156MHZ (3)
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#define MSDC0_CLKSRC_182MHZ (4)
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#define MSDC0_CLKSRC_364MHZ (5)
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#define MSDC0_CLKSRC_200MHZ (6)
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#define MSDC0_CLKSRC_312MHZ (7)
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#define MSDC1_CLKSRC_26MHZ (0)
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#define MSDC1_CLKSRC_208MHZ (1)
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#define MSDC1_CLKSRC_200MHZ (2)
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#define MSDC1_CLKSRC_156MHZ (3)
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#define MSDC1_CLKSRC_182MHZ (4)
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/* #define MSDC1_CLKSRC_156MHZ (5) */
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#define MSDC1_CLKSRC_178MHZ (6)
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#define MSDC1_CLKSRC_400MHZ (7)
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#define MSDC3_CLKSRC_26MHZ (0)
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#define MSDC3_CLKSRC_208MHZ (1)
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#define MSDC3_CLKSRC_400MHZ (2)
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#define MSDC3_CLKSRC_156MHZ (3)
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#define MSDC3_CLKSRC_182MHZ (4)
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#define MSDC3_CLKSRC_312MHZ (5)
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#define MSDC3_CLKSRC_364MHZ (6)
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#define MSDC3_CLKSRC_200MHZ (7)
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#define MSDC_SMPL_RISING (0)
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#define MSDC_SMPL_FALLING (1)
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#define MSDC_SMPL_SEPARATE (2)
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#endif /* _DT_BINDINGS_MMC_MT6739_H */
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