298 lines
11 KiB
C
298 lines
11 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 MediaTek Inc.
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*/
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struct nvt_ts_mem_map {
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uint32_t EVENT_BUF_ADDR;
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uint32_t RAW_PIPE0_ADDR;
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uint32_t RAW_PIPE1_ADDR;
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uint32_t BASELINE_ADDR;
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uint32_t BASELINE_BTN_ADDR;
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uint32_t DIFF_PIPE0_ADDR;
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uint32_t DIFF_PIPE1_ADDR;
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uint32_t RAW_BTN_PIPE0_ADDR;
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uint32_t RAW_BTN_PIPE1_ADDR;
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uint32_t DIFF_BTN_PIPE0_ADDR;
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uint32_t DIFF_BTN_PIPE1_ADDR;
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uint32_t READ_FLASH_CHECKSUM_ADDR;
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uint32_t RW_FLASH_DATA_ADDR;
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/* Phase 2 Host Download */
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uint32_t BOOT_RDY_ADDR;
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uint32_t POR_CD_ADDR;
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/* BLD CRC */
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uint32_t BLD_LENGTH_ADDR;
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uint32_t ILM_LENGTH_ADDR;
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uint32_t DLM_LENGTH_ADDR;
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uint32_t BLD_DES_ADDR;
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uint32_t ILM_DES_ADDR;
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uint32_t DLM_DES_ADDR;
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uint32_t G_ILM_CHECKSUM_ADDR;
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uint32_t G_DLM_CHECKSUM_ADDR;
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uint32_t R_ILM_CHECKSUM_ADDR;
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uint32_t R_DLM_CHECKSUM_ADDR;
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uint32_t BLD_CRC_EN_ADDR;
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uint32_t DMA_CRC_EN_ADDR;
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uint32_t BLD_ILM_DLM_CRC_ADDR;
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uint32_t DMA_CRC_FLAG_ADDR;
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};
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struct nvt_ts_hw_info {
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uint8_t carrier_system;
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uint8_t hw_crc;
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};
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static const struct nvt_ts_mem_map NT36526_memory_map = {
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.EVENT_BUF_ADDR = 0x22D00,
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.RAW_PIPE0_ADDR = 0x24000,
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.RAW_PIPE1_ADDR = 0x24000,
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.BASELINE_ADDR = 0x21758,
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.BASELINE_BTN_ADDR = 0,
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.DIFF_PIPE0_ADDR = 0x20AB0,
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.DIFF_PIPE1_ADDR = 0x24AB0,
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.RAW_BTN_PIPE0_ADDR = 0,
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.RAW_BTN_PIPE1_ADDR = 0,
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.DIFF_BTN_PIPE0_ADDR = 0,
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.DIFF_BTN_PIPE1_ADDR = 0,
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.READ_FLASH_CHECKSUM_ADDR = 0x24000,
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.RW_FLASH_DATA_ADDR = 0x24002,
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/* Phase 2 Host Download */
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.BOOT_RDY_ADDR = 0x3F10D,
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/* BLD CRC */
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.BLD_LENGTH_ADDR = 0x3F138, //0x3F138 ~ 0x3F13A (3 bytes)
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.ILM_LENGTH_ADDR = 0x3F118, //0x3F118 ~ 0x3F11A (3 bytes)
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.DLM_LENGTH_ADDR = 0x3F130, //0x3F130 ~ 0x3F132 (3 bytes)
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.BLD_DES_ADDR = 0x3F114, //0x3F114 ~ 0x3F116 (3 bytes)
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.ILM_DES_ADDR = 0x3F128, //0x3F128 ~ 0x3F12A (3 bytes)
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.DLM_DES_ADDR = 0x3F12C, //0x3F12C ~ 0x3F12E (3 bytes)
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.G_ILM_CHECKSUM_ADDR = 0x3F100, //0x3F100 ~ 0x3F103 (4 bytes)
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.G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes)
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.R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes)
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.R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes)
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.BLD_CRC_EN_ADDR = 0x3F30E,
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.DMA_CRC_EN_ADDR = 0x3F136,
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.BLD_ILM_DLM_CRC_ADDR = 0x3F133,
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.DMA_CRC_FLAG_ADDR = 0x3F134,
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};
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static const struct nvt_ts_mem_map NT36675_memory_map = {
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.EVENT_BUF_ADDR = 0x22D00,
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.RAW_PIPE0_ADDR = 0x24000,
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.RAW_PIPE1_ADDR = 0x24000,
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.BASELINE_ADDR = 0x21B90,
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.BASELINE_BTN_ADDR = 0,
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.DIFF_PIPE0_ADDR = 0x20C60,
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.DIFF_PIPE1_ADDR = 0x24C60,
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.RAW_BTN_PIPE0_ADDR = 0,
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.RAW_BTN_PIPE1_ADDR = 0,
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.DIFF_BTN_PIPE0_ADDR = 0,
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.DIFF_BTN_PIPE1_ADDR = 0,
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.READ_FLASH_CHECKSUM_ADDR = 0x24000,
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.RW_FLASH_DATA_ADDR = 0x24002,
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/* Phase 2 Host Download */
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.BOOT_RDY_ADDR = 0x3F10D,
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/* BLD CRC */
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.BLD_LENGTH_ADDR = 0x3F138, //0x3F138 ~ 0x3F13A (3 bytes)
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.ILM_LENGTH_ADDR = 0x3F118, //0x3F118 ~ 0x3F11A (3 bytes)
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.DLM_LENGTH_ADDR = 0x3F130, //0x3F130 ~ 0x3F132 (3 bytes)
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.BLD_DES_ADDR = 0x3F114, //0x3F114 ~ 0x3F116 (3 bytes)
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.ILM_DES_ADDR = 0x3F128, //0x3F128 ~ 0x3F12A (3 bytes)
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.DLM_DES_ADDR = 0x3F12C, //0x3F12C ~ 0x3F12E (3 bytes)
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.G_ILM_CHECKSUM_ADDR = 0x3F100, //0x3F100 ~ 0x3F103 (4 bytes)
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.G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes)
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.R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes)
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.R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes)
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.BLD_CRC_EN_ADDR = 0x3F30E,
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.DMA_CRC_EN_ADDR = 0x3F136,
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.BLD_ILM_DLM_CRC_ADDR = 0x3F133,
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.DMA_CRC_FLAG_ADDR = 0x3F134,
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};
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static const struct nvt_ts_mem_map NT36672A_memory_map = {
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.EVENT_BUF_ADDR = 0x21C00,
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.RAW_PIPE0_ADDR = 0x20000,
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.RAW_PIPE1_ADDR = 0x23000,
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.BASELINE_ADDR = 0x20BFC,
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.BASELINE_BTN_ADDR = 0x23BFC,
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.DIFF_PIPE0_ADDR = 0x206DC,
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.DIFF_PIPE1_ADDR = 0x236DC,
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.RAW_BTN_PIPE0_ADDR = 0x20510,
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.RAW_BTN_PIPE1_ADDR = 0x23510,
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.DIFF_BTN_PIPE0_ADDR = 0x20BF0,
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.DIFF_BTN_PIPE1_ADDR = 0x23BF0,
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.READ_FLASH_CHECKSUM_ADDR = 0x24000,
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.RW_FLASH_DATA_ADDR = 0x24002,
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/* Phase 2 Host Download */
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.BOOT_RDY_ADDR = 0x3F10D,
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/* BLD CRC */
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.BLD_LENGTH_ADDR = 0x3F10E, //0x3F10E ~ 0x3F10F (2 bytes)
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.ILM_LENGTH_ADDR = 0x3F118, //0x3F118 ~ 0x3F119 (2 bytes)
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.DLM_LENGTH_ADDR = 0x3F130, //0x3F130 ~ 0x3F131 (2 bytes)
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.BLD_DES_ADDR = 0x3F114, //0x3F114 ~ 0x3F116 (3 bytes)
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.ILM_DES_ADDR = 0x3F128, //0x3F128 ~ 0x3F12A (3 bytes)
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.DLM_DES_ADDR = 0x3F12C, //0x3F12C ~ 0x3F12E (3 bytes)
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.G_ILM_CHECKSUM_ADDR = 0x3F100, //0x3F100 ~ 0x3F103 (4 bytes)
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.G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes)
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.R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes)
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.R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes)
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.BLD_CRC_EN_ADDR = 0x3F30E,
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.DMA_CRC_EN_ADDR = 0x3F132,
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.BLD_ILM_DLM_CRC_ADDR = 0x3F133,
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.DMA_CRC_FLAG_ADDR = 0x3F134,
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};
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static const struct nvt_ts_mem_map NT36772_memory_map = {
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.EVENT_BUF_ADDR = 0x11E00,
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.RAW_PIPE0_ADDR = 0x10000,
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.RAW_PIPE1_ADDR = 0x12000,
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.BASELINE_ADDR = 0x10E70,
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.BASELINE_BTN_ADDR = 0x12E70,
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.DIFF_PIPE0_ADDR = 0x10830,
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.DIFF_PIPE1_ADDR = 0x12830,
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.RAW_BTN_PIPE0_ADDR = 0x10E60,
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.RAW_BTN_PIPE1_ADDR = 0x12E60,
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.DIFF_BTN_PIPE0_ADDR = 0x10E68,
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.DIFF_BTN_PIPE1_ADDR = 0x12E68,
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.READ_FLASH_CHECKSUM_ADDR = 0x14000,
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.RW_FLASH_DATA_ADDR = 0x14002,
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/* Phase 2 Host Download */
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.BOOT_RDY_ADDR = 0x1F141,
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.POR_CD_ADDR = 0x1F61C,
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/* BLD CRC */
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.R_ILM_CHECKSUM_ADDR = 0x1BF00,
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};
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static const struct nvt_ts_mem_map NT36525_memory_map = {
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.EVENT_BUF_ADDR = 0x11A00,
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.RAW_PIPE0_ADDR = 0x10000,
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.RAW_PIPE1_ADDR = 0x12000,
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.BASELINE_ADDR = 0x10B08,
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.BASELINE_BTN_ADDR = 0x12B08,
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.DIFF_PIPE0_ADDR = 0x1064C,
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.DIFF_PIPE1_ADDR = 0x1264C,
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.RAW_BTN_PIPE0_ADDR = 0x10634,
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.RAW_BTN_PIPE1_ADDR = 0x12634,
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.DIFF_BTN_PIPE0_ADDR = 0x10AFC,
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.DIFF_BTN_PIPE1_ADDR = 0x12AFC,
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.READ_FLASH_CHECKSUM_ADDR = 0x14000,
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.RW_FLASH_DATA_ADDR = 0x14002,
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/* Phase 2 Host Download */
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.BOOT_RDY_ADDR = 0x1F141,
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.POR_CD_ADDR = 0x1F61C,
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/* BLD CRC */
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.R_ILM_CHECKSUM_ADDR = 0x1BF00,
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};
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static const struct nvt_ts_mem_map NT36676F_memory_map = {
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.EVENT_BUF_ADDR = 0x11A00,
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.RAW_PIPE0_ADDR = 0x10000,
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.RAW_PIPE1_ADDR = 0x12000,
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.BASELINE_ADDR = 0x10B08,
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.BASELINE_BTN_ADDR = 0x12B08,
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.DIFF_PIPE0_ADDR = 0x1064C,
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.DIFF_PIPE1_ADDR = 0x1264C,
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.RAW_BTN_PIPE0_ADDR = 0x10634,
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.RAW_BTN_PIPE1_ADDR = 0x12634,
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.DIFF_BTN_PIPE0_ADDR = 0x10AFC,
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.DIFF_BTN_PIPE1_ADDR = 0x12AFC,
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.READ_FLASH_CHECKSUM_ADDR = 0x14000,
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.RW_FLASH_DATA_ADDR = 0x14002,
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};
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static struct nvt_ts_hw_info NT36526_hw_info = {
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.carrier_system = 2,
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.hw_crc = 2,
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};
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static struct nvt_ts_hw_info NT36675_hw_info = {
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.carrier_system = 2,
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.hw_crc = 2,
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};
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static struct nvt_ts_hw_info NT36672A_hw_info = {
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.carrier_system = 0,
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.hw_crc = 1,
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};
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static struct nvt_ts_hw_info NT36772_hw_info = {
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.carrier_system = 0,
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.hw_crc = 0,
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};
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static struct nvt_ts_hw_info NT36525_hw_info = {
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.carrier_system = 0,
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.hw_crc = 0,
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};
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static struct nvt_ts_hw_info NT36676F_hw_info = {
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.carrier_system = 0,
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.hw_crc = 0,
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};
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#define NVT_ID_BYTE_MAX 6
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struct nvt_ts_trim_id_table {
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uint8_t id[NVT_ID_BYTE_MAX];
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uint8_t mask[NVT_ID_BYTE_MAX];
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const struct nvt_ts_mem_map *mmap;
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const struct nvt_ts_hw_info *hwinfo;
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};
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static const struct nvt_ts_trim_id_table trim_id_table[] = {
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{.id = {0x0D, 0xFF, 0xFF, 0x72, 0x66, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
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.mmap = &NT36675_memory_map, .hwinfo = &NT36675_hw_info},
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{.id = {0x20, 0xFF, 0xFF, 0x72, 0x66, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
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.mmap = &NT36675_memory_map, .hwinfo = &NT36675_hw_info},
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{.id = {0x00, 0xFF, 0xFF, 0x80, 0x66, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
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.mmap = &NT36675_memory_map, .hwinfo = &NT36675_hw_info},
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{.id = {0x0C, 0xFF, 0xFF, 0x25, 0x65, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
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.mmap = &NT36672A_memory_map, .hwinfo = &NT36672A_hw_info},
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{.id = {0x0E, 0xFF, 0xFF, 0x72, 0x66, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
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.mmap = &NT36675_memory_map, .hwinfo = &NT36675_hw_info},
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{.id = {0x0C, 0xFF, 0xFF, 0x72, 0x66, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
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.mmap = &NT36675_memory_map, .hwinfo = &NT36675_hw_info},
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{.id = {0xFF, 0xFF, 0xFF, 0x26, 0x65, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
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.mmap = &NT36526_memory_map, .hwinfo = &NT36526_hw_info},
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{.id = {0xFF, 0xFF, 0xFF, 0x75, 0x66, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
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.mmap = &NT36675_memory_map, .hwinfo = &NT36675_hw_info},
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{.id = {0x0B, 0xFF, 0xFF, 0x72, 0x66, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
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.mmap = &NT36672A_memory_map, .hwinfo = &NT36672A_hw_info},
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{.id = {0x0B, 0xFF, 0xFF, 0x82, 0x66, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
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.mmap = &NT36672A_memory_map, .hwinfo = &NT36672A_hw_info},
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{.id = {0x0B, 0xFF, 0xFF, 0x25, 0x65, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
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.mmap = &NT36672A_memory_map, .hwinfo = &NT36672A_hw_info},
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{.id = {0x0A, 0xFF, 0xFF, 0x72, 0x65, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
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.mmap = &NT36672A_memory_map, .hwinfo = &NT36672A_hw_info},
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{.id = {0x0A, 0xFF, 0xFF, 0x72, 0x66, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
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.mmap = &NT36672A_memory_map, .hwinfo = &NT36672A_hw_info},
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{.id = {0x0A, 0xFF, 0xFF, 0x82, 0x66, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
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.mmap = &NT36672A_memory_map, .hwinfo = &NT36672A_hw_info},
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{.id = {0x0A, 0xFF, 0xFF, 0x70, 0x66, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
|
||
|
|
.mmap = &NT36672A_memory_map, .hwinfo = &NT36672A_hw_info},
|
||
|
|
{.id = {0x0B, 0xFF, 0xFF, 0x70, 0x66, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
|
||
|
|
.mmap = &NT36672A_memory_map, .hwinfo = &NT36672A_hw_info},
|
||
|
|
{.id = {0x0A, 0xFF, 0xFF, 0x72, 0x67, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
|
||
|
|
.mmap = &NT36672A_memory_map, .hwinfo = &NT36672A_hw_info},
|
||
|
|
{.id = {0x55, 0x00, 0xFF, 0x00, 0x00, 0x00}, .mask = {1, 1, 0, 1, 1, 1},
|
||
|
|
.mmap = &NT36772_memory_map, .hwinfo = &NT36772_hw_info},
|
||
|
|
{.id = {0x55, 0x72, 0xFF, 0x00, 0x00, 0x00}, .mask = {1, 1, 0, 1, 1, 1},
|
||
|
|
.mmap = &NT36772_memory_map, .hwinfo = &NT36772_hw_info},
|
||
|
|
{.id = {0xAA, 0x00, 0xFF, 0x00, 0x00, 0x00}, .mask = {1, 1, 0, 1, 1, 1},
|
||
|
|
.mmap = &NT36772_memory_map, .hwinfo = &NT36772_hw_info},
|
||
|
|
{.id = {0xAA, 0x72, 0xFF, 0x00, 0x00, 0x00}, .mask = {1, 1, 0, 1, 1, 1},
|
||
|
|
.mmap = &NT36772_memory_map, .hwinfo = &NT36772_hw_info},
|
||
|
|
{.id = {0xFF, 0xFF, 0xFF, 0x72, 0x67, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
|
||
|
|
.mmap = &NT36772_memory_map, .hwinfo = &NT36772_hw_info},
|
||
|
|
{.id = {0xFF, 0xFF, 0xFF, 0x70, 0x66, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
|
||
|
|
.mmap = &NT36772_memory_map, .hwinfo = &NT36772_hw_info},
|
||
|
|
{.id = {0xFF, 0xFF, 0xFF, 0x70, 0x67, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
|
||
|
|
.mmap = &NT36772_memory_map, .hwinfo = &NT36772_hw_info},
|
||
|
|
{.id = {0xFF, 0xFF, 0xFF, 0x72, 0x66, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
|
||
|
|
.mmap = &NT36772_memory_map, .hwinfo = &NT36772_hw_info},
|
||
|
|
{.id = {0xFF, 0xFF, 0xFF, 0x25, 0x65, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
|
||
|
|
.mmap = &NT36525_memory_map, .hwinfo = &NT36525_hw_info},
|
||
|
|
{.id = {0xFF, 0xFF, 0xFF, 0x76, 0x66, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
|
||
|
|
.mmap = &NT36676F_memory_map, .hwinfo = &NT36676F_hw_info}
|
||
|
|
};
|