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drivers: mediatek: connectivity: import Samsung customizations

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BWK2 OSS package
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Fede2782 2024-04-27 23:17:48 +02:00
parent 691010b228
commit c3592be768
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490 changed files with 98254 additions and 227707 deletions
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11
drivers/misc/mediatek/connectivity/bt/mt66xx/btif/Makefile
View file

@ -31,8 +31,10 @@ endif
$(info $(LOG_TAG) TARGET_BUILD_VARIANT = $(TARGET_BUILD_VARIANT))
ifeq ("$(TARGET_BUILD_VARIANT)","user")
ccflags-y += -D FW_LOG_DEFAULT_ON=0
ccflags-y += -D BUILD_QA_DBG=0
else
ccflags-y += -D FW_LOG_DEFAULT_ON=1
ccflags-y += -D BUILD_QA_DBG=1
endif
@ -51,14 +53,7 @@ ccflags-y += -D CHIP_IF_BTIF
ccflags-y += -D USE_DEVICE_NODE=1
# Customized fw update feature
#ifndef OPLUS_FEATURE_BT_FW_SAU_MTK
#Add for fw sau
#ccflags-y += -D CUSTOMER_FW_UPDATE=0
#else /* OPLUS_FEATURE_BT_FW_SAU_MTK */
ccflags-y += -D CUSTOMER_FW_UPDATE=1
ccflags-y += -D OPLUS_FEATURE_BT_FW_SAU_MTK=1
#endif /* OPLUS_FEATURE_BT_FW_SAU_MTK */
ccflags-y += -D CUSTOMER_FW_UPDATE=0
# pm_qos control
ccflags-y += -D PM_QOS_CONTROL=0

339
drivers/misc/mediatek/connectivity/bt/mt66xx/btif/NOTICE Normal file
View file

@ -0,0 +1,339 @@
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies
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consider it more useful to permit linking proprietary applications with the
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Public License instead of this License.

72
drivers/misc/mediatek/connectivity/bt/mt66xx/btif/btmtk_btif_main.c
View file

@ -54,7 +54,6 @@
*/
uint8_t *p_conn_infra_base_addr;
uint8_t *p_bgfsys_base_addr;
extern bool g_bt_trace_pt;
extern struct btmtk_dev *g_sbdev;
static unsigned long g_btif_id; /* The user identifier to operate btif */
@ -187,7 +186,7 @@ int btmtk_disp_notify_cb(struct notifier_block *nb, unsigned long value, void *v
}
}
end:
BTMTK_DBG("%s: end", __func__);
BTMTK_INFO("%s: end", __func__);
return 0;
}
@ -258,13 +257,11 @@ static int btmtk_pm_notifier_callback(struct notifier_block *nb,
{
struct btmtk_btif_dev *cif_dev = (struct btmtk_btif_dev *)g_sbdev->cif_dev;
BTMTK_INFO("%s: bt_state[%d], event[%ld]",
__func__, cif_dev->bt_state, event);
switch (event) {
case PM_SUSPEND_PREPARE:
if(cif_dev->bt_state != FUNC_ON) {
BTMTK_INFO("%s: bt_state[%d], event[%ld]",
__func__, cif_dev->bt_state, event);
}
case PM_POST_SUSPEND:
if(cif_dev->bt_state == FUNC_ON) {
bt_dump_bgfsys_suspend_wakeup_debug();
@ -393,8 +390,7 @@ static int32_t btmtk_cif_fw_own_clr(void)
uint32_t lpctl_cr;
int32_t retry = LPCR_POLLING_RTY_LMT;
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_DRVOWN_IN, 0, 0, NULL);
bt_dbg_tp_evt(TP_ACT_DRVOWN_IN, 0, 0, NULL);
do {
/* assume wait interval 0.5ms each time,
* wait maximum total 7ms to query status
@ -423,8 +419,7 @@ static int32_t btmtk_cif_fw_own_clr(void)
if (retry == 0) {
BTMTK_ERR("[DRV_OWN] (Wakeup) failed!");
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_DRVOWN_OUT, TP_PAR_FAIL, 0, NULL);
bt_dbg_tp_evt(TP_ACT_DRVOWN_OUT, TP_PAR_FAIL, 0, NULL);
bt_dump_cif_own_cr();
/* dump cpupcr, 10 times with 1ms interval */
@ -432,8 +427,7 @@ static int32_t btmtk_cif_fw_own_clr(void)
return -1;
}
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_DRVOWN_OUT, TP_PAR_PASS, 0, NULL);
bt_dbg_tp_evt(TP_ACT_DRVOWN_OUT, TP_PAR_PASS, 0, NULL);
BTMTK_DBG("[DRV_OWN] (Wakeup) success, retry[%d]", retry);
return 0;
}
@ -454,8 +448,7 @@ static int32_t btmtk_cif_fw_own_set(void)
uint32_t irqstat_cr;
int32_t retry = LPCR_POLLING_RTY_LMT;
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_FWOWN_IN, 0, 0, NULL);
bt_dbg_tp_evt(TP_ACT_FWOWN_IN, 0, 0, NULL);
do {
if ((retry & 0xF) == 0) { /* retry % 16 == 0 */
if (((retry < LPCR_POLLING_RTY_LMT && retry >= LPCR_MASS_DUMP_LMT) || (retry == 2048) || (retry == 32)) &&
@ -491,8 +484,7 @@ static int32_t btmtk_cif_fw_own_set(void)
if (retry == 0) {
BTMTK_ERR("[FW_OWN] (Sleep) failed!");
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_FWOWN_OUT, TP_PAR_FAIL, 0, NULL);
bt_dbg_tp_evt(TP_ACT_FWOWN_OUT, TP_PAR_FAIL, 0, NULL);
bt_dump_cif_own_cr();
/* dump cpupcr, 10 times with 1ms interval */
@ -500,8 +492,7 @@ static int32_t btmtk_cif_fw_own_set(void)
return -1;
}
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_FWOWN_OUT, TP_PAR_PASS, 0, NULL);
bt_dbg_tp_evt(TP_ACT_FWOWN_OUT, TP_PAR_PASS, 0, NULL);
BTMTK_DBG("[FW_OWN] (Sleep) success, retry[%d]", retry);
return 0;
}
@ -546,8 +537,7 @@ int bt_chip_reset_flow(enum bt_reset_level rst_level,
struct btmtk_dev *bdev = hci_get_drvdata(g_sbdev->hdev);
struct btmtk_btif_dev *cif_dev = (struct btmtk_btif_dev *)g_sbdev->cif_dev;
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_RST, TP_PAR_RST_START, 0, NULL);
bt_dbg_tp_evt(TP_ACT_RST, TP_PAR_RST_START, 0, NULL);
/* dump debug message */
show_all_dump_packet();
btmtk_cif_dump_fw_no_rsp(BT_BTIF_DUMP_ALL);
@ -590,8 +580,7 @@ int bt_chip_reset_flow(enum bt_reset_level rst_level,
/* 4. Do coredump, only do this while BT is on */
down(&cif_dev->halt_sem);
if (cif_dev->bt_state != RESET_START && cif_dev->bt_state != FUNC_OFF) {
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_RST, TP_PAR_RST_DUMP, 0, NULL);
bt_dbg_tp_evt(TP_ACT_RST, TP_PAR_RST_DUMP, 0, NULL);
bt_dump_bgfsys_debug_cr();
connsys_coredump_start(cif_dev->coredump_handle, dump_property, drv, reason);
} else
@ -606,7 +595,8 @@ int bt_chip_reset_flow(enum bt_reset_level rst_level,
uint8_t *dump_msg_addr;
uint8_t msg[256] = {0};
conninfra_get_phy_addr(&emi_ap_phy_base, NULL);
conninfra_get_phy_addr((uint32_t*)&emi_ap_phy_base, NULL);
emi_ap_phy_base &= 0xFFFFFFFF;
dump_msg_addr = ioremap(emi_ap_phy_base + 0x3B000, 0x100);
if (dump_msg_addr) {
@ -637,8 +627,7 @@ int bt_chip_reset_flow(enum bt_reset_level rst_level,
bt_notify_state();
/* 5. Turn off BT */
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_RST, TP_PAR_RST_OFF, 0, NULL);
bt_dbg_tp_evt(TP_ACT_RST, TP_PAR_RST_OFF, 0, NULL);
btmtk_fops_set_state(bdev, BTMTK_FOPS_STATE_OPENED); // to comform to the common part state
ret = g_sbdev->hdev->close(g_sbdev->hdev);
#if (USE_DEVICE_NODE == 0)
@ -794,9 +783,7 @@ static int32_t bt_receive_data_cb(uint8_t *buf, uint32_t count)
{
struct btmtk_btif_dev *cif_dev = (struct btmtk_btif_dev *)g_sbdev->cif_dev;
BTMTK_LIMIT("%s: get Rx", __func__);
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_RD_CB, 0, count, buf);
bt_dbg_tp_evt(TP_ACT_RD_CB, 0, count, buf);
BTMTK_DBG_RAW(buf, count, "%s: len[%d] RX: ", __func__, count);
add_dump_packet(buf, count, RX);
cif_dev->psm.sleep_flag = FALSE;
@ -812,7 +799,7 @@ static int32_t bt_receive_data_cb(uint8_t *buf, uint32_t count)
*/
static struct coredump_event_cb bt_coredump_cb =
{
.reg_readable = conninfra_reg_readable_for_coredump,
.reg_readable = conninfra_reg_readable,
.poll_cpupcr = bt_dump_cpupcr,
};
#endif
@ -899,8 +886,7 @@ static void btmtk_btif_enter_deep_idle(struct work_struct *pwork)
bt_release_wake_lock(&cif_dev->psm.wake_lock);
idle_ctrl->is_dpidle = (ret) ? FALSE : TRUE;
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_DPI_ENTER, (ret == 0 ? TP_PAR_PASS : TP_PAR_FAIL), 0, NULL);
bt_dbg_tp_evt(TP_ACT_DPI_ENTER, (ret == 0 ? TP_PAR_PASS : TP_PAR_FAIL), 0, NULL);
if (ret)
BTMTK_ERR("[DP_IDLE] BTIF enter dpidle failed(%d)", ret);
else
@ -945,8 +931,7 @@ static int32_t btmtk_btif_dpidle_ctrl(u_int8_t enable)
ret = mtk_wcn_btif_dpidle_ctrl(g_btif_id, BTIF_DPIDLE_DISABLE);
idle_ctrl->is_dpidle = (ret) ? TRUE : FALSE;
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_DPI_EXIT, (ret == 0 ? TP_PAR_PASS : TP_PAR_FAIL), 0, NULL);
bt_dbg_tp_evt(TP_ACT_DPI_EXIT, (ret == 0 ? TP_PAR_PASS : TP_PAR_FAIL), 0, NULL);
if (ret)
BTMTK_ERR("[DP_IDLE] BTIF exit dpidle failed(%d)", ret);
else
@ -1401,8 +1386,7 @@ int btmtk_btif_send_cmd(struct btmtk_dev *bdev, struct sk_buff *skb, int delay,
cmd += ret;
}
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_WR_OUT, 0, cmd_len, tp_ptr);
bt_dbg_tp_evt(TP_ACT_WR_OUT, 0, cmd_len, tp_ptr);
return ret;
}
@ -1579,9 +1563,7 @@ static int btmtk_cif_probe(struct platform_device *pdev)
/* 8. Register screen on/off & suspend/wakup notify callback */
cif_dev->blank_state = WMT_PARA_SCREEN_ON;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
if (mtk_disp_notifier_register("btmtk_disp_notifier", &btmtk_disp_notifier)) {
BTMTK_ERR("Register mtk_disp_notifier failed\n");
}
mtk_disp_notifier_register("btmtk_disp_notifier", &btmtk_disp_notifier);
#else
btmtk_fb_notify_register();
#endif
@ -1764,16 +1746,14 @@ static u_int8_t bt_tx_wait_for_msg(struct btmtk_dev *bdev)
if (cif_dev->bt_state == RESET_START)
return kthread_should_stop();
else {
BTMTK_DBG("skb [%d], rx_ind [%d], bgf2ap_ind [%d], bt_conn2ap_ind [%d], sleep_flag [%d], wakeup_flag [%d], force_on [%d]",
BTMTK_DBG("skb [%d], rx_ind [%d], bgf2ap_ind [%d], sleep_flag [%d], wakeup_flag [%d], force_on [%d]",
skb_queue_empty(&cif_dev->tx_queue), cif_dev->rx_ind,
cif_dev->bgf2ap_ind, cif_dev->bt_conn2ap_ind,
cif_dev->psm.sleep_flag,
cif_dev->bgf2ap_ind, cif_dev->psm.sleep_flag,
cif_dev->psm.wakeup_flag,
cif_dev->psm.force_on);
return (!skb_queue_empty(&cif_dev->tx_queue)
|| cif_dev->rx_ind
|| cif_dev->bgf2ap_ind
|| cif_dev->bt_conn2ap_ind
|| (!cif_dev->psm.force_on && cif_dev->psm.sleep_flag) // only check sleep_flag if force_on is FALSE
|| cif_dev->psm.wakeup_flag
|| kthread_should_stop());
@ -1814,14 +1794,8 @@ int32_t btmtk_tx_thread(void * arg)
break;
}
/* handling BUS SW IRQ */
if (cif_dev->bt_conn2ap_ind && BT_SSPM_TIMER != 0) {
bt_conn2ap_irq_handler();
continue;
}
/* handling SW IRQ */
if (cif_dev->bgf2ap_ind) {
if(cif_dev->bgf2ap_ind) {
bt_bgf2ap_irq_handler();
/* reset bgf2ap_ind flag move into bt_bgf2ap_irq_handler */
continue;

22
drivers/misc/mediatek/connectivity/bt/mt66xx/btif/btmtk_char_dev.c
View file

@ -28,6 +28,7 @@ MODULE_LICENSE("Dual BSD/GPL");
#define COMBO_IOC_MAGIC 0xb0
#define COMBO_IOCTL_BT_HOST_DEBUG _IOW(COMBO_IOC_MAGIC, 4, void*)
#define COMBO_IOCTL_BT_INTTRX _IOW(COMBO_IOC_MAGIC, 5, void*)
#define COMBO_IOCTL_BT_GET_FW_VERSION _IOR(COMBO_IOC_MAGIC, 6, void*)
#define IOCTL_BT_HOST_DEBUG_BUF_SIZE (32)
#define IOCTL_BT_HOST_INTTRX_SIZE (128)
@ -61,12 +62,14 @@ static struct device *BT_dev;
static uint8_t i_buf[BT_BUFFER_SIZE]; /* Input buffer for read */
static uint8_t o_buf[BT_BUFFER_SIZE]; /* Output buffer for write */
static uint8_t ioc_buf[IOCTL_BT_HOST_INTTRX_SIZE];
static unsigned char bt_dump_buf[BT_BUFFER_SIZE];
extern struct btmtk_dev *g_sbdev;
extern bool g_bt_trace_pt;
extern struct btmtk_btif_dev g_btif_dev;
extern void bthost_debug_init(void);
extern void bthost_debug_save(uint32_t id, uint32_t value, char* desc);
extern int fwp_if_get_bt_patch_path(char *buf, int max_len);
static struct semaphore wr_mtx, rd_mtx;
static struct bt_wake_lock bt_wakelock;
/* Wait queue for poll and read */
@ -213,8 +216,7 @@ static ssize_t __bt_write(uint8_t *buf, size_t count, uint32_t flags)
{
int32_t retval = 0;
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_WR_IN, 0, count, buf);
bt_dbg_tp_evt(TP_ACT_WR_IN, 0, count, buf);
retval = btmtk_send_data(g_sbdev->hdev, buf, count);
if (retval < 0)
@ -311,8 +313,7 @@ static ssize_t BT_read(struct file *filp, char __user *buf, size_t count, loff_t
{
ssize_t retval = 0;
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_RD_IN, 0, count, NULL);
bt_dbg_tp_evt(TP_ACT_RD_IN, 0, count, NULL);
ftrace_print("%s get called, count %zd", __func__, count);
down(&rd_mtx);
@ -377,8 +378,7 @@ static ssize_t BT_read(struct file *filp, char __user *buf, size_t count, loff_t
wait_event(BT_wq, flag != 0);
flag = 0;
} else { /* Got something from RX queue */
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_RD_OUT, 0, retval, i_buf);
bt_dbg_tp_evt(TP_ACT_RD_OUT, 0, retval, i_buf);
break;
}
} while (btmtk_rx_data_valid() && rstflag == CHIP_RESET_NONE);
@ -421,9 +421,11 @@ int _ioctl_copy_evt_to_buf(uint8_t *buf, int len)
static long BT_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
int32_t retval = 0;
int bt_dump_buf_len = 0;
BTMTK_INFO("%s: cmd[0x%08x]", __func__, cmd);
memset(ioc_buf, 0x00, sizeof(ioc_buf));
memset(bt_dump_buf, 0x00, sizeof(bt_dump_buf));
switch (cmd) {
case COMBO_IOCTL_BT_HOST_DEBUG:
/* input: arg(buf_size = 32): id[0:3], value[4:7], desc[8:31]
@ -437,6 +439,12 @@ static long BT_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long
bthost_debug_save(pint32[0], pint32[1], (char*)&ioc_buf[8]);
}
break;
case COMBO_IOCTL_BT_GET_FW_VERSION:
bt_dump_buf_len = fwp_if_get_bt_patch_path(bt_dump_buf, BT_BUFFER_SIZE);
if (copy_to_user((unsigned char __user*)arg, bt_dump_buf, bt_dump_buf_len))
retval = -EFAULT;
BTMTK_INFO("%s: bt_dump_buf = %s, bt_dump_buf_len = %d", __func__, bt_dump_buf, bt_dump_buf_len);
break;
case COMBO_IOCTL_BT_INTTRX:
/* input: arg(buf_size = 128): hci cmd raw data
output: arg(buf_size = 128): hci evt raw data

66
drivers/misc/mediatek/connectivity/bt/mt66xx/btif/btmtk_dbg.c
View file

@ -41,7 +41,6 @@ typedef struct {
* P U B L I C D A T A
********************************************************************************
*/
bool g_bt_trace_pt = FALSE;
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
@ -76,9 +75,10 @@ static int bt_dbg_fpga_test(int par1, int par2, int par3);
static int bt_dbg_is_adie_work(int par1, int par2, int par3);
static int bt_dbg_met_start_stop(int par1, int par2, int par3);
static int bt_dbg_DynamicAdjustTxPower(int par1, int par2, int par3);
#if (BUILD_QA_DBG == 1)
static void bt_dbg_user_trx_proc(char *cmd_raw);
#endif
static int bt_dbg_user_trx_cb(uint8_t *buf, int len);
static int bt_dbg_trace_pt(int par1, int par2, int par3);
extern int32_t btmtk_set_wakeup(struct hci_dev *hdev, uint8_t need_wait);
extern int32_t btmtk_set_sleep(struct hci_dev *hdev, u_int8_t need_wait);
@ -97,7 +97,9 @@ static struct mutex g_bt_lock;
static char g_bt_dump_buf[BT_DBG_DUMP_BUF_SIZE];
static char *g_bt_dump_buf_ptr;
static int g_bt_dump_buf_len;
#if (BUILD_QA_DBG == 1)
static bool g_bt_dbg_enable = FALSE;
#endif
static const tBT_DEV_DBG_STRUCT bt_dev_dbg_struct[] = {
[0x0] = {bt_dbg_hwver_get, FALSE},
@ -123,7 +125,6 @@ static const tBT_DEV_DBG_STRUCT bt_dev_dbg_struct[] = {
[0x12] = {bt_dbg_is_adie_work, TRUE},
[0x13] = {bt_dbg_met_start_stop, FALSE},
[0x14] = {bt_dbg_DynamicAdjustTxPower, FALSE},
[0x15] = {bt_dbg_trace_pt, FALSE},
};
/*******************************************************************************
@ -156,14 +157,6 @@ int bt_dbg_chip_rst(int par1, int par2, int par3)
return 0;
}
int bt_dbg_trace_pt(int par1, int par2, int par3)
{
if(par2 == 0)
g_bt_trace_pt = FALSE;
else
g_bt_trace_pt = TRUE;
return 0;
}
int bt_dbg_read_chipid(int par1, int par2, int par3)
{
@ -230,6 +223,9 @@ int bt_dbg_reg_write(int par1, int par2, int par3)
int bt_dbg_ap_reg_read(int par1, int par2, int par3)
{
#if (BUILD_QA_DBG == 0)
return -ENODEV;
#else
uint32_t *remap_addr = NULL;
int ret_val = 0;
@ -244,6 +240,7 @@ int bt_dbg_ap_reg_read(int par1, int par2, int par3)
BTMTK_INFO("%s: 0x%08x read value = [0x%08x]", __func__, par2, ret_val);
iounmap(remap_addr);
return ret_val;
#endif
}
int bt_dbg_ap_reg_write(int par1, int par2, int par3)
@ -357,7 +354,7 @@ int bt_dbg_met_start_stop(int par1, int par2, int par3)
uint32_t val = 0, star_addr = 0, end_addr = 0;
int res = 0;
struct conn_metlog_info info;
phys_addr_t emi_base;
unsigned int emi_base;
BTMTK_INFO("%s, par2 = %d", __func__, par2);
/* reference parameter:
@ -562,6 +559,9 @@ int bt_dbg_rx_buf_control(int par1, int par2, int par3)
ssize_t bt_dbg_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos)
{
#if (BUILD_QA_DBG == 0)
return -ENODEV;
#else
int ret = 0;
int dump_len;
@ -596,6 +596,7 @@ exit:
mutex_unlock(&g_bt_lock);
return ret;
#endif
}
int bt_osal_strtol(const char *str, unsigned int adecimal, long *res)
@ -632,6 +633,7 @@ end:
return 0;
}
#if (BUILD_QA_DBG == 1)
void bt_dbg_user_trx_proc(char *cmd_raw)
{
#define LEN_64 64
@ -659,9 +661,13 @@ void bt_dbg_user_trx_proc(char *cmd_raw)
// Send command and wait for command_complete event
btmtk_btif_internal_trx(hci_cmd, len, bt_dbg_user_trx_cb, TRUE, TRUE);
}
#endif
ssize_t bt_dbg_write(struct file *filp, const char __user *buffer, size_t count, loff_t *f_pos)
{
#if (BUILD_QA_DBG == 0)
return -ENODEV;
#else
bool is_passwd = FALSE, is_turn_on = FALSE;
size_t len = count;
char buf[256], *pBuf;
@ -684,8 +690,8 @@ ssize_t bt_dbg_write(struct file *filp, const char __user *buffer, size_t count,
if (copy_from_user(buf, buffer, len))
return -EFAULT;
buf[len] = '\0';
BTMTK_INFO("%s: bt_state[%d], dbg_enable[%d], len[%d]",
__func__, bt_state, g_bt_dbg_enable, (int)len);
BTMTK_INFO("%s: bt_state[%d], dbg_enable[%d], len[%d], data = %s",
__func__, bt_state, g_bt_dbg_enable, (int)len, buf);
/* Check debug function is enabled or not
* - not enable yet: user should enable it
@ -731,7 +737,7 @@ ssize_t bt_dbg_write(struct file *filp, const char __user *buffer, size_t count,
if (pToken != NULL) {
bt_osal_strtol(pToken, 16, &res);
y = (int)res;
BTMTK_INFO("%s: y = 0x%08x", __func__, y);
BTMTK_INFO("%s: y = 0x%08x\n\r", __func__, y);
} else {
y = 3000;
/*efuse, register read write default value */
@ -762,6 +768,7 @@ ssize_t bt_dbg_write(struct file *filp, const char __user *buffer, size_t count,
}
return len;
#endif
}
int bt_dev_dbg_init(void)
@ -835,42 +842,17 @@ void bthost_debug_init(void)
void bthost_debug_print(void)
{
uint32_t i = 0;
int32_t ret = 0;
uint8_t *pos = NULL, *end = NULL;
uint8_t dump_buffer[700]={0};
pos = &dump_buffer[0];
end = pos + 700 - 1;
ret = snprintf(pos, (end - pos + 1), "[bt host info] ");
if (ret < 0 || ret >= (end - pos + 1)) {
BTMTK_ERR("snprintf [bt host info] fail");
} else {
pos += ret;
}
for (i = 0; i < BTHOST_INFO_MAX; i++){
if (bthost_info_table[i].id == 0){
ret = snprintf(pos, (end - pos + 1),"[%d-%d] not set", i, BTHOST_INFO_MAX);
if (ret < 0 || ret >= (end - pos + 1)){
BTMTK_ERR("%s: snprintf fail i[%d] ret[%d]", __func__, i, ret);
break;
}
pos += ret;
BTMTK_WARN("[bt host info][%d-%d] not set", i, BTHOST_INFO_MAX);
break;
}
else {
ret = snprintf(pos, (end - pos + 1),"[%d][%s : 0x%08x] ", i,
BTMTK_WARN("[bt host info][%d][%s : 0x%08x]", i,
bthost_info_table[i].desc,
bthost_info_table[i].value);
if (ret < 0 || ret >= (end - pos + 1)){
BTMTK_ERR("%s: snprintf fail i[%d] ret[%d]", __func__, i, ret);
break;
}
pos += ret;
}
}
BTMTK_INFO("%s", dump_buffer);
}
void bthost_debug_save(uint32_t id, uint32_t value, char* desc)

109
drivers/misc/mediatek/connectivity/bt/mt66xx/btif/btmtk_irq.c
View file

@ -27,9 +27,7 @@
* P U B L I C D A T A
********************************************************************************
*/
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)
unsigned long long irq_timer[12] = {0};
#endif
/*******************************************************************************
* P R I V A T E D A T A
@ -38,7 +36,6 @@ unsigned long long irq_timer[12] = {0};
extern struct btmtk_dev *g_sbdev;
static struct bt_irq_ctrl bgf2ap_btif_wakeup_irq = {.name = "BTIF_WAKEUP_IRQ"};
static struct bt_irq_ctrl bgf2ap_sw_irq = {.name = "BGF_SW_IRQ"};
static struct bt_irq_ctrl bt_conn2ap_sw_irq = {.name = "BUS_SW_IRQ"};
static struct bt_irq_ctrl *bt_irq_table[BGF2AP_IRQ_MAX];
static struct work_struct rst_trigger_work;
@ -67,7 +64,7 @@ static struct work_struct rst_trigger_work;
static void bt_reset_work(struct work_struct *work)
{
BTMTK_INFO("Trigger subsys reset");
bt_chip_reset_flow(RESET_LEVEL_0_5, CONNDRV_TYPE_BT, "BT Subsys reset");
bt_chip_reset_flow(RESET_LEVEL_0_5, CONNDRV_TYPE_BT, "Subsys reset");
}
/* bt_trigger_reset
@ -126,10 +123,8 @@ void bt_bgf2ap_irq_handler(void)
if (bgf_status == RET_SWIRQ_ST_FAIL)
return;
if (bgf_status && !(bgf_status & BGF_FW_LOG_NOTIFY)) {
if (!(bgf_status & BGF_FW_LOG_NOTIFY)) {
BTMTK_INFO("bgf_status = 0x%08x", bgf_status);
}else{
BTMTK_DBG("bgf_status = 0x%08x", bgf_status);
}
if (bgf_status == 0xDEADFEED) {
@ -152,28 +147,7 @@ void bt_bgf2ap_irq_handler(void)
}
}
/* bt_conn2ap_irq_handler
*
* Handling BT_CONN2AP_SW_IRQ, include BGF bus hang. And dump SSPM TIMER
* Please be noticed this handler is running in bt thread
* not interrupt thread
*
* Arguments:
* N/A
*
* Return Value:
* N/A
*
*/
void bt_conn2ap_irq_handler(void)
{
uint32_t value = 0;
struct btmtk_btif_dev *cif_dev = (struct btmtk_btif_dev *)g_sbdev->cif_dev;
cif_dev->bt_conn2ap_ind = FALSE;
value = bt_read_cr(BT_SSPM_TIMER);
BTMTK_INFO("%s: [SSPM] [0x%08x] = [0x%08x]", __func__, BT_SSPM_TIMER, value);
bt_trigger_reset();
}
/* btmtk_reset_init()
*
* Inint work thread for subsys chip reset
@ -207,50 +181,19 @@ void btmtk_reset_init(void)
static irqreturn_t btmtk_irq_handler(int irq, void * arg)
{
struct btmtk_btif_dev *cif_dev = (struct btmtk_btif_dev *)g_sbdev->cif_dev;
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)
irq_timer[0] = sched_clock();
#endif
if (irq == bgf2ap_btif_wakeup_irq.irq_num) {
if (cif_dev->rst_level == RESET_LEVEL_NONE) {
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)
irq_timer[1] = sched_clock();
#endif
bt_disable_irq(BGF2AP_BTIF_WAKEUP_IRQ);
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)
irq_timer[7] = sched_clock();
#endif
cif_dev->rx_ind = TRUE;
cif_dev->psm.sleep_flag = FALSE;
wake_up_interruptible(&cif_dev->tx_waitq);
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)
irq_timer[10] = sched_clock();
if (irq_timer[10] - irq_timer[1] > 5000000){
BTMTK_ERR("btif: start1[%llu] b_dis2[%llu] in_dis3[%llu] b_lock4[%llu] a_lock5[%llu] b_unlock6[%llu] a_unlock7[%llu] a_dis8[%llu] end11[%llu]", irq_timer[0], irq_timer[1], irq_timer[2], irq_timer[3], irq_timer[4], irq_timer[5], irq_timer[6], irq_timer[7], irq_timer[10]);
}
#endif
}
return IRQ_HANDLED;
} else if (irq == bgf2ap_sw_irq.irq_num) {
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)
irq_timer[8] = sched_clock();
#endif
bt_disable_irq(BGF2AP_SW_IRQ);
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)
irq_timer[9] = sched_clock();
#endif
cif_dev->bgf2ap_ind = TRUE;
wake_up_interruptible(&cif_dev->tx_waitq);
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)
irq_timer[11] = sched_clock();
if (irq_timer[11] - irq_timer[8] > 5000000){
BTMTK_ERR("sw: start1[%llu] b_dis9[%llu] in_dis3[%llu] b_lock4[%llu] a_lock5[%llu] b_unlock6[%llu] a_unlock7[%llu] a_dis10[%llu] end11[%llu]", irq_timer[0], irq_timer[8], irq_timer[2], irq_timer[3], irq_timer[4], irq_timer[5], irq_timer[6], irq_timer[9], irq_timer[11]);
}
#endif
return IRQ_HANDLED;
} else if (irq == bt_conn2ap_sw_irq.irq_num) {
bt_disable_irq(BT_CONN2AP_SW_IRQ);
cif_dev->bt_conn2ap_ind = TRUE;
wake_up_interruptible(&cif_dev->tx_waitq);
return IRQ_HANDLED;
}
return IRQ_NONE;
@ -280,7 +223,7 @@ int32_t bt_request_irq(enum bt_irq_type irq_type)
node = of_find_compatible_node(NULL, NULL, "mediatek,bt");
if (node) {
irq_num = irq_of_parse_and_map(node, 0);
BTMTK_DBG("irqNum of BGF2AP_BTIF_WAKEUP_IRQ = %d", irq_num);
BTMTK_INFO("irqNum of BGF2AP_BTIF_WAKEUP_IRQ = %d", irq_num);
}
else
BTMTK_ERR("WIFI-OF: get bt device node fail");
@ -292,47 +235,32 @@ int32_t bt_request_irq(enum bt_irq_type irq_type)
node = of_find_compatible_node(NULL, NULL, "mediatek,bt");
if (node) {
irq_num = irq_of_parse_and_map(node, 1);
BTMTK_DBG("irqNum of BGF2AP_SW_IRQ = %d", irq_num);
BTMTK_INFO("irqNum of BGF2AP_SW_IRQ = %d", irq_num);
}
else
BTMTK_ERR("WIFI-OF: get bt device node fail");
irq_flags = IRQF_TRIGGER_HIGH | IRQF_SHARED;
pirq = &bgf2ap_sw_irq;
break;
case BT_CONN2AP_SW_IRQ:
node = of_find_compatible_node(NULL, NULL, "mediatek,bt");
if (node) {
irq_num = irq_of_parse_and_map(node, 2);
BTMTK_DBG("irqNum of BT_CONN2AP_SW_IRQ = %d", irq_num);
}
else
BTMTK_ERR("WIFI-OF: get bt device node fail");
irq_flags = IRQF_TRIGGER_HIGH | IRQF_SHARED;
pirq = &bt_conn2ap_sw_irq;
break;
default:
BTMTK_ERR("Invalid irq_type %d!", irq_type);
return -EINVAL;
}
BTMTK_INFO("pirq = %p, flag = 0x%08x", pirq, irq_flags);
pirq->irq_num = irq_num;
spin_lock_init(&pirq->lock);
pirq->active = TRUE;
ret = request_irq(irq_num, btmtk_irq_handler, irq_flags,
pirq->name, pirq);
if (ret) {
BTMTK_ERR("Request %s (%u) failed! ret(%d)", pirq->name, irq_num, ret);
pirq->active = FALSE;
return ret;
}
ret = enable_irq_wake(irq_num);
if (ret) {
BTMTK_ERR("enable_irq_wake %s (%u) failed! ret(%d)", pirq->name, irq_num, ret);
}
BTMTK_INFO("Request %s (%u) succeed, pirq = %p, flag = 0x%08x", pirq->name, irq_num, pirq, irq_flags);
enable_irq_wake(irq_num);
BTMTK_INFO("Request %s (%u) succeed", pirq->name, irq_num);
bt_irq_table[irq_type] = pirq;
pirq->active = TRUE;
return 0;
}
@ -383,9 +311,6 @@ void bt_disable_irq(enum bt_irq_type irq_type)
{
struct bt_irq_ctrl *pirq;
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)
irq_timer[2] = sched_clock();
#endif
if (irq_type >= BGF2AP_IRQ_MAX) {
BTMTK_ERR("Invalid irq_type %d!", irq_type);
return;
@ -393,24 +318,12 @@ void bt_disable_irq(enum bt_irq_type irq_type)
pirq = bt_irq_table[irq_type];
if (pirq) {
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)
irq_timer[3] = sched_clock();
#endif
spin_lock_irqsave(&pirq->lock, pirq->flags);
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)
irq_timer[4] = sched_clock();
#endif
if (pirq->active) {
disable_irq_nosync(pirq->irq_num);
pirq->active = FALSE;
}
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)
irq_timer[5] = sched_clock();
#endif
spin_unlock_irqrestore(&pirq->lock, pirq->flags);
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)
irq_timer[6] = sched_clock();
#endif
}
}

88
drivers/misc/mediatek/connectivity/bt/mt66xx/btif/btmtk_mt66xx.c
View file

@ -18,10 +18,6 @@
#include "connsys_debug_utility.h"
#include "connfem_api.h"
//#ifdef OPLUS_BUG_STABILITY
// add for MTK ANT SWAP
#include <soc/oplus/system/oplus_project.h>
//#endif /* OPLUS_BUG_STABILITY */
/*******************************************************************************
* M A C R O S
@ -93,13 +89,7 @@ enum FWP_CHECK_STATUS {
static const uint8_t WMT_OVER_HCI_CMD_HDR[] = { 0x01, 0x6F, 0xFC, 0x00 };
#if (CUSTOMER_FW_UPDATE == 1)
//Add for fw sau
#if (OPLUS_FEATURE_BT_FW_SAU_MTK == 1)
static bool g_fwp_update_enable = TRUE;
#else /* OPLUS_FEATURE_BT_FW_SAU_MTK */
static bool g_fwp_update_enable = FALSE;
#endif /* OPLUS_FEATURE_BT_FW_SAU_MTK */
uint8_t g_fwp_names[PATCH_FILE_NUM][2][FW_NAME_LEN] = {};
#else
uint8_t g_fwp_names[PATCH_FILE_NUM][1][FW_NAME_LEN] = {};
@ -111,7 +101,6 @@ static struct fwp_info g_fwp_info;
********************************************************************************
*/
extern bool g_bt_trace_pt;
extern struct btmtk_dev *g_sbdev;
extern struct bt_dbg_st g_bt_dbg_st;
@ -223,7 +212,7 @@ static void fwp_update_info(struct fwp_info *info) {
struct timespec64 time;
struct rtc_time tm;
unsigned long local_time;
//int i;
int i;
ktime_get_real_ts64(&time);
local_time = (uint32_t)(time.tv_nsec/1000 - (sys_tz.tz_minuteswest * 60));
@ -494,12 +483,13 @@ static int32_t __download_patch_to_emi(
patch_emi_offset = (p_patch_hdr->emi_addr[2] << 16) |
(p_patch_hdr->emi_addr[1] << 8);
conninfra_get_phy_addr(&emi_ap_phy_base, NULL);
conninfra_get_phy_addr((uint32_t*)&emi_ap_phy_base, NULL);
emi_ap_phy_base &= 0xFFFFFFFF;
//if ((patch_emi_offset >= emi_start) &&
// (patch_emi_offset + patch_size < emi_start + emi_size)) {
remap_addr = ioremap(emi_ap_phy_base + patch_emi_offset, patch_size);
BTMTK_INFO("[Patch] emi_ap_phy_base[0x%p], remap_addr[0x%08x]", emi_ap_phy_base, *remap_addr);
BTMTK_INFO("[Patch] emi_ap_phy_base[0x%08x], remap_addr[0x%08x]", emi_ap_phy_base, *remap_addr);
BTMTK_INFO("[Patch] patch_emi_offset[0x%08x], patch_size[0x%08x]", patch_emi_offset, patch_size);
if (remap_addr) {
@ -659,13 +649,6 @@ static int32_t bt_hw_and_mcu_on(void)
bt_disable_irq(BGF2AP_SW_IRQ);
if (BT_SSPM_TIMER) {
ret = bt_request_irq(BT_CONN2AP_SW_IRQ);
if (ret)
goto bus_operate_error;
bt_disable_irq(BT_CONN2AP_SW_IRQ);
}
btmtk_reset_init();
if (btmtk_wcn_btif_open()) {
@ -703,19 +686,14 @@ static void bt_hw_and_mcu_off(void)
BTMTK_INFO("%s", __func__);
/* Close hardware bus interface */
btmtk_wcn_btif_close();
BTMTK_INFO("%s: bt_disable_irq start", __func__);
bt_disable_irq(BGF2AP_SW_IRQ);
bt_disable_irq(BGF2AP_BTIF_WAKEUP_IRQ);
BTMTK_INFO("%s: bt_free_irq start", __func__);
/* Free all registered IRQs */
bt_free_irq(BGF2AP_SW_IRQ);
bt_free_irq(BGF2AP_BTIF_WAKEUP_IRQ);
if (BT_SSPM_TIMER) {
bt_disable_irq(BT_CONN2AP_SW_IRQ);
bt_free_irq(BT_CONN2AP_SW_IRQ);
}
BTMTK_INFO("%s: bgfsys_power_off start", __func__);
/* BGFSYS hardware power off */
bgfsys_power_off();
}
@ -785,6 +763,7 @@ static int32_t _send_wmt_power_cmd(struct hci_dev *hdev, u_int8_t is_on)
if (ret <= 0 && is_on) {
BTMTK_ERR("%s: Unable to get event in time, start dump and reset!", __func__);
bt_trigger_reset();
up(&cif_dev->internal_cmd_sem);
}
ret = (p_inter_cmd->result == WMT_EVT_SUCCESS) ? 0 : -EIO;
@ -857,7 +836,6 @@ static int32_t _send_wmt_get_cal_data_cmd(
BTMTK_ERR("Unable to get calibration event in time, start dump and reset!");
// TODO: FW request dump & reset, need apply to all internal cmdå
bt_trigger_reset();
up(&cif_dev->internal_cmd_sem);
return -1;
}
@ -1069,35 +1047,13 @@ int32_t btmtk_intcmd_wmt_send_antenna_cmd(struct hci_dev *hdev)
uint8_t cmd[32] = {0};
long val = 0;
uint8_t cmd_header[] = {0x01, 0x6F, 0xFC, 0x00, 0x01, 0x55, 0x03, 0x00, 0x00};
//#ifndef /* OPLUS_BUG_STABILITY */
// add for MTK ANT SWAP
/*
BTMTK_DBG("%s: load config [%s]", __func__, BT_FW_CFG_FILE);
BTMTK_INFO("%s: load config [%s]", __func__, BT_FW_CFG_FILE);
btmtk_load_code_from_bin(&p_img, BT_FW_CFG_FILE, NULL, &len, 10);
*/
//#else /* OPLUS_BUG_STABILITY */
uint32_t dev_prj = 0;
char str[32];
dev_prj = get_project();
if (dev_prj != 0) {
sprintf(str, "BT_FW_%d.cfg",dev_prj);
BTMTK_INFO("%s: try to load [%s] ", __func__, str);
if (btmtk_load_code_from_bin(&p_img, str, NULL, &len, 2) == -1) {
BTMTK_INFO("%s: [%s] file not exist,load [%s] ", __func__, str, BT_FW_CFG_FILE);
btmtk_load_code_from_bin(&p_img, BT_FW_CFG_FILE, NULL, &len, 10);
}
} else {
BTMTK_INFO("%s: load config [%s]", __func__, BT_FW_CFG_FILE);
btmtk_load_code_from_bin(&p_img, BT_FW_CFG_FILE, NULL, &len, 10);
}
//#endif /* OPLUS_BUG_STABILITY */
if (p_img == NULL) {
BTMTK_WARN("%s: get config file fail!", __func__);
return 0;
}
BTMTK_INFO("%s: load config finish [%s]", __func__, BT_FW_CFG_FILE);
/* find tag: [BT_FW_CFG_TAG][CONNAC20_CHIPID] */
if (snprintf(findTag, sizeof(findTag), "%s[%d] ", BT_FW_CFG_TAG, CONNAC20_CHIPID) < 0) {
@ -1160,7 +1116,7 @@ int32_t btmtk_intcmd_wmt_send_antenna_cmd(struct hci_dev *hdev)
cmd[6] = cmd[10] + 3;
cmd[3] = cmd[6] + 4;
BTMTK_DBG_RAW(cmd, len, "%s: Send: ", __func__);
BTMTK_INFO_RAW(cmd, len, "%s: Send: ", __func__);
down(&cif_dev->internal_cmd_sem);
cif_dev->event_intercept = TRUE;
@ -1169,8 +1125,6 @@ int32_t btmtk_intcmd_wmt_send_antenna_cmd(struct hci_dev *hdev)
p_inter_cmd->wmt_opcode = WMT_OPCODE_ANT_EFEM;
p_inter_cmd->result = WMT_EVT_INVALID;
BTMTK_INFO("[Before btmtk_main_send_cmd] %s done", __func__);
btmtk_main_send_cmd(g_sbdev, cmd, len, NULL, 0, 0, 0, BTMTK_TX_WAIT_VND_EVT);
cif_dev->event_intercept = FALSE;
@ -1208,7 +1162,7 @@ int32_t btmtk_intcmd_wmt_power_off(struct hci_dev *hdev)
} else if (cif_dev->bt_state != RESET_START)
ret = _send_wmt_power_cmd(hdev, FALSE);
BTMTK_DBG("%s: Done", __func__);
BTMTK_INFO("%s: Done", __func__);
return ret;
}
@ -1317,6 +1271,7 @@ int32_t btmtk_intcmd_query_thermal(void)
if (ret <= 0) {
BTMTK_ERR("Unable to send thermal cmd");
up(&cif_dev->internal_cmd_sem);
return -1;
}
@ -1615,14 +1570,13 @@ int32_t btmtk_intcmd_send_connfem_cmd(void)
int32_t btmtk_set_power_on(struct hci_dev *hdev, u_int8_t for_precal)
{
int ret;
bool skip_up_sem = FALSE;
int sch_ret = -1;
struct sched_param sch_param;
struct btmtk_dev *bdev = hci_get_drvdata(hdev);
struct btmtk_btif_dev *cif_dev = (struct btmtk_btif_dev *)g_sbdev->cif_dev;
bool is_wmt_power_on_error = false;
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_PWR_ON, 0, 0, NULL);
bt_dbg_tp_evt(TP_ACT_PWR_ON, 0, 0, NULL);
/*
* 1. ConnInfra hardware power on (Must be the first step)
*
@ -1751,8 +1705,6 @@ int32_t btmtk_set_power_on(struct hci_dev *hdev, u_int8_t for_precal)
#endif
bt_enable_irq(BGF2AP_SW_IRQ);
if (BT_SSPM_TIMER)
bt_enable_irq(BT_CONN2AP_SW_IRQ);
/* 8. init cmd queue and workqueue */
#if (DRIVER_CMD_CHECK == 1)
@ -1800,7 +1752,7 @@ int32_t btmtk_set_power_on(struct hci_dev *hdev, u_int8_t for_precal)
return -EIO;
else if (ret) {
BTMTK_ERR("btmtk_intcmd_wmt_power_on fail");
skip_up_sem = TRUE;
is_wmt_power_on_error = true;
goto wmt_power_on_error;
}
@ -1832,11 +1784,11 @@ mcu_error:
conninfra_pwr_off(CONNDRV_TYPE_BT);
bt_pwrctrl_post_off();
}
if (!is_wmt_power_on_error)
up(&cif_dev->halt_sem);
conninfra_error:
cif_dev->bt_state = FUNC_OFF;
if (!skip_up_sem)
up(&cif_dev->halt_sem);
return ret;
}
@ -1860,8 +1812,7 @@ int32_t btmtk_set_power_off(struct hci_dev *hdev, u_int8_t for_precal)
struct btmtk_btif_dev *cif_dev = (struct btmtk_btif_dev *)g_sbdev->cif_dev;
BTMTK_INFO("%s", __func__);
if (g_bt_trace_pt)
bt_dbg_tp_evt(TP_ACT_PWR_OFF, 0, 0, NULL);
bt_dbg_tp_evt(TP_ACT_PWR_OFF, 0, 0, NULL);
down(&cif_dev->halt_sem);
@ -1888,9 +1839,6 @@ int32_t btmtk_set_power_off(struct hci_dev *hdev, u_int8_t for_precal)
return 0; // directly return since reset thread will perform turn off
}
/* flush fw log in EMI */
connsys_log_irq_handler(CONN_DEBUG_TYPE_BT);
/* 2. Stop TX thread */
#if SUPPORT_BT_THREAD
if (cif_dev->tx_thread) {

27
drivers/misc/mediatek/connectivity/bt/mt66xx/btif/btmtk_queue.c
View file

@ -103,7 +103,7 @@ int32_t rx_skb_enqueue(struct sk_buff *skb)
int32_t ret = 0;
struct btmtk_btif_dev *cif_dev = (struct btmtk_btif_dev *)g_sbdev->cif_dev;
if ( !skb || skb->len == 0) {
if (!skb || skb->len == 0) {
BTMTK_WARN("Inavlid data event, skip, skb = NULL or skb len = 0");
ret = -1;
goto end;
@ -381,7 +381,6 @@ void cmd_list_destory(void)
BTMTK_DBG("%s",__func__);
p_queue = &cif_dev->cmd_queue;
spin_lock(&p_queue->lock);
curr = p_queue->head;
while(curr){
curr = cmd_free_node(curr);
@ -389,7 +388,6 @@ void cmd_list_destory(void)
p_queue->head = NULL;
p_queue->tail = NULL;
p_queue->size = 0;
spin_unlock(&p_queue->lock);
}
void command_response_timeout(struct work_struct *pwork)
@ -408,12 +406,7 @@ void command_response_timeout(struct work_struct *pwork)
btmtk_cif_dump_rxd_backtrace();
btmtk_cif_dump_fw_no_rsp(BT_BTIF_DUMP_REG);
if (cif_dev->cmd_timeout_count == 4) {
spin_lock(&p_queue->lock);
if (p_queue->head)
BTMTK_ERR("%s, !!!! Command Timeout !!!! opcode 0x%4X", __func__, p_queue->head->opcode);
else
BTMTK_ERR("%s, p_queue head is NULL", __func__);
spin_unlock(&p_queue->lock);
BTMTK_ERR("%s, !!!! Command Timeout !!!! opcode 0x%4X", __func__, p_queue->head->opcode);
// To-do : Need to consider if it has any condition to check
cif_dev->cmd_timeout_count = 0;
bt_trigger_reset();
@ -452,12 +445,7 @@ void update_command_response_workqueue(void)
BTMTK_DBG("command queue size = 0");
cancel_delayed_work(&work);
} else {
spin_lock(&p_queue->lock);
if (p_queue->head)
BTMTK_DBG("update new command queue : %4X" , p_queue->head->opcode);
else
BTMTK_ERR("%s, p_queue head is NULL", __func__);
spin_unlock(&p_queue->lock);
BTMTK_DBG("update new command queue : %4X" , p_queue->head->opcode);
cif_dev->cmd_timeout_count = 0;
cancel_delayed_work(&work);
down(&cif_dev->cmd_tout_sem);
@ -471,12 +459,13 @@ void update_command_response_workqueue(void)
void cmd_workqueue_exit(void)
{
struct btmtk_btif_dev *cif_dev = (struct btmtk_btif_dev *)g_sbdev->cif_dev;
int ret_a = 0, ret_b = 0;
int ret = 0;
if(workqueue_task != NULL) {
ret_b = cancel_delayed_work(&work);
ret = cancel_delayed_work(&work);
BTMTK_INFO("cancel workqueue before flush ret[%d]", ret);
flush_workqueue(workqueue_task);
ret_a = cancel_delayed_work(&work);
BTMTK_INFO("cancel workqueue before[%d] after[%d] flush", ret_b, ret_a);
ret = cancel_delayed_work(&work);
BTMTK_INFO("cancel workqueue after flush ret[%d]", ret);
down(&cif_dev->cmd_tout_sem);
destroy_workqueue(workqueue_task);
workqueue_task = NULL;

2
drivers/misc/mediatek/connectivity/bt/mt66xx/btif/init.bt_drv.rc
View file

@ -2,8 +2,6 @@
on property:vendor.connsys.driver.ready=yes
insmod /vendor/lib/modules/bt_drv_${ro.vendor.bt.platform}.ko
chown bluetooth bluetooth /proc/driver/bt_dbg
chown bluetooth bluetooth /proc/driver/wmt_dbg
on property:vendor.connsys.driver.ready=no
insmod /vendor/lib/modules/bt_drv_${ro.vendor.bt.platform}.ko
chown bluetooth bluetooth /proc/driver/bt_dbg
chown bluetooth bluetooth /proc/driver/wmt_dbg

74
drivers/misc/mediatek/connectivity/connfem/Makefile
View file

@ -1,9 +1,71 @@
all:
$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS)
###############################################################################
# Necessary Check
###############################################################################
ifneq ($(KERNEL_OUT),)
ccflags-y += -imacros $(KERNEL_OUT)/include/generated/autoconf.h
endif
modules_install:
$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
ifndef TOP
TOP := $(srctree)/..
endif
clean:
$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
# Force build fail on modpost warning
KBUILD_MODPOST_FAIL_ON_WARNINGS := y
###############################################################################
# GCC Options
###############################################################################
ccflags-y += -Wall
ccflags-y += -Werror
###############################################################################
# Compile Options
###############################################################################
ifneq ($(TARGET_BUILD_VARIANT), user)
ccflags-y += -D CONNFEM_DBG=1
else
ccflags-y += -D CONNFEM_DBG=0
endif
###############################################################################
# Include Paths
###############################################################################
ccflags-y += -I$(src)/include
###############################################################################
# ConnFem Module
###############################################################################
MODULE_NAME := connfem
obj-m += $(MODULE_NAME).o
$(MODULE_NAME)-objs += connfem_module.o
$(MODULE_NAME)-objs += connfem_api.o
$(MODULE_NAME)-objs += connfem_container.o
$(MODULE_NAME)-objs += connfem_dt_parser.o
$(MODULE_NAME)-objs += connfem_epaelna.o
$(MODULE_NAME)-objs += connfem_subsys_bt.o
$(MODULE_NAME)-objs += connfem_subsys_wifi.o
ifneq ($(wildcard $(TOP)/vendor/mediatek/internal/connfem_enable),)
$(info ConnFem: MTK internal load)
$(MODULE_NAME)-objs += connfem_internal.o
else
$(info ConnFem: Customer load)
endif
###############################################################################
# Test
###############################################################################
CONNFEM_TEST_ENABLED = no
ifeq ($(CONNFEM_TEST_ENABLED), yes)
ccflags-y += -D CONNFEM_TEST_ENABLED=1
$(MODULE_NAME)-objs += connfem_test.o
else
ccflags-y += -D CONNFEM_TEST_ENABLED=0
endif

339
drivers/misc/mediatek/connectivity/connfem/NOTICE Normal file
View file

@ -0,0 +1,339 @@
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
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software--to make sure the software is free for all its users. This
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Foundation's software and to any other program whose authors commit to
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When we speak of free software, we are referring to freedom, not
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this service if you wish), that you receive source code or can get it
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To protect your rights, we need to make restrictions that forbid
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These restrictions translate to certain responsibilities for you if you
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impose that choice.
This section is intended to make thoroughly clear what is believed to
be a consequence of the rest of this License.
8. If the distribution and/or use of the Program is restricted in
certain countries either by patents or by copyrighted interfaces, the
original copyright holder who places the Program under this License
may add an explicit geographical distribution limitation excluding
those countries, so that distribution is permitted only in or among
countries not thus excluded. In such case, this License incorporates
the limitation as if written in the body of this License.
9. The Free Software Foundation may publish revised and/or new versions
of the General Public License from time to time. Such new versions will
be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
Each version is given a distinguishing version number. If the Program
specifies a version number of this License which applies to it and "any
later version", you have the option of following the terms and conditions
either of that version or of any later version published by the Free
Software Foundation. If the Program does not specify a version number of
this License, you may choose any version ever published by the Free Software
Foundation.
10. If you wish to incorporate parts of the Program into other free
programs whose distribution conditions are different, write to the author
to ask for permission. For software which is copyrighted by the Free
Software Foundation, write to the Free Software Foundation; we sometimes
make exceptions for this. Our decision will be guided by the two goals
of preserving the free status of all derivatives of our free software and
of promoting the sharing and reuse of software generally.
NO WARRANTY
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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REPAIR OR CORRECTION.
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License.

1
drivers/misc/mediatek/connectivity/connfem/connfem_dt_parser.c
View file

@ -9,7 +9,6 @@
#include <linux/of_gpio.h>
#include <linux/pinctrl/consumer.h>
#include <linux/iio/consumer.h>
#include <linux/slab.h>
#include "connfem.h"
/*******************************************************************************

71
drivers/misc/mediatek/connectivity/connfem/connfem_epaelna.c
View file

@ -693,14 +693,7 @@ void cfm_epaelna_feminfo_dump(struct connfem_epaelna_fem_info *fem_info)
void cfm_epaelna_pininfo_dump(struct connfem_epaelna_pin_info *pin_info)
{
int i, c;
/* Multiply by 5 to align the maximum size like "0xcc," in fem log */
char ant_log[(CONNFEM_EPAELNA_PIN_COUNT * 5) + 1] = {0};
char fem_log[(CONNFEM_EPAELNA_PIN_COUNT * 5) + 1] = {0};
char pol_log[(CONNFEM_EPAELNA_PIN_COUNT * 5) + 1] = {0};
int ant_pos = 0;
int fem_pos = 0;
int pol_pos = 0;
int i;
if (!pin_info) {
pr_info("PinInfo, (null)");
@ -711,65 +704,11 @@ void cfm_epaelna_pininfo_dump(struct connfem_epaelna_pin_info *pin_info)
pin_info->count, CONNFEM_EPAELNA_PIN_COUNT);
for (i = 0; i < pin_info->count; i++) {
if (ant_pos >= sizeof(ant_log) - 1) {
pr_info("[WARN] ant_pos:%d >= ant_log size:%zu",
ant_pos,
sizeof(ant_log) - 1);
break;
}
c = snprintf(ant_log + ant_pos, sizeof(ant_log) - ant_pos,
"%4d,",
pin_info->pin[i].antsel);
if (c < 0 || c >= sizeof(ant_log) - ant_pos) {
pr_info("[WARN] c:%d,ant_log size:%zu",
c,
sizeof(ant_log));
break;
} else {
ant_pos += c;
}
if (fem_pos >= sizeof(fem_log) - 1) {
pr_info("[WARN] fem_pos:%d > fem_log size:%zu",
fem_pos,
sizeof(fem_log) - 1);
break;
}
c = snprintf(fem_log + fem_pos, sizeof(fem_log) - fem_pos,
"0x%02x,",
pin_info->pin[i].fem);
if (c < 0 || c >= sizeof(fem_log) - fem_pos) {
pr_info("[WARN] c:%d,fem_log size:%zu",
c,
sizeof(fem_log));
break;
} else {
fem_pos += c;
}
if (pol_pos >= sizeof(pol_log) - 1) {
pr_info("[WARN] pol_pos:%d > pol_log size:%zu",
pol_pos,
sizeof(pol_log) - 1);
break;
}
c = snprintf(pol_log + pol_pos, sizeof(pol_log) - pol_pos,
"%4d,",
pr_info("PinInfo, [%d]antsel:%d,fem:0x%02x,polarity:%d",
i,
pin_info->pin[i].antsel,
pin_info->pin[i].fem,
pin_info->pin[i].polarity);
if (c < 0 || c >= sizeof(pol_log) - pol_pos) {
pr_info("[WARN] c:%d,pol_log size:%zu",
c,
sizeof(pol_log));
break;
} else {
pol_pos += c;
}
}
if (pin_info->count > 0) {
pr_info("ant:%s", ant_log);
pr_info("fem:%s", fem_log);
pr_info("pol:%s", pol_log);
}
}

8
drivers/misc/mediatek/connectivity/connfem/connfem_module.c
View file

@ -66,8 +66,8 @@ struct connfem_context connfem_ctx_mt6983 = {
struct connfem_context connfem_ctx_mt6879 = {
.id = 0x6879
};
struct connfem_context connfem_ctx_mt6895 = {
.id = 0x6895
struct connfem_context connfem_ctx_mt6877 = {
.id = 0x6877
};
static const struct of_device_id connfem_of_ids[] = {
@ -84,8 +84,8 @@ static const struct of_device_id connfem_of_ids[] = {
.data = (void *)&connfem_ctx_mt6879
},
{
.compatible = "mediatek,mt6895-connfem",
.data = (void *)&connfem_ctx_mt6895
.compatible = "mediatek,mt6877-connfem",
.data = (void *)&connfem_ctx_mt6877
},
{}
};

248
drivers/misc/mediatek/connectivity/conninfra/Makefile
View file

@ -1,8 +1,244 @@
all:
$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS)
###############################################################################
# Necessary Check
modules_install:
$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
ifneq ($(KERNEL_OUT),)
ccflags-y += -imacros $(KERNEL_OUT)/include/generated/autoconf.h
endif
clean:
$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
# Force build fail on modpost warning
KBUILD_MODPOST_FAIL_ON_WARNINGS := y
###############################################################################
# Option for some ALPS specific feature, ex: AEE.
ccflags-y += -D CONNINFRA_PLAT_ALPS=1
ccflags-y += -D MTK_CONNINFRA_CLOCK_BUFFER_API_AVAILABLE=1
ccflags-y += -I$(srctree)/drivers/misc/mediatek/include
ccflags-y += -I$(srctree)/drivers/misc/mediatek/include/mt-plat
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/include/clkbuf_v1
ccflags-y += -I$(srctree)/drivers/misc/mediatek/clkbuf/src/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/connectivity/common
ccflags-y += -I$(srctree)/drivers/misc/mediatek/connectivity/power_throttling
ccflags-y += -I$(srctree)/drivers/misc/mediatek/pmic/include/
ccflags-y += -I$(srctree)/include/linux/soc/mediatek/
ccflags-y += -I$(srctree)/drivers/gpu/drm/mediatek/mediatek_v2
ccflags-y += -I$(srctree)/drivers/memory/mediatek/
###############################################################################
ccflags-y += -Werror
ccflags-y += -Wno-error=format
ccflags-y += -Wno-error=format-extra-args
###############################################################################
MODULE_NAME := conninfra
ifeq ($(CONFIG_WLAN_DRV_BUILD_IN),y)
$(warning $(MODULE_NAME) build-in boot.img)
obj-y += $(MODULE_NAME).o
PATH_TO_CONNINFRA_DRV := $(srctree)/$(src)
else
$(warning $(MODULE_NAME) is kernel module)
obj-m += $(MODULE_NAME).o
PATH_TO_CONNINFRA_DRV := $(src)
endif
###############################################################################
# Common_main
###############################################################################
ccflags-y += -I$(src)/include
ccflags-y += -I$(src)/base/include
ccflags-y += -I$(src)/core/include
ccflags-y += -I$(src)/conf/include
ccflags-y += -I$(src)/drv_init/include
ccflags-y += -I$(src)/platform/include
ccflags-y += -I$(src)/debug_utility
ccflags-y += -I$(src)/debug_utility/include
ccflags-y += -I$(src)/debug_utility/connsyslog
ccflags-y += -I$(src)/debug_utility/connsyslog/platform/include
ccflags-y += -I$(src)/debug_utility/coredump
ccflags-y += -I$(src)/debug_utility/coredump/platform/include
ccflags-y += -I$(src)/debug_utility/metlog
# By Plaftfrom
ifeq ($(CONFIG_MTK_COMBO_CHIP_CONSYS_6885),y)
ifneq ($(wildcard $(PATH_TO_CONNINFRA_DRV)/platform/mt6885),)
ccflags-y += -I$(src)/platform/mt6885/include
ccflags-y += -I$(src)/platform/mt6885/include/CODA
endif
endif
ifeq ($(CONFIG_MTK_COMBO_CHIP_CONSYS_6893),y)
ifneq ($(wildcard $(PATH_TO_CONNINFRA_DRV)/platform/mt6893),)
$(warning $(MODULE_NAME) build mt6893)
ccflags-y += -I$(src)/platform/mt6893/include
ccflags-y += -I$(src)/platform/mt6893/include/CODA
endif
endif
ifeq ($(CONFIG_MTK_COMBO_CHIP_CONSYS_6877),y)
ifneq ($(wildcard $(PATH_TO_CONNINFRA_DRV)/platform/mt6877),)
ccflags-y += -I$(src)/platform/mt6877/include
ccflags-y += -I$(src)/platform/mt6877/include/CODA
endif
endif
ifeq ($(CONFIG_MTK_COMBO_CHIP_CONSYS_6983),y)
ifneq ($(wildcard $(PATH_TO_CONNINFRA_DRV)/platform/mt6983),)
ccflags-y += -I$(src)/platform/mt6983/include
ccflags-y += -I$(src)/platform/mt6983/include/CODA
endif
endif
ifeq ($(CONFIG_MTK_COMBO_CHIP_CONSYS_6879),y)
ifneq ($(wildcard $(PATH_TO_CONNINFRA_DRV)/platform/mt6879),)
ccflags-y += -I$(src)/platform/mt6879/include
ccflags-y += -I$(src)/platform/mt6879/include/CODA
endif
endif
ifeq ($(CONFIG_MTK_COMBO_CHIP_CONSYS_6895),y)
ifneq ($(wildcard $(PATH_TO_CONNINFRA_DRV)/platform/mt6895),)
ccflags-y += -I$(src)/platform/mt6895/include
ccflags-y += -I$(src)/platform/mt6895/include/CODA
endif
endif
ifneq ($(TARGET_BUILD_VARIANT), user)
ccflags-y += -D CONNINFRA_DBG_SUPPORT=1
else
ccflags-y += -D CONNINFRA_DBG_SUPPORT=0
endif
# Build mode option
ifeq ($(TARGET_BUILD_VARIANT),eng)
ccflags-y += -D CONNINFRA_PLAT_BUILD_MODE=1
else ifeq ($(TARGET_BUILD_VARIANT),userdebug)
ccflags-y += -D CONNINFRA_PLAT_BUILD_MODE=2
else ifeq ($(TARGET_BUILD_VARIANT),user)
ccflags-y += -D CONNINFRA_PLAT_BUILD_MODE=3
else
$(info invalid $$TARGET_BUILD_VARIANT[${TARGET_BUILD_VARIANT}])
ccflags-y += -D CONNINFRA_PLAT_BUILD_MODE=0
endif
$(MODULE_NAME)-objs += base/ring.o
$(MODULE_NAME)-objs += base/osal.o
$(MODULE_NAME)-objs += base/msg_thread.o
$(MODULE_NAME)-objs += core/conninfra_core.o
$(MODULE_NAME)-objs += src/conninfra_dev.o
$(MODULE_NAME)-objs += src/conninfra.o
$(MODULE_NAME)-objs += conf/conninfra_conf.o
$(MODULE_NAME)-objs += platform/consys_hw.o
$(MODULE_NAME)-objs += platform/consys_hw_plat_data.o
$(MODULE_NAME)-objs += platform/clock_mng.o
$(MODULE_NAME)-objs += platform/pmic_mng.o
$(MODULE_NAME)-objs += platform/emi_mng.o
$(MODULE_NAME)-objs += platform/consys_reg_mng.o
$(MODULE_NAME)-objs += platform/coredump_mng.o
$(MODULE_NAME)-objs += debug_utility/conninfra_dbg.o
# By Plaftfrom
ifeq ($(CONFIG_MTK_COMBO_CHIP_CONSYS_6885),y)
ifneq ($(wildcard $(PATH_TO_CONNINFRA_DRV)/platform/mt6885),)
$(MODULE_NAME)-objs += platform/mt6885/mt6885.o
$(MODULE_NAME)-objs += platform/mt6885/mt6885_pmic.o
$(MODULE_NAME)-objs += platform/mt6885/mt6885_emi.o
$(MODULE_NAME)-objs += platform/mt6885/mt6885_consys_reg.o
$(MODULE_NAME)-objs += platform/mt6885/mt6885_pos.o
$(MODULE_NAME)-objs += platform/mt6885/mt6885_coredump.o
endif
endif
ifeq ($(CONFIG_MTK_COMBO_CHIP_CONSYS_6893),y)
ifneq ($(wildcard $(PATH_TO_CONNINFRA_DRV)/platform/mt6893),)
$(MODULE_NAME)-objs += platform/mt6893/mt6893.o
$(MODULE_NAME)-objs += platform/mt6893/mt6893_pmic.o
$(MODULE_NAME)-objs += platform/mt6893/mt6893_emi.o
$(MODULE_NAME)-objs += platform/mt6893/mt6893_consys_reg.o
$(MODULE_NAME)-objs += platform/mt6893/mt6893_pos.o
$(MODULE_NAME)-objs += platform/mt6893/mt6893_coredump.o
endif
endif
ifeq ($(CONFIG_MTK_COMBO_CHIP_CONSYS_6877),y)
ifneq ($(wildcard $(PATH_TO_CONNINFRA_DRV)/platform/mt6877),)
$(MODULE_NAME)-objs += platform/mt6877/mt6877.o
$(MODULE_NAME)-objs += platform/mt6877/mt6877_pmic.o
$(MODULE_NAME)-objs += platform/mt6877/mt6877_emi.o
$(MODULE_NAME)-objs += platform/mt6877/mt6877_consys_reg.o
$(MODULE_NAME)-objs += platform/mt6877/mt6877_pos.o
$(MODULE_NAME)-objs += platform/mt6877/mt6877_coredump.o
endif
endif
ifeq ($(CONFIG_MTK_COMBO_CHIP_CONSYS_6983),y)
ifneq ($(wildcard $(PATH_TO_CONNINFRA_DRV)/platform/mt6983),)
$(MODULE_NAME)-objs += platform/mt6983/mt6983.o
$(MODULE_NAME)-objs += platform/mt6983/mt6983_pmic.o
$(MODULE_NAME)-objs += platform/mt6983/mt6983_emi.o
$(MODULE_NAME)-objs += platform/mt6983/mt6983_consys_reg.o
$(MODULE_NAME)-objs += platform/mt6983/mt6983_pos.o
$(MODULE_NAME)-objs += platform/mt6983/mt6983_pos_gen.o
$(MODULE_NAME)-objs += platform/mt6983/mt6983_coredump.o
$(MODULE_NAME)-objs += platform/mt6983/mt6983_debug_gen.o
endif
endif
ifeq ($(CONFIG_MTK_COMBO_CHIP_CONSYS_6879),y)
ifneq ($(wildcard $(PATH_TO_CONNINFRA_DRV)/platform/mt6879),)
$(MODULE_NAME)-objs += platform/mt6879/mt6879.o
$(MODULE_NAME)-objs += platform/mt6879/mt6879_pmic.o
$(MODULE_NAME)-objs += platform/mt6879/mt6879_emi.o
$(MODULE_NAME)-objs += platform/mt6879/mt6879_consys_reg.o
$(MODULE_NAME)-objs += platform/mt6879/mt6879_pos.o
$(MODULE_NAME)-objs += platform/mt6879/mt6879_pos_gen.o
$(MODULE_NAME)-objs += platform/mt6879/mt6879_coredump.o
$(MODULE_NAME)-objs += platform/mt6879/mt6879_debug_gen.o
endif
endif
ifeq ($(CONFIG_MTK_COMBO_CHIP_CONSYS_6895),y)
ifneq ($(wildcard $(PATH_TO_CONNINFRA_DRV)/platform/mt6895),)
$(MODULE_NAME)-objs += platform/mt6895/mt6895.o
$(MODULE_NAME)-objs += platform/mt6895/mt6895_pmic.o
$(MODULE_NAME)-objs += platform/mt6895/mt6895_emi.o
$(MODULE_NAME)-objs += platform/mt6895/mt6895_consys_reg.o
$(MODULE_NAME)-objs += platform/mt6895/mt6895_pos.o
$(MODULE_NAME)-objs += platform/mt6895/mt6895_pos_gen.o
$(MODULE_NAME)-objs += platform/mt6895/mt6895_coredump.o
$(MODULE_NAME)-objs += platform/mt6895/mt6895_debug_gen.o
endif
endif
# Debug utility
$(MODULE_NAME)-objs += debug_utility/connsyslog/ring_emi.o
$(MODULE_NAME)-objs += debug_utility/connsyslog/connsyslog.o
$(MODULE_NAME)-objs += debug_utility/connsyslog/fw_log_mcu.o
$(MODULE_NAME)-objs += debug_utility/connsyslog/fw_log_wifi_mcu.o
$(MODULE_NAME)-objs += debug_utility/connsyslog/fw_log_bt_mcu.o
$(MODULE_NAME)-objs += debug_utility/coredump/connsys_coredump.o
$(MODULE_NAME)-objs += debug_utility/coredump/conndump_netlink.o
$(MODULE_NAME)-objs += debug_utility/metlog/metlog.o
# Drv init
$(MODULE_NAME)-objs += drv_init/bluetooth_drv_init.o
$(MODULE_NAME)-objs += drv_init/conn_drv_init.o
$(MODULE_NAME)-objs += drv_init/fm_drv_init.o
$(MODULE_NAME)-objs += drv_init/gps_drv_init.o
$(MODULE_NAME)-objs += drv_init/wlan_drv_init.o
###############################################################################
# Test
###############################################################################
ifneq ($(TARGET_BUILD_VARIANT), user)
ccflags-y += -D CFG_CONNINFRA_UT_SUPPORT
ccflags-y += -I$(src)/test/include
$(MODULE_NAME)-objs += test/conninfra_core_test.o
$(MODULE_NAME)-objs += test/conf_test.o
$(MODULE_NAME)-objs += test/cal_test.o
$(MODULE_NAME)-objs += test/msg_evt_test.o
$(MODULE_NAME)-objs += test/chip_rst_test.o
$(MODULE_NAME)-objs += test/conninfra_test.o
$(MODULE_NAME)-objs += test/connsyslog_test.o
$(MODULE_NAME)-objs += test/dump_test.o
endif

195
drivers/misc/mediatek/connectivity/conninfra/core/conninfra_core.c
View file

@ -79,8 +79,6 @@ static int opfunc_spi_clock_switch(struct msg_op_data *op);
static int opfunc_clock_fail_dump(struct msg_op_data *op);
static int opfunc_pre_cal_prepare(struct msg_op_data *op);
static int opfunc_pre_cal_check(struct msg_op_data *op);
static int opfunc_pre_cal_backup(struct msg_op_data *op);
static int opfunc_pre_cal_clean(struct msg_op_data *op);
static int opfunc_force_conninfra_wakeup(struct msg_op_data *op);
static int opfunc_force_conninfra_sleep(struct msg_op_data *op);
@ -93,7 +91,6 @@ static int opfunc_subdrv_cal_pwr_on(struct msg_op_data *op);
static int opfunc_subdrv_cal_do_cal(struct msg_op_data *op);
static int opfunc_subdrv_therm_ctrl(struct msg_op_data *op);
static int opfunc_subdrv_time_change(struct msg_op_data *op);
static int opfunc_subdrv_get_cal_result(struct msg_op_data *op);
static void _conninfra_core_update_rst_status(enum chip_rst_status status);
@ -131,8 +128,6 @@ static const msg_opid_func conninfra_core_opfunc[] = {
[CONNINFRA_OPID_FORCE_CONNINFRA_SLEEP] = opfunc_force_conninfra_sleep,
[CONNINFRA_OPID_DUMP_POWER_STATE] = opfunc_dump_power_state,
[CONNINFRA_OPID_PRE_CAL_BACKUP] = opfunc_pre_cal_backup,
[CONNINFRA_OPID_PRE_CAL_CLEAN_DATA] = opfunc_pre_cal_clean,
};
static const msg_opid_func conninfra_core_cb_opfunc[] = {
@ -165,7 +160,7 @@ typedef enum {
INFRA_SUBDRV_OPID_CAL_DO_CAL = 3,
INFRA_SUBDRV_OPID_THERM_CTRL = 4,
INFRA_SUBDRV_OPID_TIME_CHANGED = 5,
INFRA_SUBDRV_OPID_GET_CAL_RESULT= 6,
INFRA_SUBDRV_OPID_MAX
} infra_subdrv_op;
@ -177,7 +172,6 @@ static const msg_opid_func infra_subdrv_opfunc[] = {
[INFRA_SUBDRV_OPID_CAL_DO_CAL] = opfunc_subdrv_cal_do_cal,
[INFRA_SUBDRV_OPID_THERM_CTRL] = opfunc_subdrv_therm_ctrl,
[INFRA_SUBDRV_OPID_TIME_CHANGED] = opfunc_subdrv_time_change,
[INFRA_SUBDRV_OPID_GET_CAL_RESULT] = opfunc_subdrv_get_cal_result,
};
enum pre_cal_type {
@ -276,7 +270,8 @@ static int opfunc_power_on_internal(unsigned int drv_type)
}
/* Check abnormal state */
if (g_conninfra_ctx.drv_inst[drv_type].drv_status >= DRV_STS_MAX) {
if ((g_conninfra_ctx.drv_inst[drv_type].drv_status < DRV_STS_POWER_OFF)
|| (g_conninfra_ctx.drv_inst[drv_type].drv_status >= DRV_STS_MAX)) {
pr_err("func(%d) status[0x%x] abnormal\n", drv_type,
g_conninfra_ctx.drv_inst[drv_type].drv_status);
return -EINVAL;
@ -358,7 +353,8 @@ static int opfunc_power_off_internal(unsigned int drv_type)
}
/* Check abnormal state */
if (g_conninfra_ctx.drv_inst[drv_type].drv_status >= DRV_STS_MAX) {
if ((g_conninfra_ctx.drv_inst[drv_type].drv_status < DRV_STS_POWER_OFF)
|| (g_conninfra_ctx.drv_inst[drv_type].drv_status >= DRV_STS_MAX)) {
pr_err("func(%d) status[0x%x] abnormal\n", drv_type,
g_conninfra_ctx.drv_inst[drv_type].drv_status);
osal_unlock_sleepable_lock(&infra_ctx->core_lock);
@ -565,10 +561,7 @@ static int opfunc_pre_cal(struct msg_op_data *op)
int bt_cal_ret, wf_cal_ret;
struct subsys_drv_inst *drv_inst;
int pre_cal_done_state = (0x1 << CONNDRV_TYPE_BT) | (0x1 << CONNDRV_TYPE_WIFI);
struct timespec64 begin, bt_cal_begin, wf_cal_begin, end, backup_end;
struct subsys_drv_inst *wifi_drv = &g_conninfra_ctx.drv_inst[CONNDRV_TYPE_WIFI];
unsigned int cal_result_offset = 0, cal_result_size = 0;
int get_cal_ret;
struct timespec64 begin, bt_cal_begin, wf_cal_begin, end;
/* Check BT/WIFI status again */
ret = osal_lock_sleepable_lock(&g_conninfra_ctx.core_lock);
@ -585,10 +578,6 @@ static int opfunc_pre_cal(struct msg_op_data *op)
}
}
osal_unlock_sleepable_lock(&g_conninfra_ctx.core_lock);
/* Clean pre-cal backup data */
ret = conninfra_core_pre_cal_clean_data();
if (ret)
pr_info("[pre_cal] clean data fail, ret = %d", ret);
ret = conninfra_core_power_on(CONNDRV_TYPE_BT);
if (ret) {
@ -669,78 +658,17 @@ static int opfunc_pre_cal(struct msg_op_data *op)
conninfra_core_power_off(CONNDRV_TYPE_WIFI);
pr_info(">>>>>>>> WF do cal done");
osal_gettimeofday(&end);
/* Backup WIFI calibration data */
if (wifi_drv->ops_cb.pre_cal_cb.get_cal_result_cb != NULL) {
get_cal_ret = msg_thread_send_wait_3(
&wifi_drv->msg_ctx, INFRA_SUBDRV_OPID_GET_CAL_RESULT,
0,
CONNDRV_TYPE_WIFI, (size_t)&cal_result_offset, (size_t)&cal_result_size);
if (get_cal_ret == 0 && cal_result_size != 0) {
ret = conninfra_core_pre_cal_backup(cal_result_offset, cal_result_size);
if (ret)
pr_err("[pre_cal] backup error: %d", ret);
} else {
pr_info("[pre_cal] get_cal_ret=%d, cal_result_size=%d, cal_result_offset=0x%08x",
get_cal_ret, cal_result_size, cal_result_offset);
}
} else
pr_info("[pre_cal] WIFI not support get_cal_result_cb");
osal_gettimeofday(&backup_end);
pr_info("[pre_cal] summary pwr=[%lu] bt_cal=[%d][%lu] wf_cal=[%d][%lu] backup=[%lu]",
pr_info("[pre_cal] summary pwr=[%lu] bt_cal=[%d][%lu] wf_cal=[%d][%lu]",
timespec64_to_ms(&begin, &bt_cal_begin),
bt_cal_ret, timespec64_to_ms(&bt_cal_begin, &wf_cal_begin),
wf_cal_ret, timespec64_to_ms(&wf_cal_begin, &end),
timespec64_to_ms(&end, &backup_end));
wf_cal_ret, timespec64_to_ms(&wf_cal_begin, &end));
return 0;
}
static int opfunc_pre_cal_backup(struct msg_op_data *op)
{
int ret = 0;
unsigned int offset = op->op_data[0];
unsigned int size = op->op_data[1];
ret = consys_hw_pre_cal_backup(offset, size);
if (ret)
pr_err("[%s] pre-cal backup fail, ret=%d", __func__, ret);
return ret;
}
static int opfunc_pre_cal_clean(struct msg_op_data *op)
{
int ret = 0;
ret = consys_hw_pre_cal_clean_data();
if (ret)
pr_err("[%s] fail, ret = %d", __func__, ret);
return ret;
}
static int opfunc_subdrv_get_cal_result(struct msg_op_data *op)
{
int ret = 0;
unsigned int drv_type = op->op_data[0];
struct subsys_drv_inst *drv_inst;
unsigned int *offset = (unsigned int*)op->op_data[1];
unsigned int *size = (unsigned int*)op->op_data[2];
pr_info("[%s] drv=[%s]", __func__, drv_thread_name[drv_type]);
drv_inst = &g_conninfra_ctx.drv_inst[drv_type];
if (drv_inst->ops_cb.pre_cal_cb.get_cal_result_cb) {
ret = drv_inst->ops_cb.pre_cal_cb.get_cal_result_cb(offset, size);
if (ret)
pr_warn("[%s] fail [%d]", __func__, ret);
}
pr_info("[pre_cal][%s] [%s] DONE", __func__, drv_thread_name[drv_type]);
return ret;
}
static void conninfra_detect_time_change(void) {
static struct timespec64 prev_utc;
static u64 prev_soc_time;
@ -992,7 +920,7 @@ static int opfunc_clock_fail_dump(struct msg_op_data *op)
static int opfunc_pre_cal_prepare(struct msg_op_data *op)
{
int ret = 0, rst_status, num = 0;
int ret, rst_status;
unsigned long flag;
struct pre_cal_info *cal_info = &g_conninfra_ctx.cal_info;
struct subsys_drv_inst *bt_drv = &g_conninfra_ctx.drv_inst[CONNDRV_TYPE_BT];
@ -1021,23 +949,9 @@ static int opfunc_pre_cal_prepare(struct msg_op_data *op)
}
/* non-zero means lock got, zero means not */
ret = osal_trylock_sleepable_lock(&cal_info->pre_cal_lock);
while (!ret) {
ret = osal_trylock_sleepable_lock(&cal_info->pre_cal_lock);
if (ret == 0) {
if (num >= 10) {
/* Another pre-cal should be on progress */
/* Skip to prevent block core thread */
pr_notice("[%s] fail to get pre_cal_lock\n", __func__);
break;
}
/* sleep time is short to make sure get lock easier than */
/* conninfra_core_pre_cal_blocking */
osal_sleep_ms(10);
num++;
continue;
}
if (ret) {
cur_status = cal_info->status;
if ((cur_status == PRE_CAL_NOT_INIT || cur_status == PRE_CAL_NEED_RESCHEDULE) &&
@ -1152,7 +1066,7 @@ static int opfunc_dump_power_state(struct msg_op_data *op)
}
spin_lock_irqsave(&infra_ctx->power_dump_lock, flag);
ret = consys_hw_dump_power_state((char *)op->op_data[0], op->op_data[1]);
ret = consys_hw_dump_power_state();
if (ret)
pr_err("[%s] dump power state fail, ret=%d", __func__, ret);
@ -1317,33 +1231,32 @@ int conninfra_core_pre_cal_start(void)
}
caller = cal_info->caller;
pr_info("[%s] [pre_cal] Caller = %u", __func__, caller);
/* Handle different pre_cal_mode */
switch (g_pre_cal_mode) {
case PRE_CAL_ALL_DISABLED:
pr_info("[%s] [pre_cal] Skip all pre-cal, caller = %u", __func__, caller);
pr_info("[%s] [pre_cal] Skip all pre-cal", __func__);
skip = true;
cal_info->status = PRE_CAL_DONE;
break;
case PRE_CAL_PWR_ON_DISABLED:
if (caller == PRE_CAL_BY_SUBDRV_REGISTER) {
pr_info("[%s] [pre_cal] Skip pre-cal triggered by subdrv register, "
"caller = %u", __func__, caller);
pr_info("[%s] [pre_cal] Skip pre-cal triggered by subdrv register", __func__);
skip = true;
cal_info->status = PRE_CAL_NOT_INIT;
}
break;
case PRE_CAL_SCREEN_ON_DISABLED:
if (caller == PRE_CAL_BY_SCREEN_ON) {
pr_info("[%s] [pre_cal] Skip pre-cal triggered by screen on, "
"caller = %u", __func__, caller);
pr_info("[%s] [pre_cal] Skip pre-cal triggered by screen on", __func__);
skip = true;
cal_info->status = PRE_CAL_DONE;
}
break;
default:
pr_info("[%s] [pre_cal] Begin pre-cal, g_pre_cal_mode: %u, caller = %u",
__func__, g_pre_cal_mode, caller);
pr_info("[%s] [pre_cal] Begin pre-cal, g_pre_cal_mode: %u",
__func__, g_pre_cal_mode);
break;
}
@ -1365,31 +1278,6 @@ int conninfra_core_pre_cal_start(void)
return 0;
}
int conninfra_core_pre_cal_backup(unsigned int offset, unsigned int size)
{
int ret = 0;
struct conninfra_ctx *infra_ctx = &g_conninfra_ctx;
ret = msg_thread_send_wait_2(&infra_ctx->msg_ctx,
CONNINFRA_OPID_PRE_CAL_BACKUP, 0, offset, size);
if (ret)
pr_err("[%s] fail, ret = %d\n", __func__, ret);
return ret;
}
int conninfra_core_pre_cal_clean_data(void)
{
int ret = 0;
struct conninfra_ctx *infra_ctx = &g_conninfra_ctx;
ret = msg_thread_send_wait(
&infra_ctx->msg_ctx,
CONNINFRA_OPID_PRE_CAL_CLEAN_DATA, 0);
if (ret)
pr_err("[%s] fail, ret = %d\n", __func__, ret);
return ret;
}
int conninfra_core_screen_on(void)
{
int ret = 0, rst_status;
@ -1649,10 +1537,8 @@ int conninfra_core_trg_chip_rst(enum consys_drv_type drv, char *reason)
int conninfra_core_thermal_query(int *temp_val)
{
#define PRINT_TEMP_THRESHOLD 60
int ret = 0;
struct conninfra_ctx *infra_ctx = &g_conninfra_ctx;
static DEFINE_RATELIMIT_STATE(_rs, 10 * HZ, 1);
if (temp_val == NULL)
return -1;
@ -1663,24 +1549,12 @@ int conninfra_core_thermal_query(int *temp_val)
if (ret) {
pr_info("thermal query fail ret=%d\n", ret);
return ret;
} else if (*temp_val >= CONNINFRA_MAX_TEMP) {
pr_info("%s: temp[%d] is too high, re-query.\n", __func__, *temp_val);
ret = msg_thread_send_wait_1(&infra_ctx->msg_ctx,
CONNINFRA_OPID_THERM_CTRL, 0,
(size_t) temp_val);
if (ret) {
pr_info("thermal query fail ret=%d\n", ret);
return ret;
}
pr_info("temp of re-query is [%d]\n", *temp_val);
if (*temp_val >= CONNINFRA_MAX_TEMP)
conninfra_trigger_whole_chip_rst(CONNDRV_TYPE_CONNINFRA,
"thermal is too high");
} else {
ratelimit_set_flags(&_rs, RATELIMIT_MSG_ON_RELEASE);
if (__ratelimit(&_rs) || *temp_val > PRINT_TEMP_THRESHOLD)
pr_info("ret=[%d] temp=[%d]\n", ret, *temp_val);
}
pr_info("ret=[%d] temp=[%d]\n", ret, *temp_val);
if (*temp_val >= CONNINFRA_MAX_TEMP)
conninfra_trigger_whole_chip_rst(CONNDRV_TYPE_CONNINFRA, "thermal is too high");
return ret;
}
@ -1709,7 +1583,7 @@ static inline char* conninfra_core_spi_subsys_string(enum sys_spi_subsystem subs
"SYS_SPI_MAX"
};
if (subsystem > SYS_SPI_MAX)
if (subsystem < 0 || subsystem > SYS_SPI_MAX)
return "UNKNOWN";
return subsys_name[subsystem];
@ -1738,12 +1612,8 @@ int conninfra_core_spi_write(enum sys_spi_subsystem subsystem, unsigned int addr
ret = msg_thread_send_wait_3(&(g_conninfra_ctx.msg_ctx), CONNINFRA_OPID_RFSPI_WRITE, 0,
subsystem, addr, data);
if (ret) {
pr_err("[%s] failed (ret = %d). subsystem=%s addr=0x%x data=0x%x\n",
pr_err("[%s] failed (ret = %d). subsystem=%s addr=0x%x data=%d\n",
__func__, ret, conninfra_core_spi_subsys_string(subsystem), addr, data);
if (ret == CONNINFRA_SPI_ADDR_INVALID)
return CONNINFRA_SPI_ADDR_INVALID;
return CONNINFRA_SPI_OP_FAIL;
}
return 0;
@ -1848,7 +1718,7 @@ int conninfra_core_subsys_ops_reg(enum consys_drv_type type,
struct conninfra_ctx *infra_ctx = &g_conninfra_ctx;
int ret, trigger_pre_cal = 0;
if (type >= CONNDRV_TYPE_MAX)
if (type < CONNDRV_TYPE_BT || type >= CONNDRV_TYPE_MAX)
return -1;
spin_lock_irqsave(&g_conninfra_ctx.infra_lock, flag);
@ -1887,7 +1757,7 @@ int conninfra_core_subsys_ops_unreg(enum consys_drv_type type)
{
unsigned long flag;
if (type >= CONNDRV_TYPE_MAX)
if (type < CONNDRV_TYPE_BT || type >= CONNDRV_TYPE_MAX)
return -1;
spin_lock_irqsave(&g_conninfra_ctx.infra_lock, flag);
memset(&g_conninfra_ctx.drv_inst[type].ops_cb, 0,
@ -2040,7 +1910,7 @@ int conninfra_core_reset_power_state(void)
}
int conninfra_core_dump_power_state(char *buf, unsigned int size)
int conninfra_core_dump_power_state(void)
{
int ret = 0;
struct conninfra_ctx *infra_ctx = &g_conninfra_ctx;
@ -2049,12 +1919,7 @@ int conninfra_core_dump_power_state(char *buf, unsigned int size)
* 1. Power state
* 2. Sleep count (if supported)
*/
if (buf && size > 0)
ret = msg_thread_send_wait_2(&infra_ctx->msg_ctx,
CONNINFRA_OPID_DUMP_POWER_STATE,
0, (size_t)buf, size);
else
ret = msg_thread_send(&infra_ctx->msg_ctx,
ret = msg_thread_send(&infra_ctx->msg_ctx,
CONNINFRA_OPID_DUMP_POWER_STATE);
if (ret) {
pr_err("[%s] fail, ret = %d\n", __func__, ret);

6
drivers/misc/mediatek/connectivity/conninfra/core/include/conninfra_core.h
View file

@ -171,8 +171,6 @@ typedef enum {
CONNINFRA_OPID_DUMP_POWER_STATE = 15,
CONNINFRA_OPID_RAISE_VOLTAGE = 16,
CONNINFRA_OPID_RFSPI_UPDATE_BITS = 17,
CONNINFRA_OPID_PRE_CAL_BACKUP = 18,
CONNINFRA_OPID_PRE_CAL_CLEAN_DATA = 19,
CONNINFRA_OPID_MAX
} conninfra_core_opid;
@ -221,8 +219,6 @@ int conninfra_core_pre_cal_start(void);
#if ENABLE_PRE_CAL_BLOCKING_CHECK
void conninfra_core_pre_cal_blocking(void);
#endif
int conninfra_core_pre_cal_backup(unsigned int offset, unsigned int size);
int conninfra_core_pre_cal_clean_data(void);
/* reg control */
/* NOTE: NOT thread-safe
@ -258,7 +254,7 @@ int conninfra_core_force_conninfra_sleep(void);
int conninfra_core_spi_clock_switch(enum connsys_spi_speed_type type);
int conninfra_core_reset_power_state(void);
int conninfra_core_dump_power_state(char *buf, unsigned int size);
int conninfra_core_dump_power_state(void);
int conninfra_core_pmic_event_cb(unsigned int, unsigned int);
void conninfra_core_config_setup(void);

71
drivers/misc/mediatek/connectivity/conninfra/debug_utility/conninfra_dbg.c
View file

@ -37,9 +37,9 @@
static struct proc_dir_entry *g_conninfra_dbg_entry;
ssize_t conninfra_dbg_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos);
#if CONNINFRA_DBG_SUPPORT
static ssize_t conninfra_dbg_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos);
static int conninfra_dbg_hwver_get(int par1, int par2, int par3);
static int conninfra_dbg_chip_rst(int par1, int par2, int par3);
@ -180,10 +180,10 @@ int conninfra_dbg_reg_read(int par1, int par2, int par3)
if (ret < 0) {
pr_info("read chip register (0x%08x) with mask (0x%08x) error(%d)\n",
par2, par3, ret);
return -1;
} else
pr_info("%s", buf);
ret = osal_lock_sleepable_lock(&g_dump_lock);
if (ret) {
pr_err("dump_lock fail!!");
@ -495,7 +495,7 @@ static inline char* conninfra_dbg_spi_subsys_string(enum sys_spi_subsystem subsy
"SYS_SPI_MAX"
};
if (subsystem > SYS_SPI_MAX)
if (subsystem < 0 || subsystem > SYS_SPI_MAX)
return "UNKNOWN";
return subsys_name[subsystem];
@ -504,47 +504,20 @@ static inline char* conninfra_dbg_spi_subsys_string(enum sys_spi_subsystem subsy
static int conninfra_dbg_spi_read(int par1, int par2, int par3)
{
unsigned int data;
int iRet, get_lock_ret, spi_ret, sz;
char buf[CONNINFRA_DBG_DUMP_BUF_SIZE] = {'\0'};
int ret;
if (par2 < 0 || par2 >= SYS_SPI_MAX) {
pr_notice("%s par2 is out of range\n", __func__);
return 0;
}
spi_ret = conninfra_spi_read(par2, par3, &data);
if (spi_ret == 0) {
ret = conninfra_spi_read(par2, par3, &data);
if (ret == 0)
pr_info("%s read[%s]addr[0x%x]val[0x%x] ok\n",
__func__, conninfra_dbg_spi_subsys_string(par2), par3, data);
iRet = snprintf(buf, CONNINFRA_DBG_DUMP_BUF_SIZE, "[%s] addr[0x%08x]=[0x%08x]\n",
conninfra_dbg_spi_subsys_string(par2), par3, data);
} else {
else
pr_notice("%s read[%s]addr[0x%x] failed(%d)\n",
__func__, conninfra_dbg_spi_subsys_string(par2), par3, spi_ret);
iRet = snprintf(buf, CONNINFRA_DBG_DUMP_BUF_SIZE, "[%s] addr[0x%08x] read fail, spi_ret=%d\n",
conninfra_dbg_spi_subsys_string(par2), par3, spi_ret);
}
if (iRet)
pr_info("[%s] string error, iRet = %d", __func__, iRet);
get_lock_ret = osal_lock_sleepable_lock(&g_dump_lock);
if (get_lock_ret) {
pr_notice("[%s] dump lock fail, ret=%d", __func__, get_lock_ret);
return 0;
}
if (g_dump_buf_len < CONNINFRA_DBG_DUMP_BUF_SIZE - 1) {
sz = strlen(buf);
sz = (sz < CONNINFRA_DBG_DUMP_BUF_SIZE - g_dump_buf_len -1) ?
sz : CONNINFRA_DBG_DUMP_BUF_SIZE - g_dump_buf_len - 1;
strncpy(g_dump_buf + g_dump_buf_len, buf, sz);
g_dump_buf_len += sz;
if (g_dump_buf_len >= 0)
g_dump_buf[g_dump_buf_len] = '\0';
}
osal_unlock_sleepable_lock(&g_dump_lock);
__func__, conninfra_dbg_spi_subsys_string(par2), par3, ret);
return 0;
}
@ -629,27 +602,8 @@ static int conninfra_dbg_mcu_log_ctrl(int par1, int par2, int par3)
static int conninfra_dbg_dump_power_state(int par1, int par2, int par3)
{
int ret = 0, len;
consys_hw_dump_power_state();
ret = osal_lock_sleepable_lock(&g_dump_lock);
if (ret) {
pr_notice("dump_lock fail!!");
return ret;
}
ret = conninfra_core_dump_power_state(g_dump_buf, CONNINFRA_DBG_DUMP_BUF_SIZE);
if (ret) {
osal_unlock_sleepable_lock(&g_dump_lock);
return ret;
}
len = strlen(g_dump_buf);
if (len > 0 && len < CONNINFRA_DBG_DUMP_BUF_SIZE) {
g_dump_buf_ptr = g_dump_buf;
g_dump_buf_len = len + 1;
}
osal_unlock_sleepable_lock(&g_dump_lock);
return 0;
}
@ -757,9 +711,9 @@ ssize_t conninfra_dbg_write(struct file *filp, const char __user *buffer, size_t
return len;
}
#endif
/* For user load, only 0x13, 0x14 and 0x40 is allowed to execute */
/* For user load, only 0x13 is allowed to execute */
/* allow command 0x2e to enable catch connsys log on userload */
if (0 == dbg_enabled && (x != 0x13) && (x != 0x14) && (x != 0x40)) {
if (0 == dbg_enabled && (x != 0x13) && (x != 0x14)) {
pr_info("please enable conninfra debug first\n\r");
return len;
}
@ -796,7 +750,6 @@ int conninfra_dev_dbg_init(void)
osal_sleepable_lock_init(&g_dump_lock);
memset(g_dump_buf, '\0', CONNINFRA_DBG_DUMP_BUF_SIZE);
return i_ret;
}

3
drivers/misc/mediatek/connectivity/conninfra/debug_utility/conninfra_dbg.h
View file

@ -11,7 +11,8 @@ typedef int(*CONNINFRA_DEV_DBG_FUNC) (int par1, int par2, int par3);
int conninfra_dev_dbg_init(void);
int conninfra_dev_dbg_deinit(void);
ssize_t conninfra_dbg_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos);
#if CONNINFRA_DBG_SUPPORT
ssize_t conninfra_dbg_write(struct file *filp, const char __user *buf, size_t count, loff_t *f_pos);
#endif
#endif /* _CONNINFRA_DBG_H_ */

33
drivers/misc/mediatek/connectivity/conninfra/debug_utility/connsyslog/connsyslog.c
View file

@ -231,7 +231,7 @@ static int connlog_emi_init(struct connlog_dev* handler, phys_addr_t emiaddr, un
}
if (emiaddr == 0) {
pr_notice("[%s] consys emi memory address invalid emi_addr=%llx emi_size=%d\n",
pr_err("[%s] consys emi memory address invalid emi_addr=%p emi_size=%d\n",
type_to_title[conn_type], emiaddr, emi_size);
return -1;
}
@ -257,9 +257,10 @@ static int connlog_emi_init(struct connlog_dev* handler, phys_addr_t emiaddr, un
handler->log_offset.emi_idx = emi_offset_table[conn_type].emi_idx;
if (handler->virAddrEmiLogBase) {
pr_info("[%s] EMI mapping OK virtual(0x%p) physical(0x%x) size=%d\n",
pr_info("[%s] EMI mapping OK virtual(0x%p) (0x%x) physical(0x%x) size=%d\n",
type_to_title[conn_type],
handler->virAddrEmiLogBase,
handler->virAddrEmiLogBase,
(unsigned int)handler->phyAddrEmiBase,
handler->emi_size);
@ -551,8 +552,7 @@ static void connlog_ring_emi_to_cache(struct connlog_dev* handler)
unsigned int cache_max_size = 0;
#ifndef DEBUG_LOG_ON
static DEFINE_RATELIMIT_STATE(_rs, 10 * HZ, 1);
ratelimit_set_flags(&_rs, RATELIMIT_MSG_ON_RELEASE);
static DEFINE_RATELIMIT_STATE(_rs2, HZ, 1);
#endif
if (handler->conn_type < 0 || handler->conn_type >= CONN_DEBUG_TYPE_END) {
pr_notice("%s conn_type %d is invalid\n", __func__, handler->conn_type);
@ -597,6 +597,12 @@ static void connlog_ring_emi_to_cache(struct connlog_dev* handler)
ring_dump(__func__, &handler->log_buffer.ring_cache);
ring_dump_segment(__func__, &ring_cache_seg);
#endif
#ifndef DEBUG_LOG_ON
if (__ratelimit(&_rs2))
#endif
pr_info("%s: ring_emi_seg.sz=%d, ring_cache_pt=%p, ring_cache_seg.sz=%d\n",
type_to_title[handler->conn_type], ring_emi_seg.sz, ring_cache_seg.ring_pt,
ring_cache_seg.sz);
memcpy_fromio(ring_cache_seg.ring_pt, ring_emi_seg.ring_emi_pt + ring_cache_seg.data_pos,
ring_cache_seg.sz);
emi_buf_size -= ring_cache_seg.sz;
@ -731,9 +737,6 @@ static void connlog_log_data_handler(struct work_struct *work)
#ifndef DEBUG_LOG_ON
static DEFINE_RATELIMIT_STATE(_rs, 10 * HZ, 1);
static DEFINE_RATELIMIT_STATE(_rs2, 2 * HZ, 1);
ratelimit_set_flags(&_rs, RATELIMIT_MSG_ON_RELEASE);
ratelimit_set_flags(&_rs2, RATELIMIT_MSG_ON_RELEASE);
#endif
if (handler == NULL) {
@ -843,8 +846,7 @@ static ssize_t connlog_read_internal(
int retval;
#ifndef DEBUG_LOG_ON
static DEFINE_RATELIMIT_STATE(_rs, 10 * HZ, 1);
ratelimit_set_flags(&_rs, RATELIMIT_MSG_ON_RELEASE);
static DEFINE_RATELIMIT_STATE(_rs2, 1 * HZ, 1);
#endif
if (conn_type < 0 || conn_type >= CONN_DEBUG_TYPE_END) {
@ -874,6 +876,14 @@ static ssize_t connlog_read_internal(
}
cache_buf_size -= ring_seg.sz;
written += ring_seg.sz;
#ifndef DEBUG_LOG_ON
if (__ratelimit(&_rs2))
#endif
pr_info("[%s] copy %d to %s\n",
type_to_title[conn_type],
ring_seg.sz,
(to_user? "user space" : "buffer"));
}
done:
return written;
@ -1210,7 +1220,7 @@ int connsys_log_init(int conn_type)
log_start_addr = emi_config->log_offset + gPhyEmiBase;
log_size = emi_config->log_size;
pr_info("%s init. Base=%llx size=%d\n",
pr_info("%s init. Base=%p size=%d\n",
type_to_title[conn_type], log_start_addr, log_size);
// Check if emi layout contains mcu block
@ -1509,7 +1519,7 @@ EXPORT_SYMBOL(connsys_dedicated_log_path_blank_state_changed);
int connsys_dedicated_log_path_apsoc_init(phys_addr_t emiaddr, const struct connlog_emi_config* config)
{
if (gPhyEmiBase != 0 || emiaddr == 0) {
pr_notice("Connsys log double init or invalid parameter(emiaddr=%llx)\n", emiaddr);
pr_err("Connsys log double init or invalid parameter(emiaddr=%p)\n", emiaddr);
return -1;
}
@ -1599,6 +1609,7 @@ int connsys_dedicated_log_set_ap_state(int state)
}
EMI_WRITE32(handler->virAddrEmiLogBase + 32, state);
pr_info("%s state: drv:%s %d\n", __func__, type_to_title[i], state);
}
return 0;

6
drivers/misc/mediatek/connectivity/conninfra/debug_utility/coredump/conndump_netlink.c
View file

@ -248,7 +248,7 @@ static int conndump_nl_bind_internal(struct dump_netlink_ctx* ctx, struct sk_buf
if (port_na) {
port = (unsigned int)nla_get_u32(port_na);
} else {
pr_notice("%s:-> no port_na found\n", __func__);
pr_err("%s:-> no port_na found\n");
return -1;
}
@ -524,8 +524,8 @@ int conndump_netlink_send_to_native(int conn_type, char* tag, char* buf, unsigne
unsigned int remain_len = length;
int ret;
pr_info("[%s] conn_type=%d tag=%s length=%d\n",
__func__, conn_type, tag, length);
pr_info("[%s] conn_type=%d tag=%s buf=0x%x length=%d\n",
__func__, conn_type, tag, buf, length);
if ((conn_type < CONN_DEBUG_TYPE_WIFI || conn_type > CONN_DEBUG_TYPE_BT) || tag == NULL) {
pr_err("Incorrect type (%d), tag = %s\n", conn_type, tag);
return -1;

16
drivers/misc/mediatek/connectivity/conninfra/debug_utility/coredump/connsys_coredump.c
View file

@ -277,7 +277,7 @@ static void conndump_timeout_handler(timer_handler_arg arg)
GET_HANDLER_DATA(arg, data);
ctx = (struct connsys_dump_ctx*)data;
if (ctx) {
pr_info("[%d] coredump timeout\n", ctx->conn_type);
pr_info("[%s] coredump timeout\n", ctx->conn_type);
conndump_set_dump_state(ctx, CORE_DUMP_TIMEOUT);
}
}
@ -559,9 +559,9 @@ static void conndump_info_analysis(
pr_err("parser ' ' is not find\n");
pTemp2 = pTemp + 1;
}
pr_info("(pTemp2 - pTemp)=%ld\n", (pTemp2 - pTemp));
pr_info("(pTemp2 - pTemp)=%d\n", (pTemp2 - pTemp));
if ((remain_array_len) > (pTemp2 - pTemp)) {
pr_info("Copy %ld\n", pTemp2 - pTemp);
pr_info("Copy %d\n", pTemp2 - pTemp);
memcpy(
&ctx->info.assert_info[idx],
pTemp,
@ -1283,7 +1283,7 @@ static void conndump_exception_show(struct connsys_dump_ctx* ctx, bool full_dump
}
#if defined(CONNINFRA_PLAT_ALPS) && CONNINFRA_PLAT_ALPS
pr_info("par1: [%s] pars: [%s] par3: [%lu]\n",
pr_info("par1: [%s] pars: [%s] par3: [%d]\n",
ctx->hw_config.exception_tag_name,
ctx->info.exception_log,
strlen(ctx->info.exception_log));
@ -1414,13 +1414,12 @@ int connsys_coredump_start(
struct timespec64 begin, end, put_done;
struct timespec64 mem_start, mem_end, cr_start, cr_end, emi_dump_start, emi_dump_end;
unsigned int coredump_mode = 0;
static DEFINE_RATELIMIT_STATE(_rs, HZ, 1);
if (ctx == NULL || ctx->conn_type < 0 || ctx->conn_type > CONN_DEBUG_TYPE_BT)
return 0;
ratelimit_set_flags(&_rs, RATELIMIT_MSG_ON_RELEASE);
/* TODO: Check coredump mode */
coredump_mode = connsys_coredump_get_mode();
if (coredump_mode == DUMP_MODE_RESET_ONLY)
@ -1461,7 +1460,6 @@ int connsys_coredump_start(
conndump_send_fake_coredump(ctx);
goto partial_dump;
}
if (__ratelimit(&_rs)) {
pr_info("Wait coredump state, EMI[0]=0x%x EMI[4]=0x%x\n",
conndump_get_dmp_info(ctx, 0, false),
@ -1623,7 +1621,7 @@ void* connsys_coredump_init(
/* EMI init */
conninfra_get_emi_phy_addr(CONNSYS_EMI_FW, &emi_base, &emi_size);
conninfra_get_emi_phy_addr(CONNSYS_EMI_MCIF, NULL, &mcif_emi_size);
pr_info("conn_type=%d Get emi_base=0x%llx emi_size=%d\n", conn_type, emi_base, emi_size);
pr_info("conn_type=%d Get emi_base=0x%x emi_size=%d\n", conn_type, emi_base, emi_size);
ctx->full_emi_size = emi_size;
ctx->emi_phy_addr_base = config->start_offset + emi_base;
ctx->emi_size = config->size;
@ -1632,7 +1630,7 @@ void* connsys_coredump_init(
ctx->emi_virt_addr_base =
ioremap(ctx->emi_phy_addr_base, ctx->emi_size);
if (ctx->emi_virt_addr_base == 0) {
pr_notice("Remap emi fail (0x%llx) size=%d",
pr_err("Remap emi fail (0x%08x) size=%d",
ctx->emi_phy_addr_base, ctx->emi_size);
goto error_exit;
}

4
drivers/misc/mediatek/connectivity/conninfra/debug_utility/metlog/metlog.c
View file

@ -108,8 +108,8 @@ static int met_thread(void *pvData)
info = &data->info;
pr_info("type %d\n", info->type);
pr_info("read_cr %llx, write_cr %llx\n", info->read_cr, info->write_cr);
pr_info("met_base_ap %llx met_base_fw 0x%x, met_size 0x%x, output_len %d\n",
pr_info("read_cr 0x%x, write_cr 0x%x\n", info->read_cr, info->write_cr);
pr_info("met_base_ap 0x%x met_base_fw 0x%x, met_size 0x%x, output_len %d\n",
info->met_base_ap, info->met_base_fw, info->met_size, info->output_len);
if (info->read_cr == 0 || info->write_cr == 0 || info->met_base_ap == 0 ||

6
drivers/misc/mediatek/connectivity/conninfra/debug_utility/metlog/metlog.h
View file

@ -22,9 +22,9 @@
*/
struct conn_metlog_info {
int type;
phys_addr_t read_cr;
phys_addr_t write_cr;
phys_addr_t met_base_ap;
unsigned int read_cr;
unsigned int write_cr;
unsigned int met_base_ap;
unsigned int met_base_fw;
unsigned int met_size;
unsigned int output_len;

4
drivers/misc/mediatek/connectivity/conninfra/include/conninfra.h
View file

@ -124,7 +124,6 @@ enum connsys_ic_info_type
};
#define CONNINFRA_SPI_OP_FAIL 0x1
#define CONNINFRA_SPI_ADDR_INVALID -0x777
#define CONNINFRA_CB_RET_CAL_PASS_POWER_OFF 0x0
#define CONNINFRA_CB_RET_CAL_PASS_POWER_ON 0x2
@ -189,7 +188,7 @@ int conninfra_spi_write(enum sys_spi_subsystem subsystem, unsigned int addr, uns
int conninfra_spi_update_bits(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data, unsigned int mask);
/* EMI */
void conninfra_get_phy_addr(phys_addr_t *addr, unsigned int *size);
void conninfra_get_phy_addr(unsigned int *addr, unsigned int *size);
void conninfra_get_emi_phy_addr(enum connsys_emi_type type, phys_addr_t* base, unsigned int *size);
/* power on/off */
@ -256,7 +255,6 @@ struct whole_chip_rst_cb {
struct pre_calibration_cb {
int (*pwr_on_cb)(void);
int (*do_cal_cb)(void);
int (*get_cal_result_cb)(unsigned int* offset, unsigned int* size);
};
struct sub_drv_ops_cb {

1
drivers/misc/mediatek/connectivity/conninfra/platform/clock_mng.c
View file

@ -78,7 +78,6 @@ static struct platform_driver consys_mt6685_dev_drv = {
#ifdef CONFIG_OF
.of_match_table = consys_clock_mt6685_of_ids,
#endif
.probe_type = PROBE_FORCE_SYNCHRONOUS,
},
};

117
drivers/misc/mediatek/connectivity/conninfra/platform/consys_hw.c
View file

@ -21,7 +21,6 @@
#include "connsys_debug_utility.h"
#include "coredump_mng.h"
#include "conn_power_throttling.h"
#include "aee.h"
/*******************************************************************************
* C O M P I L E R F L A G S
@ -76,7 +75,6 @@ static void _consys_hw_conninfra_sleep(void);
* 0: No, the request is from sub-radio
*/
static int _consys_hw_raise_voltage(enum consys_drv_type drv_type, bool raise, bool onoff);
static void _consys_hw_conninfra_print_wakeup_record(void);
/*******************************************************************************
* P U B L I C D A T A
@ -94,7 +92,6 @@ static struct platform_driver mtk_conninfra_dev_drv = {
#ifdef CONFIG_OF
.of_match_table = apconninfra_of_ids,
#endif
.probe_type = PROBE_FORCE_SYNCHRONOUS,
},
};
@ -104,13 +101,7 @@ struct consys_hw_env conn_hw_env;
const struct consys_hw_ops_struct *consys_hw_ops;
struct platform_device *g_pdev;
static int g_conninfra_wakeup_ref_cnt;
#define CONNINFRA_WAKEUP_RECORD_NUM 6
static int g_conninfra_wakeup_rec_idx;
static unsigned long long g_conninfra_wakeup_rec_sec[CONNINFRA_WAKEUP_RECORD_NUM];
static unsigned long g_conninfra_wakeup_rec_nsec[CONNINFRA_WAKEUP_RECORD_NUM];
static int g_conninfra_wakeup_rec_cnt[CONNINFRA_WAKEUP_RECORD_NUM];
int g_conninfra_wakeup_ref_cnt;
struct work_struct ap_resume_work;
@ -118,6 +109,7 @@ struct conninfra_dev_cb *g_conninfra_dev_cb;
const struct conninfra_plat_data *g_conninfra_plat_data = NULL;
struct pinctrl *g_conninfra_pinctrl_ptr = NULL;
static atomic_t g_hw_init_done = ATOMIC_INIT(0);
static unsigned int g_adie_chipid = 0;
static OSAL_SLEEPABLE_LOCK g_adie_chipid_lock;
@ -128,7 +120,6 @@ static int g_platform_config;
static struct notifier_block conninfra_pm_notifier;
static atomic_t g_hw_init_done = ATOMIC_INIT(0);
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
@ -208,7 +199,8 @@ int consys_hw_pwr_off(unsigned int curr_status, unsigned int off_radio)
int ret = 0;
if (next_status == 0) {
pr_info("Last power off: %d, Power off CONNSYS PART 1\n", off_radio);
pr_info("Last power off: %d\n", off_radio);
pr_info("Power off CONNSYS PART 1\n");
consys_hw_raise_voltage(off_radio, false, true);
if (consys_hw_ops->consys_plt_conninfra_on_power_ctrl)
consys_hw_ops->consys_plt_conninfra_on_power_ctrl(0);
@ -261,7 +253,7 @@ int _consys_hw_pwr_on_rollback(enum conninfra_pwr_on_rollback_type type)
pr_err("[%s] turn off VCN control fail, ret=%d\n", __func__, ret);
break;
default:
pr_notice("[%s] wrong type: %u", __func__, type);
pr_err("[%s] wrong type: %d", type);
break;
}
return 0;
@ -435,8 +427,12 @@ int consys_hw_therm_query(int *temp_ptr)
/* wake/sleep conninfra */
if (consys_hw_ops && consys_hw_ops->consys_plt_thermal_query) {
ret = _consys_hw_conninfra_wakeup();
if (ret)
if (ret) {
ret = consys_hw_is_bus_hang();
consys_hw_clock_fail_dump();
pr_info("[%s] bus status=%d", __func__, ret);
return CONNINFRA_ERR_WAKEUP_FAIL;
}
*temp_ptr = consys_hw_ops->consys_plt_thermal_query();
_consys_hw_conninfra_sleep();
} else
@ -469,10 +465,10 @@ int consys_hw_reset_power_state(void)
return ret;
}
int consys_hw_dump_power_state(char *buf, unsigned int size)
int consys_hw_dump_power_state(void)
{
if (consys_hw_ops && consys_hw_ops->consys_plt_power_state)
consys_hw_ops->consys_plt_power_state(buf, size);
consys_hw_ops->consys_plt_power_state();
return 0;
}
@ -530,38 +526,9 @@ int consys_hw_raise_voltage(enum consys_drv_type drv_type, bool raise, bool onof
return 0;
}
static void _consys_hw_conninfra_add_wakeup_record(int count)
{
unsigned long long sec = 0;
unsigned long nsec = 0;
osal_get_local_time(&sec, &nsec);
if (g_conninfra_wakeup_rec_idx >= CONNINFRA_WAKEUP_RECORD_NUM)
g_conninfra_wakeup_rec_idx = 0;
g_conninfra_wakeup_rec_cnt[g_conninfra_wakeup_rec_idx] = count;
g_conninfra_wakeup_rec_sec[g_conninfra_wakeup_rec_idx] = sec;
g_conninfra_wakeup_rec_nsec[g_conninfra_wakeup_rec_idx] = nsec;
g_conninfra_wakeup_rec_idx++;
if (g_conninfra_wakeup_rec_idx == CONNINFRA_WAKEUP_RECORD_NUM)
_consys_hw_conninfra_print_wakeup_record();
}
static void _consys_hw_conninfra_print_wakeup_record(void)
{
unsigned long long *sec = g_conninfra_wakeup_rec_sec;
unsigned long *nsec = g_conninfra_wakeup_rec_nsec;
int *cnt = g_conninfra_wakeup_rec_cnt;
pr_info("conn_wakeup:%llu.%06lu:%d; %llu.%06lu:%d; %llu.%06lu:%d; %llu.%06lu:%d; %llu.%06lu:%d; %llu.%06lu:%d",
sec[0], nsec[0], cnt[0], sec[1], nsec[1], cnt[1], sec[2], nsec[2], cnt[2],
sec[3], nsec[3], cnt[3], sec[4], nsec[4], cnt[4], sec[5], nsec[5], cnt[5]);
}
static int _consys_hw_conninfra_wakeup(void)
{
int ref = g_conninfra_wakeup_ref_cnt;
bool wakeup = false, ret;
if (consys_hw_ops->consys_plt_conninfra_wakeup) {
@ -574,13 +541,16 @@ static int _consys_hw_conninfra_wakeup(void)
wakeup = true;
}
g_conninfra_wakeup_ref_cnt++;
_consys_hw_conninfra_add_wakeup_record(g_conninfra_wakeup_ref_cnt);
}
pr_info("conninfra_wakeup refcnt=[%d]->[%d] %s",
ref, g_conninfra_wakeup_ref_cnt, (wakeup ? "wakeup!!" : ""));
return 0;
}
static void _consys_hw_conninfra_sleep(void)
{
int ref = g_conninfra_wakeup_ref_cnt;
bool sleep = false;
if (consys_hw_ops->consys_plt_conninfra_sleep &&
@ -588,16 +558,8 @@ static void _consys_hw_conninfra_sleep(void)
sleep = true;
consys_hw_ops->consys_plt_conninfra_sleep();
}
if (g_conninfra_wakeup_ref_cnt < 0) {
#if IS_ENABLED(CONFIG_MTK_AEE_FEATURE)
aee_kernel_exception("conninfra", "%s count %d is unexpected.", __func__, g_conninfra_wakeup_ref_cnt);
#else
pr_notice("%s count %d is unexpected.", __func__, g_conninfra_wakeup_ref_cnt);
#endif
_consys_hw_conninfra_print_wakeup_record();
} else
_consys_hw_conninfra_add_wakeup_record(g_conninfra_wakeup_ref_cnt);
pr_info("conninfra_sleep refcnt=[%d]->[%d] %s",
ref, g_conninfra_wakeup_ref_cnt, (sleep ? "sleep!!" : ""));
}
int consys_hw_force_conninfra_wakeup(void)
@ -713,24 +675,11 @@ u64 consys_hw_soc_timestamp_get(void)
return 0;
}
int consys_hw_pre_cal_backup(unsigned int offset, unsigned int size)
{
if (consys_hw_ops->consys_plt_pre_cal_backup)
return consys_hw_ops->consys_plt_pre_cal_backup(offset, size);
return 0;
}
int consys_hw_pre_cal_clean_data(void)
{
if (consys_hw_ops->consys_plt_pre_cal_clean_data)
return consys_hw_ops->consys_plt_pre_cal_clean_data();
return 0;
}
int mtk_conninfra_probe(struct platform_device *pdev)
{
int ret = -1;
struct consys_emi_addr_info* emi_info = NULL;
struct conn_pwr_plat_info pwr_info;
if (pdev == NULL) {
pr_err("[%s] invalid input", __func__);
@ -784,6 +733,12 @@ int mtk_conninfra_probe(struct platform_device *pdev)
g_pdev = pdev;
osal_sleepable_lock_init(&g_adie_chipid_lock);
pwr_info.chip_id = consys_hw_chipid_get();
pwr_info.adie_id = consys_hw_detect_adie_chipid();
pwr_info.get_temp = consys_hw_therm_query;
ret = conn_pwr_init(&pwr_info);
if (ret < 0)
pr_info("conn_pwr_init is failed %d.", ret);
atomic_set(&g_hw_init_done, 1);
return 0;
@ -791,13 +746,14 @@ int mtk_conninfra_probe(struct platform_device *pdev)
int mtk_conninfra_remove(struct platform_device *pdev)
{
atomic_set(&g_hw_init_done, 0);
conn_pwr_deinit();
if (consys_hw_ops->consys_plt_clk_detach)
consys_hw_ops->consys_plt_clk_detach();
else
pr_info("consys_plt_clk_detach is null");
atomic_set(&g_hw_init_done, 0);
if (g_pdev)
g_pdev = NULL;
@ -872,17 +828,13 @@ void consys_hw_set_mcu_control(int type, bool onoff)
int consys_hw_init(struct conninfra_dev_cb *dev_cb)
{
int iRet = 0, ret = 0, retry = 0;
phys_addr_t emi_addr = 0;
unsigned int emi_size = 0;
int iRet = 0, retry = 0, ret = 0;
static DEFINE_RATELIMIT_STATE(_rs, HZ, 1);
unsigned int emi_addr = 0;
unsigned int emi_size = 0;
ratelimit_set_flags(&_rs, RATELIMIT_MSG_ON_RELEASE);
g_conninfra_dev_cb = dev_cb;
pmic_mng_register_device();
clock_mng_register_device();
atomic_set(&g_hw_init_done, 0);
iRet = platform_driver_register(&mtk_conninfra_dev_drv);
if (iRet)
pr_err("Conninfra platform driver registered failed(%d)\n", iRet);
@ -895,6 +847,9 @@ int consys_hw_init(struct conninfra_dev_cb *dev_cb)
}
}
pmic_mng_register_device();
clock_mng_register_device();
conninfra_get_phy_addr(&emi_addr, &emi_size);
connectivity_export_conap_scp_init(consys_hw_get_ic_info(CONNSYS_SOC_CHIPID), emi_addr);
@ -903,7 +858,7 @@ int consys_hw_init(struct conninfra_dev_cb *dev_cb)
conninfra_pm_notifier.notifier_call = conninfra_pm_notifier_callback;
ret = register_pm_notifier(&conninfra_pm_notifier);
if (ret < 0)
pr_notice("%s register_pm_notifier fail %d\n", __func__, ret);
pr_notice("%s register_pm_notifier fail %d\n", ret);
pr_info("[consys_hw_init] result [%d]\n", iRet);

2
drivers/misc/mediatek/connectivity/conninfra/platform/consys_reg_mng.c
View file

@ -119,6 +119,8 @@ int consys_reg_mng_reg_read(unsigned long addr, unsigned int *value, unsigned in
*value = (unsigned int)CONSYS_REG_READ(vir_addr) & mask;
pr_info("[%x] mask=[%x]", *value, mask);
iounmap(vir_addr);
return 0;
}

40
drivers/misc/mediatek/connectivity/conninfra/platform/emi_mng.c
View file

@ -86,8 +86,6 @@ struct consys_emi_addr_info connsys_emi_addr_info = {
.emi_size = 0,
.md_emi_phy_addr = 0,
.md_emi_size = 0,
.gps_emi_phy_addr = 0,
.gps_emi_size = 0,
};
/*******************************************************************************
@ -113,8 +111,7 @@ int emi_mng_set_remapping_reg(void)
consys_platform_emi_ops->consys_ic_emi_set_remapping_reg)
return consys_platform_emi_ops->consys_ic_emi_set_remapping_reg(
connsys_emi_addr_info.emi_ap_phy_addr,
connsys_emi_addr_info.md_emi_phy_addr,
connsys_emi_addr_info.gps_emi_phy_addr);
connsys_emi_addr_info.md_emi_phy_addr);
return -1;
}
@ -123,33 +120,6 @@ struct consys_emi_addr_info* emi_mng_get_phy_addr(void)
return &connsys_emi_addr_info;
}
static void emi_mng_get_gps_emi(struct platform_device *pdev)
{
struct device_node *node;
unsigned int phy_addr = 0;
unsigned int phy_size = 0;
node = of_find_node_by_name(NULL, "gps");
if (!node) {
pr_notice("%s failed to find gps node\n", __func__);
return;
}
if (of_property_read_u32(node, "emi-addr", &phy_addr)) {
pr_info("%s: unable to get emi_addr\n", __func__);
return;
}
if (of_property_read_u32(node, "emi-size", &phy_size)) {
pr_info("%s: unable to get emi_size\n", __func__);
return;
}
connsys_emi_addr_info.gps_emi_phy_addr = phy_addr;
connsys_emi_addr_info.gps_emi_size = phy_size;
pr_info("%s emi_addr %x, emi_size %x\n", __func__, phy_addr, phy_size);
}
#ifdef ALLOCATE_CONNSYS_EMI_FROM_DTS
static int emi_mng_allocate_connsys_emi(struct platform_device *pdev)
{
@ -179,7 +149,7 @@ static int emi_mng_allocate_connsys_emi(struct platform_device *pdev)
static int emi_mng_get_emi_allocated_by_lk2(struct platform_device *pdev)
{
struct device_node *node;
u64 phy_addr = 0;
unsigned int phy_addr = 0;
unsigned int phy_size = 0;
node = pdev->dev.of_node;
@ -188,7 +158,7 @@ static int emi_mng_get_emi_allocated_by_lk2(struct platform_device *pdev)
return -1;
}
if (of_property_read_u64(node, "emi-addr", &phy_addr)) {
if (of_property_read_u32(node, "emi-addr", &phy_addr)) {
pr_info("%s: unable to get emi_addr\n", __func__);
return -1;
}
@ -198,7 +168,7 @@ static int emi_mng_get_emi_allocated_by_lk2(struct platform_device *pdev)
return -1;
}
pr_info("%s emi_addr %llx, emi_size %x\n", __func__, phy_addr, phy_size);
pr_info("%s emi_addr %x, emi_size %x\n", __func__, phy_addr, phy_size);
gConEmiPhyBase = phy_addr;
gConEmiSize = phy_size;
@ -236,8 +206,6 @@ int emi_mng_init(struct platform_device *pdev, const struct conninfra_plat_data*
consys_platform_emi_ops->consys_ic_emi_mpu_set_region_protection)
consys_platform_emi_ops->consys_ic_emi_mpu_set_region_protection();
emi_mng_get_gps_emi(pdev);
return 0;
}

15
drivers/misc/mediatek/connectivity/conninfra/platform/include/consys_hw.h
View file

@ -100,7 +100,7 @@ typedef int(*CONSYS_PLT_THERMAL_QUERY)(void);
typedef int(*CONSYS_PLT_ENABLE_POWER_DUMP)(void);
typedef int(*CONSYS_PLT_RESET_POWER_STATE)(void);
typedef int(*CONSYS_PLT_POWER_STATE)(char *buf, unsigned int size);
typedef int(*CONSYS_PLT_POWER_STATE)(void);
typedef void(*CONSYS_PLT_CONFIG_SETUP)(void);
@ -111,9 +111,6 @@ typedef unsigned int (*CONSYS_PLT_ADIE_DETECTION)(void);
typedef void (*CONSYS_PLT_SET_MCU_CONTROL)(int type, bool onoff);
typedef int (*CONSYS_PLT_PRE_CAL_BACKUP)(unsigned int offset, unsigned int size);
typedef int (*CONSYS_PLT_PRE_CAL_CLEAN_DATA)(void);
struct consys_hw_ops_struct {
/* load from dts */
CONSYS_PLT_CLK_GET_FROM_DTS consys_plt_clk_get_from_dts;
@ -178,9 +175,6 @@ struct consys_hw_ops_struct {
CONSYS_PLT_ADIE_DETECTION consys_plt_adie_detection;
CONSYS_PLT_SET_MCU_CONTROL consys_plt_set_mcu_control;
CONSYS_PLT_PRE_CAL_BACKUP consys_plt_pre_cal_backup;
CONSYS_PLT_PRE_CAL_CLEAN_DATA consys_plt_pre_cal_clean_data;
};
struct conninfra_dev_cb {
@ -278,7 +272,7 @@ void consys_hw_clock_fail_dump(void);
/* Low debug */
int consys_hw_enable_power_dump(void);
int consys_hw_reset_power_state(void);
int consys_hw_dump_power_state(char *buf, unsigned int size);
int consys_hw_dump_power_state(void);
void consys_hw_config_setup(void);
@ -302,11 +296,6 @@ int consys_hw_set_platform_config(int value);
int consys_hw_get_platform_config(void);
void consys_hw_set_mcu_control(int type, bool onoff);
/* Pre-cal */
int consys_hw_pre_cal_backup(unsigned int offset, unsigned int size);
int consys_hw_pre_cal_clean_data(void);
/*******************************************************************************
* F U N C T I O N S
********************************************************************************

5
drivers/misc/mediatek/connectivity/conninfra/platform/include/emi_mng.h
View file

@ -58,13 +58,10 @@ struct consys_emi_addr_info {
/* MCIF EMI get from MD */
phys_addr_t md_emi_phy_addr;
unsigned int md_emi_size;
/* GPS EMI */
phys_addr_t gps_emi_phy_addr;
unsigned int gps_emi_size;
};
typedef int(*CONSYS_IC_EMI_MPU_SET_REGION_PROTECTION) (void);
typedef unsigned int(*CONSYS_IC_EMI_SET_REMAPPING_REG) (phys_addr_t, phys_addr_t, phys_addr_t);
typedef unsigned int(*CONSYS_IC_EMI_SET_REMAPPING_REG) (phys_addr_t, phys_addr_t);
typedef void(*CONSYS_IC_EMI_GET_MD_SHARED_EMI) (phys_addr_t* phy_addr, unsigned int *size);
struct consys_platform_emi_ops {

1
drivers/misc/mediatek/connectivity/conninfra/platform/mt6877/include/CODA/conn_rgu.h
View file

@ -23,6 +23,7 @@
#define CONN_RGU_CO_EXT_MEM_HWCTL_PDN_ADDR (CONN_RGU_BASE + 0x070) // 0070
#define CONN_RGU_CO_EXT_MEM_HWCTL_SLP_ADDR (CONN_RGU_BASE + 0x074) // 0074
#define CONN_RGU_WFSYS_WA_WDT_EN_ADDR (CONN_RGU_BASE + 0x104) // 0104
#define CONN_RGU_DEBUG_SEL_ADDR (CONN_RGU_BASE + 0x204) // 0204
#define CONN_RGU_WFSYS_ON_TOP_PWR_ST_ADDR (CONN_RGU_BASE + 0x400) // 0400

2
drivers/misc/mediatek/connectivity/conninfra/platform/mt6877/include/mt6877_pos.h
View file

@ -8,7 +8,7 @@
#include <linux/types.h>
unsigned int consys_emi_set_remapping_reg_mt6877(phys_addr_t, phys_addr_t, phys_addr_t);
unsigned int consys_emi_set_remapping_reg_mt6877(phys_addr_t, phys_addr_t);
int consys_conninfra_on_power_ctrl_mt6877(unsigned int enable);
int consys_conninfra_wakeup_mt6877(void);

91
drivers/misc/mediatek/connectivity/conninfra/platform/mt6877/mt6877.c
View file

@ -14,13 +14,6 @@
#include <connectivity_build_in_adapter.h>
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
#include <oplus_conn_event.h>
#include <linux/string.h>
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
#include "osal.h"
#include "conninfra.h"
#include "conninfra_conf.h"
@ -66,11 +59,6 @@
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
static char mUevent[256] = {'\0'};
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
static int consys_clk_get_from_dts_mt6877(struct platform_device *pdev);
static int consys_clock_buffer_ctrl_mt6877(unsigned int enable);
static unsigned int consys_soc_chipid_get_mt6877(void);
@ -80,7 +68,7 @@ static int consys_thermal_query_mt6877(void);
/* Power state relative */
static int consys_enable_power_dump_mt6877(void);
static int consys_reset_power_state_mt6877(void);
static int consys_power_state_dump_mt6877(char *buf, unsigned int size);
static int consys_power_state_dump_mt6877(void);
static unsigned long long consys_soc_timestamp_get_mt6877(void);
@ -329,28 +317,15 @@ void consys_power_state(void)
}
}
pr_info("[%s] [0x%x] %s", __func__, r, buf);
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
snprintf(mUevent, sizeof(mUevent), "consys=power_state:%s;", buf);
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
}
int consys_power_state_dump_mt6877(char *buf, unsigned int size)
int consys_power_state_dump_mt6877(void)
{
unsigned int conninfra_sleep_cnt, conninfra_sleep_time;
unsigned int wf_sleep_cnt, wf_sleep_time;
unsigned int bt_sleep_cnt, bt_sleep_time;
unsigned int gps_sleep_cnt, gps_sleep_time;
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
static u64 t_conninfra_sleep_cnt = 0, t_conninfra_sleep_time = 0;
static u64 t_wf_sleep_cnt = 0, t_wf_sleep_time = 0;
static u64 t_bt_sleep_cnt = 0, t_bt_sleep_time = 0;
static u64 t_gps_sleep_cnt = 0, t_gps_sleep_time = 0;
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
/* Sleep count */
/* 1. Setup read select: 0x1806_0380[3:1]
@ -403,58 +378,8 @@ int consys_power_state_dump_mt6877(char *buf, unsigned int size)
bt_sleep_time, bt_sleep_cnt,
gps_sleep_time, gps_sleep_cnt);
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
memset(mUevent, '\0', sizeof(mUevent));
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
/* Power state */
consys_power_state();
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
#define CONN_32K_TICKS_PER_SEC (32768)
#define CONN_TICK_TO_SEC(TICK) (TICK / CONN_32K_TICKS_PER_SEC)
t_conninfra_sleep_time += conninfra_sleep_time;
t_conninfra_sleep_cnt += conninfra_sleep_cnt;
t_wf_sleep_time += wf_sleep_time;
t_wf_sleep_cnt += wf_sleep_cnt;
t_bt_sleep_time += bt_sleep_time;
t_bt_sleep_cnt += bt_sleep_cnt;
t_gps_sleep_time += gps_sleep_time;
t_gps_sleep_cnt += gps_sleep_cnt;
if (strlen(mUevent) > 0) {
snprintf(&(mUevent[strlen(mUevent)]), sizeof(mUevent)-strlen(mUevent),
"conninfra:%u.%03u,%u;wf:%u.%03u,%u;bt:%u.%03u,%u;gps:%u.%03u,%u;"
"[total]conninfra:%llu.%03llu,%llu;wf:%llu.%03llu,%llu;"
"bt:%llu.%03llu,%llu;gps:%llu.%03llu,%llu;",
CONN_TICK_TO_SEC(conninfra_sleep_time),
CONN_TICK_TO_SEC((conninfra_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
conninfra_sleep_cnt,
CONN_TICK_TO_SEC(wf_sleep_time),
CONN_TICK_TO_SEC((wf_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
wf_sleep_cnt,
CONN_TICK_TO_SEC(bt_sleep_time),
CONN_TICK_TO_SEC((bt_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
bt_sleep_cnt,
CONN_TICK_TO_SEC(gps_sleep_time),
CONN_TICK_TO_SEC((gps_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
gps_sleep_cnt,
CONN_TICK_TO_SEC(t_conninfra_sleep_time),
CONN_TICK_TO_SEC((t_conninfra_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_conninfra_sleep_cnt,
CONN_TICK_TO_SEC(t_wf_sleep_time),
CONN_TICK_TO_SEC((t_wf_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_wf_sleep_cnt,
CONN_TICK_TO_SEC(t_bt_sleep_time),
CONN_TICK_TO_SEC((t_bt_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_bt_sleep_cnt,
CONN_TICK_TO_SEC(t_gps_sleep_time),
CONN_TICK_TO_SEC((t_gps_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_gps_sleep_cnt);
oplusConnSendUevent(mUevent);
}
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
return 0;
}
@ -504,7 +429,8 @@ int consys_thermal_query_mt6877(void)
#define CONN_GPT2_CTRL_AP_EN 0x38
void __iomem *addr = NULL;
int cal_val, res = 0;
int cal_val;
static int res = 0;
/* Base: 0x1800_2000, CONN_TOP_THERM_CTL */
const unsigned int thermal_dump_crs[THERMAL_DUMP_NUM] = {
0x00, 0x04, 0x08, 0x0c,
@ -543,6 +469,15 @@ int consys_thermal_query_mt6877(void)
udelay(500);
/* get thermal value */
cal_val = CONSYS_REG_READ(CONN_THERM_CTL_THERMEN3_ADDR);
if (cal_val == 0xdeadfeed) {
pr_err("[%s] cal_val get 0xdeadfeed\n", __func__);
consys_reg_mng_is_bus_hang();
consys_sema_release_mt6877(CONN_SEMA_THERMAL_INDEX);
connsys_adie_top_ck_en_ctl_mt6877(false);
iounmap(addr);
return res;
}
cal_val = (cal_val >> 8) & 0x7f;
/* thermal debug dump */

59
drivers/misc/mediatek/connectivity/conninfra/platform/mt6877/mt6877_consys_reg.c
View file

@ -16,6 +16,8 @@
#define LOG_TMP_BUF_SZ 256
#define MT6877_DEBUG_SOP_VERSION "20230215"
static int consys_reg_init(struct platform_device *pdev);
static int consys_reg_deinit(void);
static int consys_check_reg_readable(void);
@ -198,7 +200,7 @@ static inline unsigned int __consys_bus_hang_clock_detect(void)
static void consys_bus_hang_dump_b(void)
{
unsigned int b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10;
unsigned int b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15;
unsigned int bus_clock, ip_version, irq_b, irq_vndr, irq_axi, irq_conninfra, wifi_irq;
/* B0 Read 0x180602C0
@ -234,21 +236,44 @@ static void consys_bus_hang_dump_b(void)
CONN_HOST_CSR_TOP_CONN_INFRA_CFG_DBG_SEL_CONN_INFRA_CFG_DBG_SEL, 0x6);
b4 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_DBG_DUMMY_2_ADDR);
/* B5 Read 0x180602CC
/*
* B5 ~ B8
* Write 0x1806015C[2:0], by 0x1, 0x4, 0x5, 0x7
* Read 0x180602C8
*/
b5 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_DBG_DUMMY_3_ADDR);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_CONN_INFRA_CFG_DBG_SEL_CONN_INFRA_CFG_DBG_SEL, 0x1);
b5 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_DBG_DUMMY_2_ADDR);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_CONN_INFRA_CFG_DBG_SEL_CONN_INFRA_CFG_DBG_SEL, 0x4);
b6 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_DBG_DUMMY_2_ADDR);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_CONN_INFRA_CFG_DBG_SEL_CONN_INFRA_CFG_DBG_SEL, 0x5);
b7 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_DBG_DUMMY_2_ADDR);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_CONN_INFRA_CFG_DBG_SEL_CONN_INFRA_CFG_DBG_SEL, 0x7);
b8 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_DBG_DUMMY_2_ADDR);
/* B6: 0x1806_01a0
* B7: 0x1806_01a4
* B8: 0x1806_01a8
* B9: 0x1806_01ac
* B10: 0x1806_01b0
/* B9 Read 0x180602CC
*/
b6 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_CONN_INFRA_WAKEPU_TOP_ADDR);
b7 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_CONN_INFRA_WAKEPU_WF_ADDR);
b8 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_CONN_INFRA_WAKEPU_BT_ADDR);
b9 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_CONN_INFRA_WAKEPU_GPS_ADDR);
b10 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_CONN_INFRA_WAKEPU_FM_ADDR);
b9 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_DBG_DUMMY_3_ADDR);
/* B10: 0x1806_01a0
* B11: 0x1806_01a4
* B12: 0x1806_01a8
* B13: 0x1806_01ac
* B14: 0x1806_01b0
*/
b10 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_CONN_INFRA_WAKEPU_TOP_ADDR);
b11 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_CONN_INFRA_WAKEPU_WF_ADDR);
b12 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_CONN_INFRA_WAKEPU_BT_ADDR);
b13 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_CONN_INFRA_WAKEPU_GPS_ADDR);
b14 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_CONN_INFRA_WAKEPU_FM_ADDR);
/* 2023/02/15
*/
b15 = CONSYS_REG_READ(CONN_HOST_CSR_TOP_DBG_DUMMY_4_ADDR);
/* On2Off check */
/* 2. Check conn_infra off bus clock
@ -275,9 +300,10 @@ static void consys_bus_hang_dump_b(void)
*/
wifi_irq = CONSYS_REG_READ_BIT(CONN_HOST_CSR_TOP_WF_MCUSY_VDNR_BUS_TIMOUT_ADDR, (0x1 << 0));
pr_info("[CONN_BUS_B][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x]",
b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10,
bus_clock, ip_version, irq_b, irq_vndr, irq_axi, irq_conninfra, wifi_irq);
pr_info("[CONN_BUS_B][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x][0x%08x]",
b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14,
bus_clock, ip_version, irq_b, irq_vndr, irq_axi, irq_conninfra, wifi_irq,
b15);
}
static void consys_bus_hang_dump_c(bool offclock)
@ -487,6 +513,7 @@ static int consys_is_bus_hang(void)
unsigned int ret = 0;
bool offclk_ok = true;
pr_info("[CONN_BUS] version=%s\n", MT6877_DEBUG_SOP_VERSION);
consys_bus_hang_dump_a();
/* AP2CONN_INFRA ON
* 1. Check ap2conn gals sleep protect status

46
drivers/misc/mediatek/connectivity/conninfra/platform/mt6877/mt6877_pmic.c
View file

@ -27,13 +27,6 @@
#include "mt6877_consys_reg_offset.h"
#include "mt6877_pos.h"
#ifdef OPLUS_BUG_STABILITY
//modify for vcn13/vs2
#include <soc/oplus/system/oplus_project.h>
extern int is_fan53870_pmic(void);
extern unsigned int is_project(int project);
#endif /* OPLUS_BUG_STABILITY */
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
@ -54,22 +47,11 @@ extern unsigned int is_project(int project);
* C O N S T A N T S
********************************************************************************
*/
#ifdef OPLUS_BUG_STABILITY
//mtk patch modify for vcn13/vs2
enum vcn13_state {
vcn13_1_3v = 0,
vcn13_1_32v = 1,
vcn13_1_33v = 2,
vcn13_1_37v = 3,
};
#else
enum vcn13_state {
vcn13_1_3v = 0,
vcn13_1_32v = 1,
vcn13_1_37v = 2,
};
#endif /* OPLUS_BUG_STABILITY */
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
@ -500,22 +482,7 @@ int consys_plt_pmic_raise_voltage_mt6877(unsigned int drv_type, bool raise, bool
return 0;
}
if (bt_raise) {
#ifdef OPLUS_BUG_STABILITY
//mtk patch modify for vcn13/vs2, minimize the negative effects.
unsigned int pcbversion = get_PCB_Version();
//1 = fan53870, otherwise is wl2868c
int isFan53870 = is_fan53870_pmic();
if (is_project(20181) && (pcbversion == 10) && (isFan53870 != 1)) {
pr_err("[%s] vcn13 = 1.33v\n", __func__);
next_state = vcn13_1_33v;
} else {
pr_err("[%s] vcn13 = 1.37v\n", __func__);
next_state = vcn13_1_37v;
}
#else
next_state = vcn13_1_37v;
#endif /* OPLUS_BUG_STABILITY*/
} else {
next_state = vcn13_1_3v;
}
@ -592,19 +559,6 @@ int consys_plt_pmic_raise_voltage_mt6877(unsigned int drv_type, bool raise, bool
KERNEL_pmic_set_register_value(PMIC_RG_VCN13_VOCAL, 0x2);
#endif
break;
#ifdef OPLUS_BUG_STABILITY
//mtk patch modify for vcn13/vs2
case vcn13_1_33v:
/* Set VS2 to 1.375V */
KERNEL_pmic_set_register_value(PMIC_RG_BUCK_VS2_VOSEL, 0x2E);
/* request VS2 to 1.375V by VS2 VOTER (use bit 4) */
KERNEL_pmic_set_register_value(PMIC_RG_BUCK_VS2_VOTER_EN_SET, 0x10);
/* Restore VS2 sleep voltage to 1.35V */
KERNEL_pmic_set_register_value(PMIC_RG_BUCK_VS2_VOSEL_SLEEP, 0x2C);
/* Set VCN13 to 1.33V */
KERNEL_pmic_set_register_value(PMIC_RG_VCN13_VOCAL, 0x3);
break;
#endif /* OPLUS_BUG_STABILITY*/
case vcn13_1_37v:
#if COMMON_KERNEL_PMIC_SUPPORT
/* Set VS2 to 1.4625V */

83
drivers/misc/mediatek/connectivity/conninfra/platform/mt6877/mt6877_pos.c
View file

@ -61,8 +61,7 @@ static int connsys_adie_clock_buffer_setting(bool bt_only);
unsigned int consys_emi_set_remapping_reg_mt6877(
phys_addr_t con_emi_base_addr,
phys_addr_t md_shared_emi_base_addr,
phys_addr_t gps_emi_base_addr)
phys_addr_t md_shared_emi_base_addr)
{
CONSYS_REG_WRITE_OFFSET_RANGE(
CONN_HOST_CSR_TOP_CONN2AP_REMAP_MCU_EMI_BASE_ADDR_ADDR,
@ -93,6 +92,78 @@ unsigned int consys_emi_set_remapping_reg_mt6877(
int consys_conninfra_on_power_ctrl_mt6877(unsigned int enable)
{
#if MTK_CONNINFRA_CLOCK_BUFFER_API_AVAILABLE
unsigned int conninfra_off_iso = 0;
int check;
if (enable)
return consys_platform_spm_conn_ctrl_mt6877(enable);
pr_info("%s[%d], check conninfra off iso before turn off MTCMOS\n", __func__, __LINE__);
/* Caser of Turn off MTCMOS */
/* read 0x1806_02CC */
conninfra_off_iso = CONSYS_REG_READ(CONN_HOST_CSR_TOP_DBG_DUMMY_3_ADDR);
if (((conninfra_off_iso & 0x10000) == 0) && ((conninfra_off_iso & 0x0F00) == 0)) {
/* Turn on AP2CONN AHB TX bus sleep protect */
/* 0x1000_1220[13] = 1 */
CONSYS_SET_BIT(INFRACFG_AO_INFRA_TOPAXI_PROTECTEN, 1 << 13);
/*
* check AP2CONN AHB TX bus sleep protect turn on
* (polling "100 times" and each polling interval is "0.5ms")
* If AP2CONN (TX/RX) protect turn off fail, power on fail.
* (DRV access connsys CR will get 0 )
*/
CONSYS_REG_BIT_POLLING(INFRACFG_AO_INFRA_TOPAXI_PROTECTEN_STA1, 13, 0x1, 100, 500, check);
if (check != 0) {
/* cannot get AHB TX bus sleep protect */
pr_info("%s[%d], cannot get AHB TX bus sleep protect\n", __func__, __LINE__);
return consys_platform_spm_conn_ctrl_mt6877(enable);
}
/* Turn on AP2CONN AHB RX bus sleep protect */
CONSYS_SET_BIT(INFRACFG_AO_INFRA_TOPAXI_PROTECTEN, 1 << 19);
/*
* check AP2CONN AHB RX bus sleep protect turn on
* (polling "100 times" and each polling interval is "0.5ms")
* If AP2CONN (TX/RX) protect turn off fail, power on fail.
* (DRV access connsys CR will get 0 )
*/
CONSYS_REG_BIT_POLLING(INFRACFG_AO_INFRA_TOPAXI_PROTECTEN_STA1, 19, 0x1, 100, 500, check);
if (check != 0) {
/* cannot get AHB RX bus sleep protect */
pr_info("%s[%d], cannot get AHB RX bus sleep protect\n", __func__, __LINE__);
return consys_platform_spm_conn_ctrl_mt6877(enable);
}
/*
* Turn on CONN2AP AXI TX bus sleep protect (disable sleep protection when CONNSYS had been turned on)
* Note : Should turn off AXI Tx sleep protection after AXI Rx sleep protection has been turn off.
*/
CONSYS_SET_BIT(INFRACFG_AO_INFRA_TOPAXI_PROTECTEN, 1 << 18);
pr_info("%s[%d], set AXI TX bus sleep protect here\n", __func__, __LINE__);
/*
* Turn on CONN2AP AXI RX bus sleep protect (disable sleep protection when CONNSYS had been turned on)
* Note : Should turn off AXI Rx sleep protection first.
*/
CONSYS_SET_BIT(INFRACFG_AO_INFRA_TOPAXI_PROTECTEN, 1 << 14);
/*
* check CONN2AP AXI RX bus sleep protect turn on
* (polling "100 times" and each polling interval is "0.5ms")
* If CONN2AP (TX/RX) protect turn off fail, power on fail.
* (DRV access connsys CR will get 0 )
*/
CONSYS_REG_BIT_POLLING(INFRACFG_AO_INFRA_TOPAXI_PROTECTEN_STA1, 14, 0x1, 100, 500, check);
if (check != 0) {
/* cannot get AXI RX bus sleep protect */
pr_info("%s[%d], cannot get AXI RX bus sleep protect\n", __func__, __LINE__);
return consys_platform_spm_conn_ctrl_mt6877(enable);
}
/* assert "conn_infra_on" isolation, set "connsys_iso_en"=1 */
/* 0x1000_6E04[1] = 1 */
CONSYS_SET_BIT(SPM_CONN_PWR_CON, 1 << 1);
}
return consys_platform_spm_conn_ctrl_mt6877(enable);
#else
int check;
@ -1541,6 +1612,14 @@ int connsys_low_power_setting_mt6877(unsigned int curr_status, unsigned int next
CONSYS_SET_BIT(CONN_CLKGEN_ON_TOP_CKGEN_BUS_ADDR, (0x1 << 26));
CONSYS_SET_BIT(CONN_CLKGEN_ON_TOP_CKGEN_BUS_ADDR, (0x1 << 27));
/* 0x1800_1200[9]=1b'1
*/
CONSYS_SET_BIT(CONN_CFG_CONN_INFRA_CFG_PWRCTRL0_ADDR, (0x1 << 9));
/* 2023/02/15 0x1800_0204 = 32h'6
*/
CONSYS_REG_WRITE(CONN_RGU_DEBUG_SEL_ADDR, 0x6);
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
/* !!!!!!!!!!!!!!!!!!!!!! CANNOT add code after HERE!!!!!!!!!!!!!!!!!!!!!!!!!! */
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */

4619
drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/CODA/conn_afe_ctl.h Normal file
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drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/CODA/conn_bus_cr.h Normal file
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drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/CODA/conn_bus_cr_on.h Normal file
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@ -0,0 +1,727 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
//[File] : conn_bus_cr_on.h
//[Revision time] : Wed Jun 23 22:20:55 2021
//[Description] : This file is auto generated by CODA
//[Copyright] : Copyright (C) 2021 Mediatek Incorportion. All rights reserved.
#ifndef __CONN_BUS_CR_ON_REGS_H__
#define __CONN_BUS_CR_ON_REGS_H__
//****************************************************************************
//
// CONN_BUS_CR_ON CR Definitions
//
//****************************************************************************
#define CONN_BUS_CR_ON_BASE (CONN_REG_CONN_INFRA_BUS_CR_ON_ADDR) // 0x1800E000
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_IDLE_CTRL_0_ADDR (CONN_BUS_CR_ON_BASE + 0x000) // E000
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_IDLE_CTRL_1_ADDR (CONN_BUS_CR_ON_BASE + 0x004) // E004
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_STATUS_ADDR (CONN_BUS_CR_ON_BASE + 0x020) // E020
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_ADDR (CONN_BUS_CR_ON_BASE + 0x024) // E024
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_0_ADDR (CONN_BUS_CR_ON_BASE + 0x028) // E028
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_1_ADDR (CONN_BUS_CR_ON_BASE + 0x02C) // E02C
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_2_ADDR (CONN_BUS_CR_ON_BASE + 0x030) // E030
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_STATUS_ADDR (CONN_BUS_CR_ON_BASE + 0x034) // E034
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_ADDR (CONN_BUS_CR_ON_BASE + 0x038) // E038
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_0_ADDR (CONN_BUS_CR_ON_BASE + 0x03C) // E03C
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_1_ADDR (CONN_BUS_CR_ON_BASE + 0x040) // E040
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_2_ADDR (CONN_BUS_CR_ON_BASE + 0x044) // E044
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_DOMAIN_ID_ADDR (CONN_BUS_CR_ON_BASE + 0x050) // E050
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_0_ADDR (CONN_BUS_CR_ON_BASE + 0x060) // E060
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_1_ADDR (CONN_BUS_CR_ON_BASE + 0x064) // E064
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_2_ADDR (CONN_BUS_CR_ON_BASE + 0x068) // E068
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_3_ADDR (CONN_BUS_CR_ON_BASE + 0x06C) // E06C
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_4_ADDR (CONN_BUS_CR_ON_BASE + 0x070) // E070
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_5_ADDR (CONN_BUS_CR_ON_BASE + 0x074) // E074
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_6_ADDR (CONN_BUS_CR_ON_BASE + 0x078) // E078
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_7_ADDR (CONN_BUS_CR_ON_BASE + 0x07C) // E07C
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_0_ADDR (CONN_BUS_CR_ON_BASE + 0x080) // E080
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_1_ADDR (CONN_BUS_CR_ON_BASE + 0x084) // E084
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_2_ADDR (CONN_BUS_CR_ON_BASE + 0x088) // E088
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_3_ADDR (CONN_BUS_CR_ON_BASE + 0x08C) // E08C
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_4_ADDR (CONN_BUS_CR_ON_BASE + 0x090) // E090
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_5_ADDR (CONN_BUS_CR_ON_BASE + 0x094) // E094
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_6_ADDR (CONN_BUS_CR_ON_BASE + 0x098) // E098
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_7_ADDR (CONN_BUS_CR_ON_BASE + 0x09C) // E09C
#define CONN_BUS_CR_ON_GALS_AP2CONN_CTRL_ADDR (CONN_BUS_CR_ON_BASE + 0x0B0) // E0B0
#define CONN_BUS_CR_ON_AP2CONN_GALS_RX_DBG_ADDR (CONN_BUS_CR_ON_BASE + 0x0B4) // E0B4
#define CONN_BUS_CR_ON_CONN_VON_BUS_DBG_ADDR (CONN_BUS_CR_ON_BASE + 0x0C0) // E0C0
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_ADDR (CONN_BUS_CR_ON_BASE + 0x100) // E100
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_ADDR (CONN_BUS_CR_ON_BASE + 0x104) // E104
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_CK_DCM_ADDR (CONN_BUS_CR_ON_BASE + 0x108) // E108
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_ADDR (CONN_BUS_CR_ON_BASE + 0x10C) // E10C
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR (CONN_BUS_CR_ON_BASE + 0x110) // E110
#define CONN_BUS_CR_ON_CONN_INFRA_APB_SLV_ACCESS_DETECT_EN_ADDR (CONN_BUS_CR_ON_BASE + 0x114) // E114
#define CONN_BUS_CR_ON_CONN_INFRA_CKSYS_CTRL_ADDR (CONN_BUS_CR_ON_BASE + 0x120) // E120
/* =====================================================================================
---CONN_INFRA_VON_BUS_IDLE_CTRL_0 (0x1800E000 + 0x000)---
VON_BUS_IDLE_MASK[15..0] - (RW) conn_infra von bus idle mask
RESERVED16[31..16] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_IDLE_CTRL_0_VON_BUS_IDLE_MASK_ADDR CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_IDLE_CTRL_0_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_IDLE_CTRL_0_VON_BUS_IDLE_MASK_MASK 0x0000FFFF // VON_BUS_IDLE_MASK[15..0]
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_IDLE_CTRL_0_VON_BUS_IDLE_MASK_SHFT 0
/* =====================================================================================
---CONN_INFRA_VON_BUS_IDLE_CTRL_1 (0x1800E000 + 0x004)---
VON_BUS_IDLE_DEBOUNCE[4..0] - (RW) conn_infra von bus idle debounce
RESERVED5[31..5] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_IDLE_CTRL_1_VON_BUS_IDLE_DEBOUNCE_ADDR CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_IDLE_CTRL_1_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_IDLE_CTRL_1_VON_BUS_IDLE_DEBOUNCE_MASK 0x0000001F // VON_BUS_IDLE_DEBOUNCE[4..0]
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_IDLE_CTRL_1_VON_BUS_IDLE_DEBOUNCE_SHFT 0
/* =====================================================================================
---CONN_INFRA_VON_BUS_TIMEOUT_STATUS (0x1800E000 + 0x020)---
TIMEOUT_STATUS[0] - (RO) conn_von_bus apb timeout
RESERVED1[31..1] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_STATUS_TIMEOUT_STATUS_ADDR CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_STATUS_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_STATUS_TIMEOUT_STATUS_MASK 0x00000001 // TIMEOUT_STATUS[0]
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_STATUS_TIMEOUT_STATUS_SHFT 0
/* =====================================================================================
---CONN_INFRA_VON_BUS_TIMEOUT_CTRL (0x1800E000 + 0x024)---
TIMEOUT_ENABLE[0] - (RW) 1'b1:conn_von_bus timeout function
TIMEOUT_CLEAR[1] - (RW) write 1'b0 after write 1'b1 to clear timeout information
FORCE_RESPONSE_HIGH[2] - (RW) force bus response ready high
TIMEOUT_TIME_SETTING[10..3] - (RW) timeout timming setting with free run clock counter
RESERVED11[31..11] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_TIMEOUT_TIME_SETTING_ADDR CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_TIMEOUT_TIME_SETTING_MASK 0x000007F8 // TIMEOUT_TIME_SETTING[10..3]
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_TIMEOUT_TIME_SETTING_SHFT 3
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_FORCE_RESPONSE_HIGH_ADDR CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_FORCE_RESPONSE_HIGH_MASK 0x00000004 // FORCE_RESPONSE_HIGH[2]
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_FORCE_RESPONSE_HIGH_SHFT 2
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_TIMEOUT_CLEAR_ADDR CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_TIMEOUT_CLEAR_MASK 0x00000002 // TIMEOUT_CLEAR[1]
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_TIMEOUT_CLEAR_SHFT 1
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_TIMEOUT_ENABLE_ADDR CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_TIMEOUT_ENABLE_MASK 0x00000001 // TIMEOUT_ENABLE[0]
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_TIMEOUT_ENABLE_SHFT 0
/* =====================================================================================
---CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_0 (0x1800E000 + 0x028)---
APB_TIMEOUT_INFO[31..0] - (RO) depends on timeout apb slave will mapping to different psel and pwrite information
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_0_APB_TIMEOUT_INFO_ADDR CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_0_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_0_APB_TIMEOUT_INFO_MASK 0xFFFFFFFF // APB_TIMEOUT_INFO[31..0]
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_0_APB_TIMEOUT_INFO_SHFT 0
/* =====================================================================================
---CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_1 (0x1800E000 + 0x02C)---
APB_TIMEOUT_ADDR[31..0] - (RO) timeout address
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_1_APB_TIMEOUT_ADDR_ADDR CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_1_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_1_APB_TIMEOUT_ADDR_MASK 0xFFFFFFFF // APB_TIMEOUT_ADDR[31..0]
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_1_APB_TIMEOUT_ADDR_SHFT 0
/* =====================================================================================
---CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_2 (0x1800E000 + 0x030)---
APB_TIMEOUT_WRITE_DATA[31..0] - (RO) timeout write data if write
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_2_APB_TIMEOUT_WRITE_DATA_ADDR CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_2_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_2_APB_TIMEOUT_WRITE_DATA_MASK 0xFFFFFFFF // APB_TIMEOUT_WRITE_DATA[31..0]
#define CONN_BUS_CR_ON_CONN_INFRA_VON_BUS_APB_TIMEOUT_INFO_2_APB_TIMEOUT_WRITE_DATA_SHFT 0
/* =====================================================================================
---CONN_INFRA_ON_BUS_TIMEOUT_STATUS (0x1800E000 + 0x034)---
TIMEOUT_STATUS[0] - (RO) conn_infra_on_bus apb timeout
RESERVED1[31..1] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_STATUS_TIMEOUT_STATUS_ADDR CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_STATUS_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_STATUS_TIMEOUT_STATUS_MASK 0x00000001 // TIMEOUT_STATUS[0]
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_STATUS_TIMEOUT_STATUS_SHFT 0
/* =====================================================================================
---CONN_INFRA_ON_BUS_TIMEOUT_CTRL (0x1800E000 + 0x038)---
TIMEOUT_ENABLE[0] - (RW) 1'b1:conn_infra_on_bus timeout function
TIMEOUT_CLEAR[1] - (RW) write 1'b0 after write 1'b1 to clear timeout information
FORCE_RESPONSE_HIGH[2] - (RW) force bus response ready high
TIMEOUT_TIME_SETTING[10..3] - (RW) timeout timming setting with free run clock counter
RESERVED11[31..11] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_TIMEOUT_TIME_SETTING_ADDR CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_TIMEOUT_TIME_SETTING_MASK 0x000007F8 // TIMEOUT_TIME_SETTING[10..3]
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_TIMEOUT_TIME_SETTING_SHFT 3
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_FORCE_RESPONSE_HIGH_ADDR CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_FORCE_RESPONSE_HIGH_MASK 0x00000004 // FORCE_RESPONSE_HIGH[2]
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_FORCE_RESPONSE_HIGH_SHFT 2
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_TIMEOUT_CLEAR_ADDR CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_TIMEOUT_CLEAR_MASK 0x00000002 // TIMEOUT_CLEAR[1]
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_TIMEOUT_CLEAR_SHFT 1
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_TIMEOUT_ENABLE_ADDR CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_TIMEOUT_ENABLE_MASK 0x00000001 // TIMEOUT_ENABLE[0]
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_TIMEOUT_ENABLE_SHFT 0
/* =====================================================================================
---CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_0 (0x1800E000 + 0x03C)---
APB_TIMEOUT_INFO[31..0] - (RO) depends on timeout apb slave will mapping to different psel and pwrite information
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_0_APB_TIMEOUT_INFO_ADDR CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_0_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_0_APB_TIMEOUT_INFO_MASK 0xFFFFFFFF // APB_TIMEOUT_INFO[31..0]
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_0_APB_TIMEOUT_INFO_SHFT 0
/* =====================================================================================
---CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_1 (0x1800E000 + 0x040)---
APB_TIMEOUT_ADDR[31..0] - (RO) timeout address
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_1_APB_TIMEOUT_ADDR_ADDR CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_1_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_1_APB_TIMEOUT_ADDR_MASK 0xFFFFFFFF // APB_TIMEOUT_ADDR[31..0]
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_1_APB_TIMEOUT_ADDR_SHFT 0
/* =====================================================================================
---CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_2 (0x1800E000 + 0x044)---
APB_TIMEOUT_WRITE_DATA[31..0] - (RO) timeout write data if write
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_2_APB_TIMEOUT_WRITE_DATA_ADDR CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_2_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_2_APB_TIMEOUT_WRITE_DATA_MASK 0xFFFFFFFF // APB_TIMEOUT_WRITE_DATA[31..0]
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_2_APB_TIMEOUT_WRITE_DATA_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_DOMAIN_ID (0x1800E000 + 0x050)---
R_PCIE2AP_REMAP_DOMAIN_ID[3..0] - (RW) xxx
RESERVED4[31..4] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_DOMAIN_ID_R_PCIE2AP_REMAP_DOMAIN_ID_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_DOMAIN_ID_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_DOMAIN_ID_R_PCIE2AP_REMAP_DOMAIN_ID_MASK 0x0000000F // R_PCIE2AP_REMAP_DOMAIN_ID[3..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_DOMAIN_ID_R_PCIE2AP_REMAP_DOMAIN_ID_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_0 (0x1800E000 + 0x060)---
R_PCIE2AP_PUBLIC_REMAPPING_0[15..0] - (RW) xxx
R_PCIE2AP_PUBLIC_REMAPPING_1[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_0_R_PCIE2AP_PUBLIC_REMAPPING_1_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_0_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_0_R_PCIE2AP_PUBLIC_REMAPPING_1_MASK 0xFFFF0000 // R_PCIE2AP_PUBLIC_REMAPPING_1[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_0_R_PCIE2AP_PUBLIC_REMAPPING_1_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_0_R_PCIE2AP_PUBLIC_REMAPPING_0_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_0_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_0_R_PCIE2AP_PUBLIC_REMAPPING_0_MASK 0x0000FFFF // R_PCIE2AP_PUBLIC_REMAPPING_0[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_0_R_PCIE2AP_PUBLIC_REMAPPING_0_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_1 (0x1800E000 + 0x064)---
R_PCIE2AP_PUBLIC_REMAPPING_2[15..0] - (RW) xxx
R_PCIE2AP_PUBLIC_REMAPPING_3[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_1_R_PCIE2AP_PUBLIC_REMAPPING_3_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_1_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_1_R_PCIE2AP_PUBLIC_REMAPPING_3_MASK 0xFFFF0000 // R_PCIE2AP_PUBLIC_REMAPPING_3[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_1_R_PCIE2AP_PUBLIC_REMAPPING_3_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_1_R_PCIE2AP_PUBLIC_REMAPPING_2_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_1_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_1_R_PCIE2AP_PUBLIC_REMAPPING_2_MASK 0x0000FFFF // R_PCIE2AP_PUBLIC_REMAPPING_2[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_1_R_PCIE2AP_PUBLIC_REMAPPING_2_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_2 (0x1800E000 + 0x068)---
R_PCIE2AP_PUBLIC_REMAPPING_4[15..0] - (RW) xxx
R_PCIE2AP_PUBLIC_REMAPPING_5[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_2_R_PCIE2AP_PUBLIC_REMAPPING_5_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_2_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_2_R_PCIE2AP_PUBLIC_REMAPPING_5_MASK 0xFFFF0000 // R_PCIE2AP_PUBLIC_REMAPPING_5[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_2_R_PCIE2AP_PUBLIC_REMAPPING_5_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_2_R_PCIE2AP_PUBLIC_REMAPPING_4_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_2_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_2_R_PCIE2AP_PUBLIC_REMAPPING_4_MASK 0x0000FFFF // R_PCIE2AP_PUBLIC_REMAPPING_4[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_2_R_PCIE2AP_PUBLIC_REMAPPING_4_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_3 (0x1800E000 + 0x06C)---
R_PCIE2AP_PUBLIC_REMAPPING_6[15..0] - (RW) xxx
R_PCIE2AP_PUBLIC_REMAPPING_7[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_3_R_PCIE2AP_PUBLIC_REMAPPING_7_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_3_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_3_R_PCIE2AP_PUBLIC_REMAPPING_7_MASK 0xFFFF0000 // R_PCIE2AP_PUBLIC_REMAPPING_7[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_3_R_PCIE2AP_PUBLIC_REMAPPING_7_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_3_R_PCIE2AP_PUBLIC_REMAPPING_6_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_3_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_3_R_PCIE2AP_PUBLIC_REMAPPING_6_MASK 0x0000FFFF // R_PCIE2AP_PUBLIC_REMAPPING_6[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_3_R_PCIE2AP_PUBLIC_REMAPPING_6_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_4 (0x1800E000 + 0x070)---
R_PCIE2AP_PUBLIC_REMAPPING_8[15..0] - (RW) xxx
R_PCIE2AP_PUBLIC_REMAPPING_9[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_4_R_PCIE2AP_PUBLIC_REMAPPING_9_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_4_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_4_R_PCIE2AP_PUBLIC_REMAPPING_9_MASK 0xFFFF0000 // R_PCIE2AP_PUBLIC_REMAPPING_9[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_4_R_PCIE2AP_PUBLIC_REMAPPING_9_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_4_R_PCIE2AP_PUBLIC_REMAPPING_8_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_4_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_4_R_PCIE2AP_PUBLIC_REMAPPING_8_MASK 0x0000FFFF // R_PCIE2AP_PUBLIC_REMAPPING_8[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_4_R_PCIE2AP_PUBLIC_REMAPPING_8_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_5 (0x1800E000 + 0x074)---
R_PCIE2AP_PUBLIC_REMAPPING_A[15..0] - (RW) xxx
R_PCIE2AP_PUBLIC_REMAPPING_B[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_5_R_PCIE2AP_PUBLIC_REMAPPING_B_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_5_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_5_R_PCIE2AP_PUBLIC_REMAPPING_B_MASK 0xFFFF0000 // R_PCIE2AP_PUBLIC_REMAPPING_B[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_5_R_PCIE2AP_PUBLIC_REMAPPING_B_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_5_R_PCIE2AP_PUBLIC_REMAPPING_A_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_5_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_5_R_PCIE2AP_PUBLIC_REMAPPING_A_MASK 0x0000FFFF // R_PCIE2AP_PUBLIC_REMAPPING_A[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_5_R_PCIE2AP_PUBLIC_REMAPPING_A_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_6 (0x1800E000 + 0x078)---
R_PCIE2AP_PUBLIC_REMAPPING_C[15..0] - (RW) xxx
R_PCIE2AP_PUBLIC_REMAPPING_D[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_6_R_PCIE2AP_PUBLIC_REMAPPING_D_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_6_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_6_R_PCIE2AP_PUBLIC_REMAPPING_D_MASK 0xFFFF0000 // R_PCIE2AP_PUBLIC_REMAPPING_D[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_6_R_PCIE2AP_PUBLIC_REMAPPING_D_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_6_R_PCIE2AP_PUBLIC_REMAPPING_C_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_6_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_6_R_PCIE2AP_PUBLIC_REMAPPING_C_MASK 0x0000FFFF // R_PCIE2AP_PUBLIC_REMAPPING_C[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_6_R_PCIE2AP_PUBLIC_REMAPPING_C_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_7 (0x1800E000 + 0x07C)---
R_PCIE2AP_PUBLIC_REMAPPING_E[15..0] - (RW) xxx
R_PCIE2AP_PUBLIC_REMAPPING_F[31..16] - (RO) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_7_R_PCIE2AP_PUBLIC_REMAPPING_F_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_7_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_7_R_PCIE2AP_PUBLIC_REMAPPING_F_MASK 0xFFFF0000 // R_PCIE2AP_PUBLIC_REMAPPING_F[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_7_R_PCIE2AP_PUBLIC_REMAPPING_F_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_7_R_PCIE2AP_PUBLIC_REMAPPING_E_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_7_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_7_R_PCIE2AP_PUBLIC_REMAPPING_E_MASK 0x0000FFFF // R_PCIE2AP_PUBLIC_REMAPPING_E[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_7_R_PCIE2AP_PUBLIC_REMAPPING_E_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_BT_0 (0x1800E000 + 0x080)---
R_PCIE2AP_BT_PUBLIC_REMAPPING_0[15..0] - (RW) xxx
R_PCIE2AP_BT_PUBLIC_REMAPPING_1[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_0_R_PCIE2AP_BT_PUBLIC_REMAPPING_1_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_0_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_0_R_PCIE2AP_BT_PUBLIC_REMAPPING_1_MASK 0xFFFF0000 // R_PCIE2AP_BT_PUBLIC_REMAPPING_1[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_0_R_PCIE2AP_BT_PUBLIC_REMAPPING_1_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_0_R_PCIE2AP_BT_PUBLIC_REMAPPING_0_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_0_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_0_R_PCIE2AP_BT_PUBLIC_REMAPPING_0_MASK 0x0000FFFF // R_PCIE2AP_BT_PUBLIC_REMAPPING_0[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_0_R_PCIE2AP_BT_PUBLIC_REMAPPING_0_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_BT_1 (0x1800E000 + 0x084)---
R_PCIE2AP_BT_PUBLIC_REMAPPING_2[15..0] - (RW) xxx
R_PCIE2AP_BT_PUBLIC_REMAPPING_3[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_1_R_PCIE2AP_BT_PUBLIC_REMAPPING_3_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_1_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_1_R_PCIE2AP_BT_PUBLIC_REMAPPING_3_MASK 0xFFFF0000 // R_PCIE2AP_BT_PUBLIC_REMAPPING_3[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_1_R_PCIE2AP_BT_PUBLIC_REMAPPING_3_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_1_R_PCIE2AP_BT_PUBLIC_REMAPPING_2_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_1_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_1_R_PCIE2AP_BT_PUBLIC_REMAPPING_2_MASK 0x0000FFFF // R_PCIE2AP_BT_PUBLIC_REMAPPING_2[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_1_R_PCIE2AP_BT_PUBLIC_REMAPPING_2_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_BT_2 (0x1800E000 + 0x088)---
R_PCIE2AP_BT_PUBLIC_REMAPPING_4[15..0] - (RW) xxx
R_PCIE2AP_BT_PUBLIC_REMAPPING_5[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_2_R_PCIE2AP_BT_PUBLIC_REMAPPING_5_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_2_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_2_R_PCIE2AP_BT_PUBLIC_REMAPPING_5_MASK 0xFFFF0000 // R_PCIE2AP_BT_PUBLIC_REMAPPING_5[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_2_R_PCIE2AP_BT_PUBLIC_REMAPPING_5_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_2_R_PCIE2AP_BT_PUBLIC_REMAPPING_4_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_2_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_2_R_PCIE2AP_BT_PUBLIC_REMAPPING_4_MASK 0x0000FFFF // R_PCIE2AP_BT_PUBLIC_REMAPPING_4[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_2_R_PCIE2AP_BT_PUBLIC_REMAPPING_4_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_BT_3 (0x1800E000 + 0x08C)---
R_PCIE2AP_BT_PUBLIC_REMAPPING_6[15..0] - (RW) xxx
R_PCIE2AP_BT_PUBLIC_REMAPPING_7[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_3_R_PCIE2AP_BT_PUBLIC_REMAPPING_7_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_3_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_3_R_PCIE2AP_BT_PUBLIC_REMAPPING_7_MASK 0xFFFF0000 // R_PCIE2AP_BT_PUBLIC_REMAPPING_7[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_3_R_PCIE2AP_BT_PUBLIC_REMAPPING_7_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_3_R_PCIE2AP_BT_PUBLIC_REMAPPING_6_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_3_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_3_R_PCIE2AP_BT_PUBLIC_REMAPPING_6_MASK 0x0000FFFF // R_PCIE2AP_BT_PUBLIC_REMAPPING_6[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_3_R_PCIE2AP_BT_PUBLIC_REMAPPING_6_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_BT_4 (0x1800E000 + 0x090)---
R_PCIE2AP_BT_PUBLIC_REMAPPING_8[15..0] - (RW) xxx
R_PCIE2AP_BT_PUBLIC_REMAPPING_9[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_4_R_PCIE2AP_BT_PUBLIC_REMAPPING_9_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_4_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_4_R_PCIE2AP_BT_PUBLIC_REMAPPING_9_MASK 0xFFFF0000 // R_PCIE2AP_BT_PUBLIC_REMAPPING_9[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_4_R_PCIE2AP_BT_PUBLIC_REMAPPING_9_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_4_R_PCIE2AP_BT_PUBLIC_REMAPPING_8_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_4_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_4_R_PCIE2AP_BT_PUBLIC_REMAPPING_8_MASK 0x0000FFFF // R_PCIE2AP_BT_PUBLIC_REMAPPING_8[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_4_R_PCIE2AP_BT_PUBLIC_REMAPPING_8_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_BT_5 (0x1800E000 + 0x094)---
R_PCIE2AP_BT_PUBLIC_REMAPPING_A[15..0] - (RW) xxx
R_PCIE2AP_BT_PUBLIC_REMAPPING_B[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_5_R_PCIE2AP_BT_PUBLIC_REMAPPING_B_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_5_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_5_R_PCIE2AP_BT_PUBLIC_REMAPPING_B_MASK 0xFFFF0000 // R_PCIE2AP_BT_PUBLIC_REMAPPING_B[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_5_R_PCIE2AP_BT_PUBLIC_REMAPPING_B_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_5_R_PCIE2AP_BT_PUBLIC_REMAPPING_A_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_5_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_5_R_PCIE2AP_BT_PUBLIC_REMAPPING_A_MASK 0x0000FFFF // R_PCIE2AP_BT_PUBLIC_REMAPPING_A[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_5_R_PCIE2AP_BT_PUBLIC_REMAPPING_A_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_BT_6 (0x1800E000 + 0x098)---
R_PCIE2AP_BT_PUBLIC_REMAPPING_C[15..0] - (RW) xxx
R_PCIE2AP_BT_PUBLIC_REMAPPING_D[31..16] - (RW) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_6_R_PCIE2AP_BT_PUBLIC_REMAPPING_D_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_6_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_6_R_PCIE2AP_BT_PUBLIC_REMAPPING_D_MASK 0xFFFF0000 // R_PCIE2AP_BT_PUBLIC_REMAPPING_D[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_6_R_PCIE2AP_BT_PUBLIC_REMAPPING_D_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_6_R_PCIE2AP_BT_PUBLIC_REMAPPING_C_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_6_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_6_R_PCIE2AP_BT_PUBLIC_REMAPPING_C_MASK 0x0000FFFF // R_PCIE2AP_BT_PUBLIC_REMAPPING_C[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_6_R_PCIE2AP_BT_PUBLIC_REMAPPING_C_SHFT 0
/* =====================================================================================
---PCIE2AP_REMAP_BT_7 (0x1800E000 + 0x09C)---
R_PCIE2AP_BT_PUBLIC_REMAPPING_E[15..0] - (RW) xxx
R_PCIE2AP_BT_PUBLIC_REMAPPING_F[31..16] - (RO) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_7_R_PCIE2AP_BT_PUBLIC_REMAPPING_F_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_7_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_7_R_PCIE2AP_BT_PUBLIC_REMAPPING_F_MASK 0xFFFF0000 // R_PCIE2AP_BT_PUBLIC_REMAPPING_F[31..16]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_7_R_PCIE2AP_BT_PUBLIC_REMAPPING_F_SHFT 16
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_7_R_PCIE2AP_BT_PUBLIC_REMAPPING_E_ADDR CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_7_ADDR
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_7_R_PCIE2AP_BT_PUBLIC_REMAPPING_E_MASK 0x0000FFFF // R_PCIE2AP_BT_PUBLIC_REMAPPING_E[15..0]
#define CONN_BUS_CR_ON_PCIE2AP_REMAP_BT_7_R_PCIE2AP_BT_PUBLIC_REMAPPING_E_SHFT 0
/* =====================================================================================
---GALS_AP2CONN_CTRL (0x1800E000 + 0x0B0)---
RG_AFIFO_SYNC_SEL[1..0] - (RW) xxx
RESERVED2[31..2] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_GALS_AP2CONN_CTRL_RG_AFIFO_SYNC_SEL_ADDR CONN_BUS_CR_ON_GALS_AP2CONN_CTRL_ADDR
#define CONN_BUS_CR_ON_GALS_AP2CONN_CTRL_RG_AFIFO_SYNC_SEL_MASK 0x00000003 // RG_AFIFO_SYNC_SEL[1..0]
#define CONN_BUS_CR_ON_GALS_AP2CONN_CTRL_RG_AFIFO_SYNC_SEL_SHFT 0
/* =====================================================================================
---AP2CONN_GALS_RX_DBG (0x1800E000 + 0x0B4)---
DBG_INFO[31..0] - (RO) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_AP2CONN_GALS_RX_DBG_DBG_INFO_ADDR CONN_BUS_CR_ON_AP2CONN_GALS_RX_DBG_ADDR
#define CONN_BUS_CR_ON_AP2CONN_GALS_RX_DBG_DBG_INFO_MASK 0xFFFFFFFF // DBG_INFO[31..0]
#define CONN_BUS_CR_ON_AP2CONN_GALS_RX_DBG_DBG_INFO_SHFT 0
/* =====================================================================================
---CONN_VON_BUS_DBG (0x1800E000 + 0x0C0)---
DBG_INFO[31..0] - (RO) xxx
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_VON_BUS_DBG_DBG_INFO_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DBG_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DBG_DBG_INFO_MASK 0xFFFFFFFF // DBG_INFO[31..0]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DBG_DBG_INFO_SHFT 0
/* =====================================================================================
---CONN_VON_BUS_DCM_CTL_0 (0x1800E000 + 0x100)---
HCLK_SC_AXI_DCM_DIS[0] - (RW) xxx
HCLK_CK_RDY_ON_DCM[1] - (RO) xxx
HCLK_CK_DCM_IDLE[2] - (RO) xxx
HCLK_DEBOUNCE_EN[3] - (RW) xxx
HCLK_DEBOUNCE_NUM[15..4] - (RW) xxx
RESERVED16[31..16] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_DEBOUNCE_NUM_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_DEBOUNCE_NUM_MASK 0x0000FFF0 // HCLK_DEBOUNCE_NUM[15..4]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_DEBOUNCE_NUM_SHFT 4
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_DEBOUNCE_EN_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_DEBOUNCE_EN_MASK 0x00000008 // HCLK_DEBOUNCE_EN[3]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_DEBOUNCE_EN_SHFT 3
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_CK_DCM_IDLE_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_CK_DCM_IDLE_MASK 0x00000004 // HCLK_CK_DCM_IDLE[2]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_CK_DCM_IDLE_SHFT 2
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_CK_RDY_ON_DCM_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_CK_RDY_ON_DCM_MASK 0x00000002 // HCLK_CK_RDY_ON_DCM[1]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_CK_RDY_ON_DCM_SHFT 1
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_SC_AXI_DCM_DIS_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_SC_AXI_DCM_DIS_MASK 0x00000001 // HCLK_SC_AXI_DCM_DIS[0]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_0_HCLK_SC_AXI_DCM_DIS_SHFT 0
/* =====================================================================================
---CONN_VON_BUS_DCM_CTL_1 (0x1800E000 + 0x104)---
IDLE_CK_DCM_LEVEL_SEL[4..0] - (RW) xxx
BUSY_CK_DCM_LEVEL_SEL[9..5] - (RW) xxx
FORCE_FREE_RUN[10] - (RW) xxx
FORCE_SLOW[11] - (RW) xxx
FORCE_OFF[12] - (RW) xxx
SLOW_MODE_ENABLE[13] - (RW) xxx
OFF_MODE_ENABLE[14] - (RW) xxx
CK_RDY_ON_DCM[15] - (RW) xxx
PLL_SEL_NO_SPM[16] - (RW) xxx
SC_AXI_DCM_DIS_EN[17] - (RW) xxx
RESERVED18[31..18] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_SC_AXI_DCM_DIS_EN_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_SC_AXI_DCM_DIS_EN_MASK 0x00020000 // SC_AXI_DCM_DIS_EN[17]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_SC_AXI_DCM_DIS_EN_SHFT 17
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_PLL_SEL_NO_SPM_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_PLL_SEL_NO_SPM_MASK 0x00010000 // PLL_SEL_NO_SPM[16]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_PLL_SEL_NO_SPM_SHFT 16
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_CK_RDY_ON_DCM_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_CK_RDY_ON_DCM_MASK 0x00008000 // CK_RDY_ON_DCM[15]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_CK_RDY_ON_DCM_SHFT 15
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_OFF_MODE_ENABLE_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_OFF_MODE_ENABLE_MASK 0x00004000 // OFF_MODE_ENABLE[14]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_OFF_MODE_ENABLE_SHFT 14
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_SLOW_MODE_ENABLE_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_SLOW_MODE_ENABLE_MASK 0x00002000 // SLOW_MODE_ENABLE[13]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_SLOW_MODE_ENABLE_SHFT 13
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_FORCE_OFF_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_FORCE_OFF_MASK 0x00001000 // FORCE_OFF[12]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_FORCE_OFF_SHFT 12
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_FORCE_SLOW_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_FORCE_SLOW_MASK 0x00000800 // FORCE_SLOW[11]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_FORCE_SLOW_SHFT 11
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_FORCE_FREE_RUN_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_FORCE_FREE_RUN_MASK 0x00000400 // FORCE_FREE_RUN[10]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_FORCE_FREE_RUN_SHFT 10
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_BUSY_CK_DCM_LEVEL_SEL_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_BUSY_CK_DCM_LEVEL_SEL_MASK 0x000003E0 // BUSY_CK_DCM_LEVEL_SEL[9..5]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_BUSY_CK_DCM_LEVEL_SEL_SHFT 5
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_IDLE_CK_DCM_LEVEL_SEL_ADDR CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_IDLE_CK_DCM_LEVEL_SEL_MASK 0x0000001F // IDLE_CK_DCM_LEVEL_SEL[4..0]
#define CONN_BUS_CR_ON_CONN_VON_BUS_DCM_CTL_1_IDLE_CK_DCM_LEVEL_SEL_SHFT 0
/* =====================================================================================
---CONN_INFRA_ON_BUS_CK_DCM (0x1800E000 + 0x108)---
OSC_CK_FR_EN[0] - (RW) xxx
HOST_OSC_CK_FR_EN[1] - (RW) xxx
RESERVED2[31..2] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_CK_DCM_HOST_OSC_CK_FR_EN_ADDR CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_CK_DCM_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_CK_DCM_HOST_OSC_CK_FR_EN_MASK 0x00000002 // HOST_OSC_CK_FR_EN[1]
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_CK_DCM_HOST_OSC_CK_FR_EN_SHFT 1
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_CK_DCM_OSC_CK_FR_EN_ADDR CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_CK_DCM_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_CK_DCM_OSC_CK_FR_EN_MASK 0x00000001 // OSC_CK_FR_EN[0]
#define CONN_BUS_CR_ON_CONN_INFRA_ON_BUS_CK_DCM_OSC_CK_FR_EN_SHFT 0
/* =====================================================================================
---CONN_OFF_BUS_DCM_CTL_0 (0x1800E000 + 0x10C)---
HCLK_SC_AXI_DCM_DIS[0] - (RW) xxx
HCLK_CK_RDY_ON_DCM[1] - (RO) xxx
HCLK_CK_DCM_IDLE[2] - (RO) xxx
HCLK_DEBOUNCE_EN[3] - (RW) xxx
HCLK_DEBOUNCE_NUM[15..4] - (RW) xxx
RESERVED16[31..16] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_DEBOUNCE_NUM_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_DEBOUNCE_NUM_MASK 0x0000FFF0 // HCLK_DEBOUNCE_NUM[15..4]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_DEBOUNCE_NUM_SHFT 4
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_DEBOUNCE_EN_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_DEBOUNCE_EN_MASK 0x00000008 // HCLK_DEBOUNCE_EN[3]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_DEBOUNCE_EN_SHFT 3
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_CK_DCM_IDLE_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_CK_DCM_IDLE_MASK 0x00000004 // HCLK_CK_DCM_IDLE[2]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_CK_DCM_IDLE_SHFT 2
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_CK_RDY_ON_DCM_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_CK_RDY_ON_DCM_MASK 0x00000002 // HCLK_CK_RDY_ON_DCM[1]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_CK_RDY_ON_DCM_SHFT 1
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_SC_AXI_DCM_DIS_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_SC_AXI_DCM_DIS_MASK 0x00000001 // HCLK_SC_AXI_DCM_DIS[0]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_0_HCLK_SC_AXI_DCM_DIS_SHFT 0
/* =====================================================================================
---CONN_OFF_BUS_DCM_CTL_1 (0x1800E000 + 0x110)---
IDLE_CK_DCM_LEVEL_SEL[4..0] - (RW) xxx
BUSY_CK_DCM_LEVEL_SEL[9..5] - (RW) xxx
FORCE_FREE_RUN[10] - (RW) xxx
FORCE_SLOW[11] - (RW) xxx
FORCE_OFF[12] - (RW) xxx
SLOW_MODE_ENABLE[13] - (RW) xxx
OFF_MODE_ENABLE[14] - (RW) xxx
CK_RDY_ON_DCM[15] - (RW) xxx
PLL_SEL_NO_SPM[16] - (RW) xxx
SC_AXI_DCM_DIS_EN[17] - (RW) xxx
OSC_CK_FR_EN[18] - (RW) xxx
MASK_OFF_OSC_FR_EN_CTRL[19] - (RW) 1'b0:mask off control
MASK_OFF_DOMAIN_OFF_MODE_ENABLE_CTRL[20] - (RW) 1'b1:mask off control
MASK_OFF_DOMAIN_SLOW_MODE_ENABLE_CTRL[21] - (RW) 1'b1:mask off control
RESERVED22[31..22] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_MASK_OFF_DOMAIN_SLOW_MODE_ENABLE_CTRL_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_MASK_OFF_DOMAIN_SLOW_MODE_ENABLE_CTRL_MASK 0x00200000 // MASK_OFF_DOMAIN_SLOW_MODE_ENABLE_CTRL[21]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_MASK_OFF_DOMAIN_SLOW_MODE_ENABLE_CTRL_SHFT 21
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_MASK_OFF_DOMAIN_OFF_MODE_ENABLE_CTRL_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_MASK_OFF_DOMAIN_OFF_MODE_ENABLE_CTRL_MASK 0x00100000 // MASK_OFF_DOMAIN_OFF_MODE_ENABLE_CTRL[20]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_MASK_OFF_DOMAIN_OFF_MODE_ENABLE_CTRL_SHFT 20
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_MASK_OFF_OSC_FR_EN_CTRL_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_MASK_OFF_OSC_FR_EN_CTRL_MASK 0x00080000 // MASK_OFF_OSC_FR_EN_CTRL[19]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_MASK_OFF_OSC_FR_EN_CTRL_SHFT 19
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_OSC_CK_FR_EN_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_OSC_CK_FR_EN_MASK 0x00040000 // OSC_CK_FR_EN[18]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_OSC_CK_FR_EN_SHFT 18
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_SC_AXI_DCM_DIS_EN_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_SC_AXI_DCM_DIS_EN_MASK 0x00020000 // SC_AXI_DCM_DIS_EN[17]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_SC_AXI_DCM_DIS_EN_SHFT 17
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_PLL_SEL_NO_SPM_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_PLL_SEL_NO_SPM_MASK 0x00010000 // PLL_SEL_NO_SPM[16]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_PLL_SEL_NO_SPM_SHFT 16
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_CK_RDY_ON_DCM_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_CK_RDY_ON_DCM_MASK 0x00008000 // CK_RDY_ON_DCM[15]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_CK_RDY_ON_DCM_SHFT 15
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_OFF_MODE_ENABLE_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_OFF_MODE_ENABLE_MASK 0x00004000 // OFF_MODE_ENABLE[14]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_OFF_MODE_ENABLE_SHFT 14
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_SLOW_MODE_ENABLE_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_SLOW_MODE_ENABLE_MASK 0x00002000 // SLOW_MODE_ENABLE[13]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_SLOW_MODE_ENABLE_SHFT 13
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_FORCE_OFF_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_FORCE_OFF_MASK 0x00001000 // FORCE_OFF[12]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_FORCE_OFF_SHFT 12
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_FORCE_SLOW_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_FORCE_SLOW_MASK 0x00000800 // FORCE_SLOW[11]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_FORCE_SLOW_SHFT 11
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_FORCE_FREE_RUN_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_FORCE_FREE_RUN_MASK 0x00000400 // FORCE_FREE_RUN[10]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_FORCE_FREE_RUN_SHFT 10
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_BUSY_CK_DCM_LEVEL_SEL_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_BUSY_CK_DCM_LEVEL_SEL_MASK 0x000003E0 // BUSY_CK_DCM_LEVEL_SEL[9..5]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_BUSY_CK_DCM_LEVEL_SEL_SHFT 5
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_IDLE_CK_DCM_LEVEL_SEL_ADDR CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_ADDR
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_IDLE_CK_DCM_LEVEL_SEL_MASK 0x0000001F // IDLE_CK_DCM_LEVEL_SEL[4..0]
#define CONN_BUS_CR_ON_CONN_OFF_BUS_DCM_CTL_1_IDLE_CK_DCM_LEVEL_SEL_SHFT 0
/* =====================================================================================
---CONN_INFRA_APB_SLV_ACCESS_DETECT_EN (0x1800E000 + 0x114)---
CONN_INFRA_APB_SLV_ACCESS_DETECT_EN[0] - (WO) SW path for enable conn_infra off apb slave access detect function
RESERVED1[31..1] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_APB_SLV_ACCESS_DETECT_EN_CONN_INFRA_APB_SLV_ACCESS_DETECT_EN_ADDR CONN_BUS_CR_ON_CONN_INFRA_APB_SLV_ACCESS_DETECT_EN_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_APB_SLV_ACCESS_DETECT_EN_CONN_INFRA_APB_SLV_ACCESS_DETECT_EN_MASK 0x00000001 // CONN_INFRA_APB_SLV_ACCESS_DETECT_EN[0]
#define CONN_BUS_CR_ON_CONN_INFRA_APB_SLV_ACCESS_DETECT_EN_CONN_INFRA_APB_SLV_ACCESS_DETECT_EN_SHFT 0
/* =====================================================================================
---CONN_INFRA_CKSYS_CTRL (0x1800E000 + 0x120)---
CKSYS_CK_REQ_HW_MODE[0] - (RW) set connsys to cksys host ck request hw mode control by bus status
CKSYS_CK_REQ_SW_EN[1] - (RW) sw setting for cksys host ck request if not hw mode
RESERVED2[31..2] - (RO) Reserved bits
=====================================================================================*/
#define CONN_BUS_CR_ON_CONN_INFRA_CKSYS_CTRL_CKSYS_CK_REQ_SW_EN_ADDR CONN_BUS_CR_ON_CONN_INFRA_CKSYS_CTRL_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_CKSYS_CTRL_CKSYS_CK_REQ_SW_EN_MASK 0x00000002 // CKSYS_CK_REQ_SW_EN[1]
#define CONN_BUS_CR_ON_CONN_INFRA_CKSYS_CTRL_CKSYS_CK_REQ_SW_EN_SHFT 1
#define CONN_BUS_CR_ON_CONN_INFRA_CKSYS_CTRL_CKSYS_CK_REQ_HW_MODE_ADDR CONN_BUS_CR_ON_CONN_INFRA_CKSYS_CTRL_ADDR
#define CONN_BUS_CR_ON_CONN_INFRA_CKSYS_CTRL_CKSYS_CK_REQ_HW_MODE_MASK 0x00000001 // CKSYS_CK_REQ_HW_MODE[0]
#define CONN_BUS_CR_ON_CONN_INFRA_CKSYS_CTRL_CKSYS_CK_REQ_HW_MODE_SHFT 0
#endif // __CONN_BUS_CR_ON_REGS_H__

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drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/CODA/conn_cfg.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
//[File] : conn_cfg.h
//[Revision time] : Fri Jun 18 16:52:47 2021
//[Description] : This file is auto generated by CODA
//[Copyright] : Copyright (C) 2021 Mediatek Incorportion. All rights reserved.
#ifndef __CONN_CFG_REGS_H__
#define __CONN_CFG_REGS_H__
//****************************************************************************
//
// CONN_CFG CR Definitions
//
//****************************************************************************
#define CONN_CFG_BASE (CONN_REG_CONN_INFRA_CFG_ADDR) // 0x18011000
#define CONN_CFG_IP_VERSION_ADDR (CONN_CFG_BASE + 0x000) // 1000
#define CONN_CFG_CFG_VERSION_ADDR (CONN_CFG_BASE + 0x004) // 1004
#define CONN_CFG_STRAP_STATUS_ADDR (CONN_CFG_BASE + 0x010) // 1010
#define CONN_CFG_EFUSE_ADDR (CONN_CFG_BASE + 0x020) // 1020
#define CONN_CFG_PLL_STATUS_ADDR (CONN_CFG_BASE + 0x030) // 1030
#define CONN_CFG_BUS_STATUS_ADDR (CONN_CFG_BASE + 0x034) // 1034
#define CONN_CFG_CFG_RSV0_ADDR (CONN_CFG_BASE + 0x040) // 1040
#define CONN_CFG_CFG_RSV1_ADDR (CONN_CFG_BASE + 0x044) // 1044
#define CONN_CFG_CMDBT_FETCH_START_ADDR0_ADDR (CONN_CFG_BASE + 0x050) // 1050
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_0_ADDR (CONN_CFG_BASE + 0x060) // 1060
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR (CONN_CFG_BASE + 0x064) // 1064
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_2_ADDR (CONN_CFG_BASE + 0x068) // 1068
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_3_ADDR (CONN_CFG_BASE + 0x06C) // 106C
#define CONN_CFG_EMI_CTL_0_ADDR (CONN_CFG_BASE + 0x100) // 1100
#define CONN_CFG_EMI_CTL_1_ADDR (CONN_CFG_BASE + 0x104) // 1104
#define CONN_CFG_EMI_CTL_TOP_ADDR (CONN_CFG_BASE + 0x110) // 1110
#define CONN_CFG_EMI_CTL_WF_ADDR (CONN_CFG_BASE + 0x114) // 1114
#define CONN_CFG_EMI_CTL_BT_ADDR (CONN_CFG_BASE + 0x118) // 1118
#define CONN_CFG_EMI_CTL_GPS_ADDR (CONN_CFG_BASE + 0x11C) // 111C
#define CONN_CFG_EMI_CTL_GPS_L1_ADDR (CONN_CFG_BASE + 0X120) // 1120
#define CONN_CFG_EMI_CTL_GPS_L5_ADDR (CONN_CFG_BASE + 0X124) // 1124
#define CONN_CFG_EMI_PROBE_ADDR (CONN_CFG_BASE + 0x130) // 1130
#define CONN_CFG_EMI_PROBE_1_ADDR (CONN_CFG_BASE + 0x134) // 1134
/* =====================================================================================
---IP_VERSION (0x18011000 + 0x000)---
IP_VERSION[31..0] - (RO) IP_VERSION
=====================================================================================*/
#define CONN_CFG_IP_VERSION_IP_VERSION_ADDR CONN_CFG_IP_VERSION_ADDR
#define CONN_CFG_IP_VERSION_IP_VERSION_MASK 0xFFFFFFFF // IP_VERSION[31..0]
#define CONN_CFG_IP_VERSION_IP_VERSION_SHFT 0
/* =====================================================================================
---CFG_VERSION (0x18011000 + 0x004)---
CFG_VERSION[31..0] - (RO) CFG_VERSION
=====================================================================================*/
#define CONN_CFG_CFG_VERSION_CFG_VERSION_ADDR CONN_CFG_CFG_VERSION_ADDR
#define CONN_CFG_CFG_VERSION_CFG_VERSION_MASK 0xFFFFFFFF // CFG_VERSION[31..0]
#define CONN_CFG_CFG_VERSION_CFG_VERSION_SHFT 0
/* =====================================================================================
---STRAP_STATUS (0x18011000 + 0x010)---
OSC_IS_20M[0] - (RO) OSC is 20MHz strap status (active-high)
OSC_IS_24M[1] - (RO) OSC is 24MHz strap status (active-high)
OSC_IS_25M[2] - (RO) OSC is 25MHz strap status (active-high)
OSC_IS_26M[3] - (RO) OSC is 26MHz strap status (active-high)
OSC_IS_40M[4] - (RO) OSC is 40MHz strap status (active-high)
OSC_IS_52M[5] - (RO) OSC is 52MHz strap status (active-high)
RESERVED6[7..6] - (RO) Reserved bits
OLT_BLT_MODE[8] - (RO) OLT BLT mode strap status (active-high)
SYSSTRAP_MODE[9] - (RO) conn_infra system debug mode strap status (active-high)
WFSYSSTRAP_MODE[10] - (RO) wfsys system debug mode strap status (active-high)
BGFSYSSTRAP_MODE[11] - (RO) bgfsys system debug mode strap status (active-high)
RBIST_MODE[12] - (RO) connsys RBIST mode strap status (active-high)
CONN_SPI2AHB_MODE[13] - (RO) connsys SPI to AHB mode strap status (active-high)
CONN_TEST_MODE[14] - (RO) connsys test mode strap status, which indicates SPI2AHB, RBIST, ATPG mode (active-high)
CONN_FORCE_PWR_ON_MODE[15] - (RO) force connsys MTCMOS and memory all on mode strap status (active-high)
CONN_EXTCK_MODE[16] - (RO) connsys external clock mode strap status (active-high)
CONN_BYPASS_ROM_MODE[17] - (RO) connsys bypass rom code mode strap status (active-high)
CONN_SPEEDUP_OSC_STABLE_MODE[18] - (RO) connsys speedup OSC stable mode strap status (active-high)
RESERVED19[31..19] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_STRAP_STATUS_CONN_SPEEDUP_OSC_STABLE_MODE_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_CONN_SPEEDUP_OSC_STABLE_MODE_MASK 0x00040000 // CONN_SPEEDUP_OSC_STABLE_MODE[18]
#define CONN_CFG_STRAP_STATUS_CONN_SPEEDUP_OSC_STABLE_MODE_SHFT 18
#define CONN_CFG_STRAP_STATUS_CONN_BYPASS_ROM_MODE_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_CONN_BYPASS_ROM_MODE_MASK 0x00020000 // CONN_BYPASS_ROM_MODE[17]
#define CONN_CFG_STRAP_STATUS_CONN_BYPASS_ROM_MODE_SHFT 17
#define CONN_CFG_STRAP_STATUS_CONN_EXTCK_MODE_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_CONN_EXTCK_MODE_MASK 0x00010000 // CONN_EXTCK_MODE[16]
#define CONN_CFG_STRAP_STATUS_CONN_EXTCK_MODE_SHFT 16
#define CONN_CFG_STRAP_STATUS_CONN_FORCE_PWR_ON_MODE_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_CONN_FORCE_PWR_ON_MODE_MASK 0x00008000 // CONN_FORCE_PWR_ON_MODE[15]
#define CONN_CFG_STRAP_STATUS_CONN_FORCE_PWR_ON_MODE_SHFT 15
#define CONN_CFG_STRAP_STATUS_CONN_TEST_MODE_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_CONN_TEST_MODE_MASK 0x00004000 // CONN_TEST_MODE[14]
#define CONN_CFG_STRAP_STATUS_CONN_TEST_MODE_SHFT 14
#define CONN_CFG_STRAP_STATUS_CONN_SPI2AHB_MODE_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_CONN_SPI2AHB_MODE_MASK 0x00002000 // CONN_SPI2AHB_MODE[13]
#define CONN_CFG_STRAP_STATUS_CONN_SPI2AHB_MODE_SHFT 13
#define CONN_CFG_STRAP_STATUS_RBIST_MODE_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_RBIST_MODE_MASK 0x00001000 // RBIST_MODE[12]
#define CONN_CFG_STRAP_STATUS_RBIST_MODE_SHFT 12
#define CONN_CFG_STRAP_STATUS_BGFSYSSTRAP_MODE_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_BGFSYSSTRAP_MODE_MASK 0x00000800 // BGFSYSSTRAP_MODE[11]
#define CONN_CFG_STRAP_STATUS_BGFSYSSTRAP_MODE_SHFT 11
#define CONN_CFG_STRAP_STATUS_WFSYSSTRAP_MODE_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_WFSYSSTRAP_MODE_MASK 0x00000400 // WFSYSSTRAP_MODE[10]
#define CONN_CFG_STRAP_STATUS_WFSYSSTRAP_MODE_SHFT 10
#define CONN_CFG_STRAP_STATUS_SYSSTRAP_MODE_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_SYSSTRAP_MODE_MASK 0x00000200 // SYSSTRAP_MODE[9]
#define CONN_CFG_STRAP_STATUS_SYSSTRAP_MODE_SHFT 9
#define CONN_CFG_STRAP_STATUS_OLT_BLT_MODE_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_OLT_BLT_MODE_MASK 0x00000100 // OLT_BLT_MODE[8]
#define CONN_CFG_STRAP_STATUS_OLT_BLT_MODE_SHFT 8
#define CONN_CFG_STRAP_STATUS_OSC_IS_52M_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_OSC_IS_52M_MASK 0x00000020 // OSC_IS_52M[5]
#define CONN_CFG_STRAP_STATUS_OSC_IS_52M_SHFT 5
#define CONN_CFG_STRAP_STATUS_OSC_IS_40M_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_OSC_IS_40M_MASK 0x00000010 // OSC_IS_40M[4]
#define CONN_CFG_STRAP_STATUS_OSC_IS_40M_SHFT 4
#define CONN_CFG_STRAP_STATUS_OSC_IS_26M_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_OSC_IS_26M_MASK 0x00000008 // OSC_IS_26M[3]
#define CONN_CFG_STRAP_STATUS_OSC_IS_26M_SHFT 3
#define CONN_CFG_STRAP_STATUS_OSC_IS_25M_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_OSC_IS_25M_MASK 0x00000004 // OSC_IS_25M[2]
#define CONN_CFG_STRAP_STATUS_OSC_IS_25M_SHFT 2
#define CONN_CFG_STRAP_STATUS_OSC_IS_24M_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_OSC_IS_24M_MASK 0x00000002 // OSC_IS_24M[1]
#define CONN_CFG_STRAP_STATUS_OSC_IS_24M_SHFT 1
#define CONN_CFG_STRAP_STATUS_OSC_IS_20M_ADDR CONN_CFG_STRAP_STATUS_ADDR
#define CONN_CFG_STRAP_STATUS_OSC_IS_20M_MASK 0x00000001 // OSC_IS_20M[0]
#define CONN_CFG_STRAP_STATUS_OSC_IS_20M_SHFT 0
/* =====================================================================================
---EFUSE (0x18011000 + 0x020)---
AP2CONN_EFUSE_DATA[15..0] - (RO) efuse data
AP2CONN_EFUSE_DATA_SECURITY[25..16] - (RO) efuse data
RESERVED26[31..26] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_EFUSE_AP2CONN_EFUSE_DATA_SECURITY_ADDR CONN_CFG_EFUSE_ADDR
#define CONN_CFG_EFUSE_AP2CONN_EFUSE_DATA_SECURITY_MASK 0x03FF0000 // AP2CONN_EFUSE_DATA_SECURITY[25..16]
#define CONN_CFG_EFUSE_AP2CONN_EFUSE_DATA_SECURITY_SHFT 16
#define CONN_CFG_EFUSE_AP2CONN_EFUSE_DATA_ADDR CONN_CFG_EFUSE_ADDR
#define CONN_CFG_EFUSE_AP2CONN_EFUSE_DATA_MASK 0x0000FFFF // AP2CONN_EFUSE_DATA[15..0]
#define CONN_CFG_EFUSE_AP2CONN_EFUSE_DATA_SHFT 0
/* =====================================================================================
---PLL_STATUS (0x18011000 + 0x030)---
WPLL_RDY[0] - (RO) WPLL ready
1'h0: not ready
1'h1: ready
BPLL_RDY[1] - (RO) BPLL ready
1'h0: not ready
1'h1: ready
RESERVED2[31..2] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_PLL_STATUS_BPLL_RDY_ADDR CONN_CFG_PLL_STATUS_ADDR
#define CONN_CFG_PLL_STATUS_BPLL_RDY_MASK 0x00000002 // BPLL_RDY[1]
#define CONN_CFG_PLL_STATUS_BPLL_RDY_SHFT 1
#define CONN_CFG_PLL_STATUS_WPLL_RDY_ADDR CONN_CFG_PLL_STATUS_ADDR
#define CONN_CFG_PLL_STATUS_WPLL_RDY_MASK 0x00000001 // WPLL_RDY[0]
#define CONN_CFG_PLL_STATUS_WPLL_RDY_SHFT 0
/* =====================================================================================
---BUS_STATUS (0x18011000 + 0x034)---
BUS_OSC_SW_RDY[0] - (RO) conn_infra BUS clock switch to OSC clock ready indicator(hclk_switch_rdy[0])
1'h0: not ready
1'h1: ready
BUS_32K_SW_RDY[1] - (RO) conn_infra BUS clock switch to 32KHz clock ready indicator(hclk_switch_rdy[1])
1'h0: not ready
1'h1: ready
BUS_BGFSYS_CK_SW_RDY_0[2] - (RO) conn_infra BUS clock switch to bgfsys BUS clock ready indicator(hclk_switch_rdy[2])
1'h0: not ready
1'h1: ready
BUS_BGFSYS_CK_SW_RDY_1[3] - (RO) conn_infra BUS clock switch to bgfsys BUS clock ready indicator(hclk_switch_rdy[3])
1'h0: not ready
1'h1: ready
BUS_WFSYS_CK_SW_RDY_0[4] - (RO) conn_infra BUS clock switch to wfsys BUS clock ready indicator(hclk_switch_rdy[4])
1'h0: not ready
1'h1: ready
BUS_WFSYS_CK_SW_RDY_1[5] - (RO) conn_infra BUS clock switch to wfsys BUS clock ready indicator(hclk_switch_rdy[5])
1'h0: not ready
1'h1: ready
BUS_WFSYS_CK_SW_RDY_2[6] - (RO) conn_infra BUS clock switch to wfsys BUS clock ready indicator(hclk_switch_rdy[6])
1'h0: not ready
1'h1: ready
BUS_ICAP_CK_SW_RDY[7] - (RO) conn_infra BUS clock switch to ICAP BUS clock ready indicator(hclk_switch_rdy[7])
1'h0: not ready
1'h1: ready
RESERVED8[31..8] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_BUS_STATUS_BUS_ICAP_CK_SW_RDY_ADDR CONN_CFG_BUS_STATUS_ADDR
#define CONN_CFG_BUS_STATUS_BUS_ICAP_CK_SW_RDY_MASK 0x00000080 // BUS_ICAP_CK_SW_RDY[7]
#define CONN_CFG_BUS_STATUS_BUS_ICAP_CK_SW_RDY_SHFT 7
#define CONN_CFG_BUS_STATUS_BUS_WFSYS_CK_SW_RDY_2_ADDR CONN_CFG_BUS_STATUS_ADDR
#define CONN_CFG_BUS_STATUS_BUS_WFSYS_CK_SW_RDY_2_MASK 0x00000040 // BUS_WFSYS_CK_SW_RDY_2[6]
#define CONN_CFG_BUS_STATUS_BUS_WFSYS_CK_SW_RDY_2_SHFT 6
#define CONN_CFG_BUS_STATUS_BUS_WFSYS_CK_SW_RDY_1_ADDR CONN_CFG_BUS_STATUS_ADDR
#define CONN_CFG_BUS_STATUS_BUS_WFSYS_CK_SW_RDY_1_MASK 0x00000020 // BUS_WFSYS_CK_SW_RDY_1[5]
#define CONN_CFG_BUS_STATUS_BUS_WFSYS_CK_SW_RDY_1_SHFT 5
#define CONN_CFG_BUS_STATUS_BUS_WFSYS_CK_SW_RDY_0_ADDR CONN_CFG_BUS_STATUS_ADDR
#define CONN_CFG_BUS_STATUS_BUS_WFSYS_CK_SW_RDY_0_MASK 0x00000010 // BUS_WFSYS_CK_SW_RDY_0[4]
#define CONN_CFG_BUS_STATUS_BUS_WFSYS_CK_SW_RDY_0_SHFT 4
#define CONN_CFG_BUS_STATUS_BUS_BGFSYS_CK_SW_RDY_1_ADDR CONN_CFG_BUS_STATUS_ADDR
#define CONN_CFG_BUS_STATUS_BUS_BGFSYS_CK_SW_RDY_1_MASK 0x00000008 // BUS_BGFSYS_CK_SW_RDY_1[3]
#define CONN_CFG_BUS_STATUS_BUS_BGFSYS_CK_SW_RDY_1_SHFT 3
#define CONN_CFG_BUS_STATUS_BUS_BGFSYS_CK_SW_RDY_0_ADDR CONN_CFG_BUS_STATUS_ADDR
#define CONN_CFG_BUS_STATUS_BUS_BGFSYS_CK_SW_RDY_0_MASK 0x00000004 // BUS_BGFSYS_CK_SW_RDY_0[2]
#define CONN_CFG_BUS_STATUS_BUS_BGFSYS_CK_SW_RDY_0_SHFT 2
#define CONN_CFG_BUS_STATUS_BUS_32K_SW_RDY_ADDR CONN_CFG_BUS_STATUS_ADDR
#define CONN_CFG_BUS_STATUS_BUS_32K_SW_RDY_MASK 0x00000002 // BUS_32K_SW_RDY[1]
#define CONN_CFG_BUS_STATUS_BUS_32K_SW_RDY_SHFT 1
#define CONN_CFG_BUS_STATUS_BUS_OSC_SW_RDY_ADDR CONN_CFG_BUS_STATUS_ADDR
#define CONN_CFG_BUS_STATUS_BUS_OSC_SW_RDY_MASK 0x00000001 // BUS_OSC_SW_RDY[0]
#define CONN_CFG_BUS_STATUS_BUS_OSC_SW_RDY_SHFT 0
/* =====================================================================================
---CFG_RSV0 (0x18011000 + 0x040)---
RSV0[31..0] - (RW) reserved CR
=====================================================================================*/
#define CONN_CFG_CFG_RSV0_RSV0_ADDR CONN_CFG_CFG_RSV0_ADDR
#define CONN_CFG_CFG_RSV0_RSV0_MASK 0xFFFFFFFF // RSV0[31..0]
#define CONN_CFG_CFG_RSV0_RSV0_SHFT 0
/* =====================================================================================
---CFG_RSV1 (0x18011000 + 0x044)---
RSV1[31..0] - (RW) reserved CR
=====================================================================================*/
#define CONN_CFG_CFG_RSV1_RSV1_ADDR CONN_CFG_CFG_RSV1_ADDR
#define CONN_CFG_CFG_RSV1_RSV1_MASK 0xFFFFFFFF // RSV1[31..0]
#define CONN_CFG_CFG_RSV1_RSV1_SHFT 0
/* =====================================================================================
---CMDBT_FETCH_START_ADDR0 (0x18011000 + 0x050)---
cmdbt_fetch_start_addr0[19..0] - (RW) cmdbt fetch start address 0 for top backup instruction address
RESERVED20[31..20] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_CMDBT_FETCH_START_ADDR0_cmdbt_fetch_start_addr0_ADDR CONN_CFG_CMDBT_FETCH_START_ADDR0_ADDR
#define CONN_CFG_CMDBT_FETCH_START_ADDR0_cmdbt_fetch_start_addr0_MASK 0x000FFFFF // cmdbt_fetch_start_addr0[19..0]
#define CONN_CFG_CMDBT_FETCH_START_ADDR0_cmdbt_fetch_start_addr0_SHFT 0
/* =====================================================================================
---CONN_INFRA_SYSRAM_CTRL_0 (0x18011000 + 0x060)---
CONN_INFRA_SYSRAM_DELSEL_UMS[19..0] - (RW) xxx
CONN_INFRA_SYSRAM_MBIST_USE_DEFAULT_DESEL[20] - (RW) xxx
CONN_INFRA_SYSRAM_HDEN[23..21] - (RW) xxx
RESERVED24[31..24] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_0_CONN_INFRA_SYSRAM_HDEN_ADDR CONN_CFG_CONN_INFRA_SYSRAM_CTRL_0_ADDR
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_0_CONN_INFRA_SYSRAM_HDEN_MASK 0x00E00000 // CONN_INFRA_SYSRAM_HDEN[23..21]
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_0_CONN_INFRA_SYSRAM_HDEN_SHFT 21
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_0_CONN_INFRA_SYSRAM_MBIST_USE_DEFAULT_DESEL_ADDR CONN_CFG_CONN_INFRA_SYSRAM_CTRL_0_ADDR
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_0_CONN_INFRA_SYSRAM_MBIST_USE_DEFAULT_DESEL_MASK 0x00100000 // CONN_INFRA_SYSRAM_MBIST_USE_DEFAULT_DESEL[20]
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_0_CONN_INFRA_SYSRAM_MBIST_USE_DEFAULT_DESEL_SHFT 20
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_0_CONN_INFRA_SYSRAM_DELSEL_UMS_ADDR CONN_CFG_CONN_INFRA_SYSRAM_CTRL_0_ADDR
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_0_CONN_INFRA_SYSRAM_DELSEL_UMS_MASK 0x000FFFFF // CONN_INFRA_SYSRAM_DELSEL_UMS[19..0]
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_0_CONN_INFRA_SYSRAM_DELSEL_UMS_SHFT 0
/* =====================================================================================
---CONN_INFRA_SYSRAM_CTRL_1 (0x18011000 + 0x064)---
CONN_INFRA_SYSRAM_PD_SEL_SCAN[3..0] - (RW) xxx
CONN_INFRA_SYSRAM_AWT[6..4] - (RW) xxx
CONN_INFRA_SYSRAM_ERR_CLR[7] - (RW) xxx
CONN_INFRA_SYSRAM_ERR_ADR[23..8] - (RO) xxx
RESERVED24[31..24] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_CONN_INFRA_SYSRAM_ERR_ADR_ADDR CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_CONN_INFRA_SYSRAM_ERR_ADR_MASK 0x00FFFF00 // CONN_INFRA_SYSRAM_ERR_ADR[23..8]
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_CONN_INFRA_SYSRAM_ERR_ADR_SHFT 8
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_CONN_INFRA_SYSRAM_ERR_CLR_ADDR CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_CONN_INFRA_SYSRAM_ERR_CLR_MASK 0x00000080 // CONN_INFRA_SYSRAM_ERR_CLR[7]
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_CONN_INFRA_SYSRAM_ERR_CLR_SHFT 7
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_CONN_INFRA_SYSRAM_AWT_ADDR CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_CONN_INFRA_SYSRAM_AWT_MASK 0x00000070 // CONN_INFRA_SYSRAM_AWT[6..4]
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_CONN_INFRA_SYSRAM_AWT_SHFT 4
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_CONN_INFRA_SYSRAM_PD_SEL_SCAN_ADDR CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_ADDR
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_CONN_INFRA_SYSRAM_PD_SEL_SCAN_MASK 0x0000000F // CONN_INFRA_SYSRAM_PD_SEL_SCAN[3..0]
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_1_CONN_INFRA_SYSRAM_PD_SEL_SCAN_SHFT 0
/* =====================================================================================
---CONN_INFRA_SYSRAM_CTRL_2 (0x18011000 + 0x068)---
CONN_INFRA_SYSRAM_ERROR_INFO[31..0] - (RW) xxx
=====================================================================================*/
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_2_CONN_INFRA_SYSRAM_ERROR_INFO_ADDR CONN_CFG_CONN_INFRA_SYSRAM_CTRL_2_ADDR
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_2_CONN_INFRA_SYSRAM_ERROR_INFO_MASK 0xFFFFFFFF // CONN_INFRA_SYSRAM_ERROR_INFO[31..0]
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_2_CONN_INFRA_SYSRAM_ERROR_INFO_SHFT 0
/* =====================================================================================
---CONN_INFRA_SYSRAM_CTRL_3 (0x18011000 + 0x06C)---
CONN_INFRA_SYSRAM_Y_DELSEL_UMS[19..0] - (RW) xxx
CONN_INFRA_SYSRAM_Y_MBIST_USE_DEFAULT_DESEL[20] - (RW) xxx
RESERVED21[31..21] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_3_CONN_INFRA_SYSRAM_Y_MBIST_USE_DEFAULT_DESEL_ADDR CONN_CFG_CONN_INFRA_SYSRAM_CTRL_3_ADDR
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_3_CONN_INFRA_SYSRAM_Y_MBIST_USE_DEFAULT_DESEL_MASK 0x00100000 // CONN_INFRA_SYSRAM_Y_MBIST_USE_DEFAULT_DESEL[20]
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_3_CONN_INFRA_SYSRAM_Y_MBIST_USE_DEFAULT_DESEL_SHFT 20
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_3_CONN_INFRA_SYSRAM_Y_DELSEL_UMS_ADDR CONN_CFG_CONN_INFRA_SYSRAM_CTRL_3_ADDR
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_3_CONN_INFRA_SYSRAM_Y_DELSEL_UMS_MASK 0x000FFFFF // CONN_INFRA_SYSRAM_Y_DELSEL_UMS[19..0]
#define CONN_CFG_CONN_INFRA_SYSRAM_CTRL_3_CONN_INFRA_SYSRAM_Y_DELSEL_UMS_SHFT 0
/* =====================================================================================
---EMI_CTL_0 (0x18011000 + 0x100)---
RESERVED0[0] - (RO) Reserved bits
EMI_CONN2AP_BUS_SLPPROT_BYPASS[1] - (RW) bypass CONN2AP bus slpprotect rdy check
1'b0: emi control signal deassert after conn2ap_bus_slpprot_rdy = 1
1'b1: emi control signal deassert don't need check conn2ap_bus_slpprot_rdy
CONN2AP_EMI_REQ[2] - (RO) conn2ap BUS request
CONN2AP_EMI_ONLY_REQ[3] - (RO) conn2emi BUS request
DDR_CNT_LIMIT[14..4] - (RW) counter limit for ddr_en auto timeout
set 0, ddr_en auto turn off function is disable
set others: ddr_en is auto turn off when ddr_cnt is count to ddr_cnt_limit
DDR_EN_CNT_UPDATE[15] - (RW) counter limit for ddr_en timeout update signal
1'b1: ddr_en timeout value = CR value(need set low after value has updated). Only update value at 1'b0 -> 1'b1 (rising edge)
1'b0: ddr_em timeout value don't update
RESERVED16[16] - (RO) Reserved bits
DDR_EN_BP_PROT[17] - (RW) ddr_en sw control bypass cr_emi_req limitation
1'b0: When cr_emi_req_xxx high , ddr_en can't be disable by sw control
1'b1: When cr_emi_req_xxx high , ddr_en can be disable by sw control
EMI_SLPPROT_BP_DDR_EN[18] - (RW) sleep protect control bypass ddr_en
1'b0: ddr_en_ack = low -> sleep protect enable
1'b1: sleep protect control bypass ddr_en_ack status
EMI_SLPPROT_BP_APSRC_REQ[19] - (RW) sleep protect control bypass apsrc_req
1'b0:apsrc_ack = low -> sleep protect enable
1'b1: sleep protect control bypass apsrc_ack status
INFRA_ONLY_MODE[20] - (RW) emi_ctl infra only mode
1'b0: conn2infra request will turn on emi
1'b1: conn2infra request wiill only turon infra bus, emi keep power off
EMI_CTL_DEBUG_1_SEL[22..21] - (RW) conn_infra_emi_ctl_1 debug selection
CONN_INFRA_OFF2ON_REQ_MASK[23] - (RW) conn_infra off2on req mask
1'b0: unmask, conn_infra bus off2on request will trigger emi_ctl enable infra mtcmos
1'b1: mask
CONN_INFRA_OFF2ON_REQ[24] - (RO) conn_infra off2on BUS request
RESERVED25[25] - (RO) Reserved bits
CR_PATH_SLP_PROT_DIS_BP[26] - (RW) bypass check conn2ap cr path sleep protect disable
EMI_PATH_SLP_PROT_DIS_BP[27] - (RW) bypass check conn2ap emi path sleep protect disable
EMI_PATH_SLP_PROT_EN_BP[28] - (RW) bypass check conn2ap emi path sleep protect enable
EMI_CTL_RSV_0[31..29] - (RW) Reserved CR
=====================================================================================*/
#define CONN_CFG_EMI_CTL_0_EMI_CTL_RSV_0_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_EMI_CTL_RSV_0_MASK 0xE0000000 // EMI_CTL_RSV_0[31..29]
#define CONN_CFG_EMI_CTL_0_EMI_CTL_RSV_0_SHFT 29
#define CONN_CFG_EMI_CTL_0_EMI_PATH_SLP_PROT_EN_BP_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_EMI_PATH_SLP_PROT_EN_BP_MASK 0x10000000 // EMI_PATH_SLP_PROT_EN_BP[28]
#define CONN_CFG_EMI_CTL_0_EMI_PATH_SLP_PROT_EN_BP_SHFT 28
#define CONN_CFG_EMI_CTL_0_EMI_PATH_SLP_PROT_DIS_BP_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_EMI_PATH_SLP_PROT_DIS_BP_MASK 0x08000000 // EMI_PATH_SLP_PROT_DIS_BP[27]
#define CONN_CFG_EMI_CTL_0_EMI_PATH_SLP_PROT_DIS_BP_SHFT 27
#define CONN_CFG_EMI_CTL_0_CR_PATH_SLP_PROT_DIS_BP_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_CR_PATH_SLP_PROT_DIS_BP_MASK 0x04000000 // CR_PATH_SLP_PROT_DIS_BP[26]
#define CONN_CFG_EMI_CTL_0_CR_PATH_SLP_PROT_DIS_BP_SHFT 26
#define CONN_CFG_EMI_CTL_0_CONN_INFRA_OFF2ON_REQ_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_CONN_INFRA_OFF2ON_REQ_MASK 0x01000000 // CONN_INFRA_OFF2ON_REQ[24]
#define CONN_CFG_EMI_CTL_0_CONN_INFRA_OFF2ON_REQ_SHFT 24
#define CONN_CFG_EMI_CTL_0_CONN_INFRA_OFF2ON_REQ_MASK_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_CONN_INFRA_OFF2ON_REQ_MASK_MASK 0x00800000 // CONN_INFRA_OFF2ON_REQ_MASK[23]
#define CONN_CFG_EMI_CTL_0_CONN_INFRA_OFF2ON_REQ_MASK_SHFT 23
#define CONN_CFG_EMI_CTL_0_EMI_CTL_DEBUG_1_SEL_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_EMI_CTL_DEBUG_1_SEL_MASK 0x00600000 // EMI_CTL_DEBUG_1_SEL[22..21]
#define CONN_CFG_EMI_CTL_0_EMI_CTL_DEBUG_1_SEL_SHFT 21
#define CONN_CFG_EMI_CTL_0_INFRA_ONLY_MODE_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_INFRA_ONLY_MODE_MASK 0x00100000 // INFRA_ONLY_MODE[20]
#define CONN_CFG_EMI_CTL_0_INFRA_ONLY_MODE_SHFT 20
#define CONN_CFG_EMI_CTL_0_EMI_SLPPROT_BP_APSRC_REQ_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_EMI_SLPPROT_BP_APSRC_REQ_MASK 0x00080000 // EMI_SLPPROT_BP_APSRC_REQ[19]
#define CONN_CFG_EMI_CTL_0_EMI_SLPPROT_BP_APSRC_REQ_SHFT 19
#define CONN_CFG_EMI_CTL_0_EMI_SLPPROT_BP_DDR_EN_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_EMI_SLPPROT_BP_DDR_EN_MASK 0x00040000 // EMI_SLPPROT_BP_DDR_EN[18]
#define CONN_CFG_EMI_CTL_0_EMI_SLPPROT_BP_DDR_EN_SHFT 18
#define CONN_CFG_EMI_CTL_0_DDR_EN_BP_PROT_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_DDR_EN_BP_PROT_MASK 0x00020000 // DDR_EN_BP_PROT[17]
#define CONN_CFG_EMI_CTL_0_DDR_EN_BP_PROT_SHFT 17
#define CONN_CFG_EMI_CTL_0_DDR_EN_CNT_UPDATE_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_DDR_EN_CNT_UPDATE_MASK 0x00008000 // DDR_EN_CNT_UPDATE[15]
#define CONN_CFG_EMI_CTL_0_DDR_EN_CNT_UPDATE_SHFT 15
#define CONN_CFG_EMI_CTL_0_DDR_CNT_LIMIT_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_DDR_CNT_LIMIT_MASK 0x00007FF0 // DDR_CNT_LIMIT[14..4]
#define CONN_CFG_EMI_CTL_0_DDR_CNT_LIMIT_SHFT 4
#define CONN_CFG_EMI_CTL_0_CONN2AP_EMI_ONLY_REQ_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_CONN2AP_EMI_ONLY_REQ_MASK 0x00000008 // CONN2AP_EMI_ONLY_REQ[3]
#define CONN_CFG_EMI_CTL_0_CONN2AP_EMI_ONLY_REQ_SHFT 3
#define CONN_CFG_EMI_CTL_0_CONN2AP_EMI_REQ_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_CONN2AP_EMI_REQ_MASK 0x00000004 // CONN2AP_EMI_REQ[2]
#define CONN_CFG_EMI_CTL_0_CONN2AP_EMI_REQ_SHFT 2
#define CONN_CFG_EMI_CTL_0_EMI_CONN2AP_BUS_SLPPROT_BYPASS_ADDR CONN_CFG_EMI_CTL_0_ADDR
#define CONN_CFG_EMI_CTL_0_EMI_CONN2AP_BUS_SLPPROT_BYPASS_MASK 0x00000002 // EMI_CONN2AP_BUS_SLPPROT_BYPASS[1]
#define CONN_CFG_EMI_CTL_0_EMI_CONN2AP_BUS_SLPPROT_BYPASS_SHFT 1
/* =====================================================================================
---EMI_CTL_1 (0x18011000 + 0x104)---
SRCCLKENA_PROT_EN[0] - (RW) enable srcclkena protect for conn_ddr_en
SRCCLKENA_ACK_BYPASS[1] - (RW) bypass srcclkena_ack check for conn2ap bus sleep protect
SRCCLKENA_ACK[2] - (RO) srcclkena_ack
SRCCLKENA_ACK_ERR[3] - (RO) SRCCLKENA ACK error drop low when request is active
SRCCLKENA_PROT_LIMIT[7..4] - (RW) srcclkena prortect cycles to avoid using ack signal after ddr_req is rising (unit xtal clock), because spm is under metastable
AP_BUS_PROT_EN[8] - (RW) enable ap_bus protect for conn_ddr_en
AP_BUS_ACK_BYPASS[9] - (RW) bypass ap_bus_ack check for conn2ap bus sleep protect
AP_BUS_ACK[10] - (RO) ap_bus_ack
AP_BUS_ACK_ERR[11] - (RO) AP_BUS_ACK error drop low when request is active
AP_BUS_PROT_LIMIT[15..12] - (RW) AP BUS prortect cycles to avoid using ack signal after ddr_req is rising (unit xtal clock), because spm is under metastable
APSRC_PROT_EN[16] - (RW) enable ddr protect for apsrc_en
APSRC_ACK_BYPASS[17] - (RW) bypass apsrc_ack check for conn2ap bus sleep protect
APSRC_ACK[18] - (RO) apsrc_ack
APSRC_ACK_ERR[19] - (RO) APSRC ACK error drop low when request is active
APSRC_PROT_LIMIT[23..20] - (RW) APSRC prortect cycles to avoid using ack signal after ddr_req is rising (unit xtal clock), because spm is under metastable
DDR_PROT_EN[24] - (RW) enable ddr protect for conn_ddr_en
DDR_EN_ACK_BYPASS[25] - (RW) bypass ddr_en_ack check for conn2ap bus sleep protect
DDR_EN_ACK[26] - (RO) ddr_en_ack
DDR_EN_ACK_ERR[27] - (RO) DDR ACK error drop low when request is active
DDR_PROT_LIMIT[31..28] - (RW) ddr prortect cycles to avoid using ack signal after ddr_req is rising (unit xtal clock), because spm is under metastable
=====================================================================================*/
#define CONN_CFG_EMI_CTL_1_DDR_PROT_LIMIT_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_DDR_PROT_LIMIT_MASK 0xF0000000 // DDR_PROT_LIMIT[31..28]
#define CONN_CFG_EMI_CTL_1_DDR_PROT_LIMIT_SHFT 28
#define CONN_CFG_EMI_CTL_1_DDR_EN_ACK_ERR_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_DDR_EN_ACK_ERR_MASK 0x08000000 // DDR_EN_ACK_ERR[27]
#define CONN_CFG_EMI_CTL_1_DDR_EN_ACK_ERR_SHFT 27
#define CONN_CFG_EMI_CTL_1_DDR_EN_ACK_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_DDR_EN_ACK_MASK 0x04000000 // DDR_EN_ACK[26]
#define CONN_CFG_EMI_CTL_1_DDR_EN_ACK_SHFT 26
#define CONN_CFG_EMI_CTL_1_DDR_EN_ACK_BYPASS_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_DDR_EN_ACK_BYPASS_MASK 0x02000000 // DDR_EN_ACK_BYPASS[25]
#define CONN_CFG_EMI_CTL_1_DDR_EN_ACK_BYPASS_SHFT 25
#define CONN_CFG_EMI_CTL_1_DDR_PROT_EN_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_DDR_PROT_EN_MASK 0x01000000 // DDR_PROT_EN[24]
#define CONN_CFG_EMI_CTL_1_DDR_PROT_EN_SHFT 24
#define CONN_CFG_EMI_CTL_1_APSRC_PROT_LIMIT_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_APSRC_PROT_LIMIT_MASK 0x00F00000 // APSRC_PROT_LIMIT[23..20]
#define CONN_CFG_EMI_CTL_1_APSRC_PROT_LIMIT_SHFT 20
#define CONN_CFG_EMI_CTL_1_APSRC_ACK_ERR_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_APSRC_ACK_ERR_MASK 0x00080000 // APSRC_ACK_ERR[19]
#define CONN_CFG_EMI_CTL_1_APSRC_ACK_ERR_SHFT 19
#define CONN_CFG_EMI_CTL_1_APSRC_ACK_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_APSRC_ACK_MASK 0x00040000 // APSRC_ACK[18]
#define CONN_CFG_EMI_CTL_1_APSRC_ACK_SHFT 18
#define CONN_CFG_EMI_CTL_1_APSRC_ACK_BYPASS_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_APSRC_ACK_BYPASS_MASK 0x00020000 // APSRC_ACK_BYPASS[17]
#define CONN_CFG_EMI_CTL_1_APSRC_ACK_BYPASS_SHFT 17
#define CONN_CFG_EMI_CTL_1_APSRC_PROT_EN_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_APSRC_PROT_EN_MASK 0x00010000 // APSRC_PROT_EN[16]
#define CONN_CFG_EMI_CTL_1_APSRC_PROT_EN_SHFT 16
#define CONN_CFG_EMI_CTL_1_AP_BUS_PROT_LIMIT_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_AP_BUS_PROT_LIMIT_MASK 0x0000F000 // AP_BUS_PROT_LIMIT[15..12]
#define CONN_CFG_EMI_CTL_1_AP_BUS_PROT_LIMIT_SHFT 12
#define CONN_CFG_EMI_CTL_1_AP_BUS_ACK_ERR_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_AP_BUS_ACK_ERR_MASK 0x00000800 // AP_BUS_ACK_ERR[11]
#define CONN_CFG_EMI_CTL_1_AP_BUS_ACK_ERR_SHFT 11
#define CONN_CFG_EMI_CTL_1_AP_BUS_ACK_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_AP_BUS_ACK_MASK 0x00000400 // AP_BUS_ACK[10]
#define CONN_CFG_EMI_CTL_1_AP_BUS_ACK_SHFT 10
#define CONN_CFG_EMI_CTL_1_AP_BUS_ACK_BYPASS_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_AP_BUS_ACK_BYPASS_MASK 0x00000200 // AP_BUS_ACK_BYPASS[9]
#define CONN_CFG_EMI_CTL_1_AP_BUS_ACK_BYPASS_SHFT 9
#define CONN_CFG_EMI_CTL_1_AP_BUS_PROT_EN_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_AP_BUS_PROT_EN_MASK 0x00000100 // AP_BUS_PROT_EN[8]
#define CONN_CFG_EMI_CTL_1_AP_BUS_PROT_EN_SHFT 8
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_PROT_LIMIT_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_PROT_LIMIT_MASK 0x000000F0 // SRCCLKENA_PROT_LIMIT[7..4]
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_PROT_LIMIT_SHFT 4
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_ACK_ERR_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_ACK_ERR_MASK 0x00000008 // SRCCLKENA_ACK_ERR[3]
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_ACK_ERR_SHFT 3
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_ACK_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_ACK_MASK 0x00000004 // SRCCLKENA_ACK[2]
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_ACK_SHFT 2
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_ACK_BYPASS_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_ACK_BYPASS_MASK 0x00000002 // SRCCLKENA_ACK_BYPASS[1]
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_ACK_BYPASS_SHFT 1
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_PROT_EN_ADDR CONN_CFG_EMI_CTL_1_ADDR
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_PROT_EN_MASK 0x00000001 // SRCCLKENA_PROT_EN[0]
#define CONN_CFG_EMI_CTL_1_SRCCLKENA_PROT_EN_SHFT 0
/* =====================================================================================
---EMI_CTL_TOP (0x18011000 + 0x110)---
EMI_REQ_TOP[0] - (RW) TOP emi request
1'b1: need use EMI
1'b0: don't need use EMI, and disable emi
SW_CONN_SRCCLKENA_TOP[1] - (RW) software srcclkena control by top
SW_CONN_AP_BUS_REQ_TOP[2] - (RW) software ap_bus_req control by top
SW_CONN_APSRC_REQ_TOP[3] - (RW) software apsrc_req control by top
SW_CONN_DDR_EN_TOP[4] - (RW) software ddr_en control by top
INFRA_REQ_TOP[5] - (RW) TOP infra request
1'b1: need use INFRA
1'b0: don't need use INFRA, and disable INFRA
EMI_CTL_RSV_TOP[15..6] - (RW) reserved CR
RESERVED16[31..16] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_EMI_CTL_TOP_EMI_CTL_RSV_TOP_ADDR CONN_CFG_EMI_CTL_TOP_ADDR
#define CONN_CFG_EMI_CTL_TOP_EMI_CTL_RSV_TOP_MASK 0x0000FFC0 // EMI_CTL_RSV_TOP[15..6]
#define CONN_CFG_EMI_CTL_TOP_EMI_CTL_RSV_TOP_SHFT 6
#define CONN_CFG_EMI_CTL_TOP_INFRA_REQ_TOP_ADDR CONN_CFG_EMI_CTL_TOP_ADDR
#define CONN_CFG_EMI_CTL_TOP_INFRA_REQ_TOP_MASK 0x00000020 // INFRA_REQ_TOP[5]
#define CONN_CFG_EMI_CTL_TOP_INFRA_REQ_TOP_SHFT 5
#define CONN_CFG_EMI_CTL_TOP_SW_CONN_DDR_EN_TOP_ADDR CONN_CFG_EMI_CTL_TOP_ADDR
#define CONN_CFG_EMI_CTL_TOP_SW_CONN_DDR_EN_TOP_MASK 0x00000010 // SW_CONN_DDR_EN_TOP[4]
#define CONN_CFG_EMI_CTL_TOP_SW_CONN_DDR_EN_TOP_SHFT 4
#define CONN_CFG_EMI_CTL_TOP_SW_CONN_APSRC_REQ_TOP_ADDR CONN_CFG_EMI_CTL_TOP_ADDR
#define CONN_CFG_EMI_CTL_TOP_SW_CONN_APSRC_REQ_TOP_MASK 0x00000008 // SW_CONN_APSRC_REQ_TOP[3]
#define CONN_CFG_EMI_CTL_TOP_SW_CONN_APSRC_REQ_TOP_SHFT 3
#define CONN_CFG_EMI_CTL_TOP_SW_CONN_AP_BUS_REQ_TOP_ADDR CONN_CFG_EMI_CTL_TOP_ADDR
#define CONN_CFG_EMI_CTL_TOP_SW_CONN_AP_BUS_REQ_TOP_MASK 0x00000004 // SW_CONN_AP_BUS_REQ_TOP[2]
#define CONN_CFG_EMI_CTL_TOP_SW_CONN_AP_BUS_REQ_TOP_SHFT 2
#define CONN_CFG_EMI_CTL_TOP_SW_CONN_SRCCLKENA_TOP_ADDR CONN_CFG_EMI_CTL_TOP_ADDR
#define CONN_CFG_EMI_CTL_TOP_SW_CONN_SRCCLKENA_TOP_MASK 0x00000002 // SW_CONN_SRCCLKENA_TOP[1]
#define CONN_CFG_EMI_CTL_TOP_SW_CONN_SRCCLKENA_TOP_SHFT 1
#define CONN_CFG_EMI_CTL_TOP_EMI_REQ_TOP_ADDR CONN_CFG_EMI_CTL_TOP_ADDR
#define CONN_CFG_EMI_CTL_TOP_EMI_REQ_TOP_MASK 0x00000001 // EMI_REQ_TOP[0]
#define CONN_CFG_EMI_CTL_TOP_EMI_REQ_TOP_SHFT 0
/* =====================================================================================
---EMI_CTL_WF (0x18011000 + 0x114)---
EMI_REQ_WF[0] - (RW) wf emi request
1'b1: need use EMI
1'b0: don't need use EMI, and disable emi
SW_CONN_SRCCLKENA_WF[1] - (RW) software srcclkena control by wf
SW_CONN_AP_BUS_REQ_WF[2] - (RW) software ap_bus_req control by wf
SW_CONN_APSRC_REQ_WF[3] - (RW) software apsrc_req control by wf
SW_CONN_DDR_EN_WF[4] - (RW) software ddr_en control by wf
INFRA_REQ_WF[5] - (RW) WF infra request
1'b1: need use INFRA
1'b0: don't need use INFRA, and disable INFRA
EMI_CTL_RSV_WF[15..6] - (RW) reserved CR
RESERVED16[31..16] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_EMI_CTL_WF_EMI_CTL_RSV_WF_ADDR CONN_CFG_EMI_CTL_WF_ADDR
#define CONN_CFG_EMI_CTL_WF_EMI_CTL_RSV_WF_MASK 0x0000FFC0 // EMI_CTL_RSV_WF[15..6]
#define CONN_CFG_EMI_CTL_WF_EMI_CTL_RSV_WF_SHFT 6
#define CONN_CFG_EMI_CTL_WF_INFRA_REQ_WF_ADDR CONN_CFG_EMI_CTL_WF_ADDR
#define CONN_CFG_EMI_CTL_WF_INFRA_REQ_WF_MASK 0x00000020 // INFRA_REQ_WF[5]
#define CONN_CFG_EMI_CTL_WF_INFRA_REQ_WF_SHFT 5
#define CONN_CFG_EMI_CTL_WF_SW_CONN_DDR_EN_WF_ADDR CONN_CFG_EMI_CTL_WF_ADDR
#define CONN_CFG_EMI_CTL_WF_SW_CONN_DDR_EN_WF_MASK 0x00000010 // SW_CONN_DDR_EN_WF[4]
#define CONN_CFG_EMI_CTL_WF_SW_CONN_DDR_EN_WF_SHFT 4
#define CONN_CFG_EMI_CTL_WF_SW_CONN_APSRC_REQ_WF_ADDR CONN_CFG_EMI_CTL_WF_ADDR
#define CONN_CFG_EMI_CTL_WF_SW_CONN_APSRC_REQ_WF_MASK 0x00000008 // SW_CONN_APSRC_REQ_WF[3]
#define CONN_CFG_EMI_CTL_WF_SW_CONN_APSRC_REQ_WF_SHFT 3
#define CONN_CFG_EMI_CTL_WF_SW_CONN_AP_BUS_REQ_WF_ADDR CONN_CFG_EMI_CTL_WF_ADDR
#define CONN_CFG_EMI_CTL_WF_SW_CONN_AP_BUS_REQ_WF_MASK 0x00000004 // SW_CONN_AP_BUS_REQ_WF[2]
#define CONN_CFG_EMI_CTL_WF_SW_CONN_AP_BUS_REQ_WF_SHFT 2
#define CONN_CFG_EMI_CTL_WF_SW_CONN_SRCCLKENA_WF_ADDR CONN_CFG_EMI_CTL_WF_ADDR
#define CONN_CFG_EMI_CTL_WF_SW_CONN_SRCCLKENA_WF_MASK 0x00000002 // SW_CONN_SRCCLKENA_WF[1]
#define CONN_CFG_EMI_CTL_WF_SW_CONN_SRCCLKENA_WF_SHFT 1
#define CONN_CFG_EMI_CTL_WF_EMI_REQ_WF_ADDR CONN_CFG_EMI_CTL_WF_ADDR
#define CONN_CFG_EMI_CTL_WF_EMI_REQ_WF_MASK 0x00000001 // EMI_REQ_WF[0]
#define CONN_CFG_EMI_CTL_WF_EMI_REQ_WF_SHFT 0
/* =====================================================================================
---EMI_CTL_BT (0x18011000 + 0x118)---
EMI_REQ_BT[0] - (RW) bt emi request
1'b1: need use EMI
1'b0: don't need use EMI, and disable emi
SW_CONN_SRCCLKENA_BT[1] - (RW) software srcclkena control by bt
SW_CONN_AP_BUS_REQ_BT[2] - (RW) software ap_bus_req control by bt
SW_CONN_APSRC_REQ_BT[3] - (RW) software apsrc_req control by bt
SW_CONN_DDR_EN_BT[4] - (RW) software ddr_en control by bt
INFRA_REQ_BT[5] - (RW) BT infra request
1'b1: need use INFRA
1'b0: don't need use INFRA, and disable INFRA
EMI_CTL_RSV_BT[15..6] - (RW) reserved CR
RESERVED16[31..16] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_EMI_CTL_BT_EMI_CTL_RSV_BT_ADDR CONN_CFG_EMI_CTL_BT_ADDR
#define CONN_CFG_EMI_CTL_BT_EMI_CTL_RSV_BT_MASK 0x0000FFC0 // EMI_CTL_RSV_BT[15..6]
#define CONN_CFG_EMI_CTL_BT_EMI_CTL_RSV_BT_SHFT 6
#define CONN_CFG_EMI_CTL_BT_INFRA_REQ_BT_ADDR CONN_CFG_EMI_CTL_BT_ADDR
#define CONN_CFG_EMI_CTL_BT_INFRA_REQ_BT_MASK 0x00000020 // INFRA_REQ_BT[5]
#define CONN_CFG_EMI_CTL_BT_INFRA_REQ_BT_SHFT 5
#define CONN_CFG_EMI_CTL_BT_SW_CONN_DDR_EN_BT_ADDR CONN_CFG_EMI_CTL_BT_ADDR
#define CONN_CFG_EMI_CTL_BT_SW_CONN_DDR_EN_BT_MASK 0x00000010 // SW_CONN_DDR_EN_BT[4]
#define CONN_CFG_EMI_CTL_BT_SW_CONN_DDR_EN_BT_SHFT 4
#define CONN_CFG_EMI_CTL_BT_SW_CONN_APSRC_REQ_BT_ADDR CONN_CFG_EMI_CTL_BT_ADDR
#define CONN_CFG_EMI_CTL_BT_SW_CONN_APSRC_REQ_BT_MASK 0x00000008 // SW_CONN_APSRC_REQ_BT[3]
#define CONN_CFG_EMI_CTL_BT_SW_CONN_APSRC_REQ_BT_SHFT 3
#define CONN_CFG_EMI_CTL_BT_SW_CONN_AP_BUS_REQ_BT_ADDR CONN_CFG_EMI_CTL_BT_ADDR
#define CONN_CFG_EMI_CTL_BT_SW_CONN_AP_BUS_REQ_BT_MASK 0x00000004 // SW_CONN_AP_BUS_REQ_BT[2]
#define CONN_CFG_EMI_CTL_BT_SW_CONN_AP_BUS_REQ_BT_SHFT 2
#define CONN_CFG_EMI_CTL_BT_SW_CONN_SRCCLKENA_BT_ADDR CONN_CFG_EMI_CTL_BT_ADDR
#define CONN_CFG_EMI_CTL_BT_SW_CONN_SRCCLKENA_BT_MASK 0x00000002 // SW_CONN_SRCCLKENA_BT[1]
#define CONN_CFG_EMI_CTL_BT_SW_CONN_SRCCLKENA_BT_SHFT 1
#define CONN_CFG_EMI_CTL_BT_EMI_REQ_BT_ADDR CONN_CFG_EMI_CTL_BT_ADDR
#define CONN_CFG_EMI_CTL_BT_EMI_REQ_BT_MASK 0x00000001 // EMI_REQ_BT[0]
#define CONN_CFG_EMI_CTL_BT_EMI_REQ_BT_SHFT 0
/* =====================================================================================
---EMI_CTL_GPS (0x18011000 + 0x11C)---
EMI_REQ_GPS[0] - (RW) gps emi request
1'b1: need use EMI
1'b0: don't need use EMI, and disable emi
SW_CONN_SRCCLKENA_GPS[1] - (RW) software srcclkena control by gps
SW_CONN_AP_BUS_REQ_GPS[2] - (RW) software ap_bus_req control by gps
SW_CONN_APSRC_REQ_GPS[3] - (RW) software apsrc_req control by gps
SW_CONN_DDR_EN_GPS[4] - (RW) software ddr_en control by gps
INFRA_REQ_GPS[5] - (RW) GPS infra request
1'b1: need use INFRA
1'b0: don't need use INFRA, and disable INFRA
EMI_CTL_RSV_GPS[15..6] - (RW) reserved CR
RESERVED16[31..16] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_EMI_CTL_GPS_EMI_CTL_RSV_GPS_ADDR CONN_CFG_EMI_CTL_GPS_ADDR
#define CONN_CFG_EMI_CTL_GPS_EMI_CTL_RSV_GPS_MASK 0x0000FFC0 // EMI_CTL_RSV_GPS[15..6]
#define CONN_CFG_EMI_CTL_GPS_EMI_CTL_RSV_GPS_SHFT 6
#define CONN_CFG_EMI_CTL_GPS_INFRA_REQ_GPS_ADDR CONN_CFG_EMI_CTL_GPS_ADDR
#define CONN_CFG_EMI_CTL_GPS_INFRA_REQ_GPS_MASK 0x00000020 // INFRA_REQ_GPS[5]
#define CONN_CFG_EMI_CTL_GPS_INFRA_REQ_GPS_SHFT 5
#define CONN_CFG_EMI_CTL_GPS_SW_CONN_DDR_EN_GPS_ADDR CONN_CFG_EMI_CTL_GPS_ADDR
#define CONN_CFG_EMI_CTL_GPS_SW_CONN_DDR_EN_GPS_MASK 0x00000010 // SW_CONN_DDR_EN_GPS[4]
#define CONN_CFG_EMI_CTL_GPS_SW_CONN_DDR_EN_GPS_SHFT 4
#define CONN_CFG_EMI_CTL_GPS_SW_CONN_APSRC_REQ_GPS_ADDR CONN_CFG_EMI_CTL_GPS_ADDR
#define CONN_CFG_EMI_CTL_GPS_SW_CONN_APSRC_REQ_GPS_MASK 0x00000008 // SW_CONN_APSRC_REQ_GPS[3]
#define CONN_CFG_EMI_CTL_GPS_SW_CONN_APSRC_REQ_GPS_SHFT 3
#define CONN_CFG_EMI_CTL_GPS_SW_CONN_AP_BUS_REQ_GPS_ADDR CONN_CFG_EMI_CTL_GPS_ADDR
#define CONN_CFG_EMI_CTL_GPS_SW_CONN_AP_BUS_REQ_GPS_MASK 0x00000004 // SW_CONN_AP_BUS_REQ_GPS[2]
#define CONN_CFG_EMI_CTL_GPS_SW_CONN_AP_BUS_REQ_GPS_SHFT 2
#define CONN_CFG_EMI_CTL_GPS_SW_CONN_SRCCLKENA_GPS_ADDR CONN_CFG_EMI_CTL_GPS_ADDR
#define CONN_CFG_EMI_CTL_GPS_SW_CONN_SRCCLKENA_GPS_MASK 0x00000002 // SW_CONN_SRCCLKENA_GPS[1]
#define CONN_CFG_EMI_CTL_GPS_SW_CONN_SRCCLKENA_GPS_SHFT 1
#define CONN_CFG_EMI_CTL_GPS_EMI_REQ_GPS_ADDR CONN_CFG_EMI_CTL_GPS_ADDR
#define CONN_CFG_EMI_CTL_GPS_EMI_REQ_GPS_MASK 0x00000001 // EMI_REQ_GPS[0]
#define CONN_CFG_EMI_CTL_GPS_EMI_REQ_GPS_SHFT 0
/* =====================================================================================
---EMI_CTL_GPS_L1 (0x18011000 + 0X120)---
EMI_REQ_GPS_L1[0] - (RW) GPS_L1 emi request
1'b1: need use EMI
1'b0: don't need use EMI, and disable emi
SW_CONN_SRCCLKENA_GPS_L1[1] - (RW) software srcclkena control by GPS_L1
SW_CONN_AP_BUS_REQ_GPS_L1[2] - (RW) software ap_bus_req control by GPS_L1
SW_CONN_APSRC_REQ_GPS_L1[3] - (RW) software apsrc_req control by GPS_L1
SW_CONN_DDR_EN_GPS_L1[4] - (RW) software ddr_en control by GPS_L1
INFRA_REQ_GPS_L1[5] - (RW) GPS_L1 infra request
1'b1: need use INFRA
1'b0: don't need use INFRA, and disable INFRA
EMI_CTL_RSV_GPS_L1[15..6] - (RW) reserved CR
RESERVED16[31..16] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_EMI_CTL_GPS_L1_EMI_CTL_RSV_GPS_L1_ADDR CONN_CFG_EMI_CTL_GPS_L1_ADDR
#define CONN_CFG_EMI_CTL_GPS_L1_EMI_CTL_RSV_GPS_L1_MASK 0x0000FFC0 // EMI_CTL_RSV_GPS_L1[15..6]
#define CONN_CFG_EMI_CTL_GPS_L1_EMI_CTL_RSV_GPS_L1_SHFT 6
#define CONN_CFG_EMI_CTL_GPS_L1_INFRA_REQ_GPS_L1_ADDR CONN_CFG_EMI_CTL_GPS_L1_ADDR
#define CONN_CFG_EMI_CTL_GPS_L1_INFRA_REQ_GPS_L1_MASK 0x00000020 // INFRA_REQ_GPS_L1[5]
#define CONN_CFG_EMI_CTL_GPS_L1_INFRA_REQ_GPS_L1_SHFT 5
#define CONN_CFG_EMI_CTL_GPS_L1_SW_CONN_DDR_EN_GPS_L1_ADDR CONN_CFG_EMI_CTL_GPS_L1_ADDR
#define CONN_CFG_EMI_CTL_GPS_L1_SW_CONN_DDR_EN_GPS_L1_MASK 0x00000010 // SW_CONN_DDR_EN_GPS_L1[4]
#define CONN_CFG_EMI_CTL_GPS_L1_SW_CONN_DDR_EN_GPS_L1_SHFT 4
#define CONN_CFG_EMI_CTL_GPS_L1_SW_CONN_APSRC_REQ_GPS_L1_ADDR CONN_CFG_EMI_CTL_GPS_L1_ADDR
#define CONN_CFG_EMI_CTL_GPS_L1_SW_CONN_APSRC_REQ_GPS_L1_MASK 0x00000008 // SW_CONN_APSRC_REQ_GPS_L1[3]
#define CONN_CFG_EMI_CTL_GPS_L1_SW_CONN_APSRC_REQ_GPS_L1_SHFT 3
#define CONN_CFG_EMI_CTL_GPS_L1_SW_CONN_AP_BUS_REQ_GPS_L1_ADDR CONN_CFG_EMI_CTL_GPS_L1_ADDR
#define CONN_CFG_EMI_CTL_GPS_L1_SW_CONN_AP_BUS_REQ_GPS_L1_MASK 0x00000004 // SW_CONN_AP_BUS_REQ_GPS_L1[2]
#define CONN_CFG_EMI_CTL_GPS_L1_SW_CONN_AP_BUS_REQ_GPS_L1_SHFT 2
#define CONN_CFG_EMI_CTL_GPS_L1_SW_CONN_SRCCLKENA_GPS_L1_ADDR CONN_CFG_EMI_CTL_GPS_L1_ADDR
#define CONN_CFG_EMI_CTL_GPS_L1_SW_CONN_SRCCLKENA_GPS_L1_MASK 0x00000002 // SW_CONN_SRCCLKENA_GPS_L1[1]
#define CONN_CFG_EMI_CTL_GPS_L1_SW_CONN_SRCCLKENA_GPS_L1_SHFT 1
#define CONN_CFG_EMI_CTL_GPS_L1_EMI_REQ_GPS_L1_ADDR CONN_CFG_EMI_CTL_GPS_L1_ADDR
#define CONN_CFG_EMI_CTL_GPS_L1_EMI_REQ_GPS_L1_MASK 0x00000001 // EMI_REQ_GPS_L1[0]
#define CONN_CFG_EMI_CTL_GPS_L1_EMI_REQ_GPS_L1_SHFT 0
/* =====================================================================================
---EMI_CTL_GPS_L5 (0x18011000 + 0X124)---
EMI_REQ_GPS_L5[0] - (RW) GPS_L5 emi request
1'b1: need use EMI
1'b0: don't need use EMI, and disable emi
SW_CONN_SRCCLKENA_GPS_L5[1] - (RW) software srcclkena control by GPS_L5
SW_CONN_AP_BUS_REQ_GPS_L5[2] - (RW) software ap_bus_req control by GPS_L5
SW_CONN_APSRC_REQ_GPS_L5[3] - (RW) software apsrc_req control by GPS_L5
SW_CONN_DDR_EN_GPS_L5[4] - (RW) software ddr_en control by GPS_L5
INFRA_REQ_GPS_L5[5] - (RW) GPS_L5 infra request
1'b1: need use INFRA
1'b0: don't need use INFRA, and disable INFRA
EMI_CTL_RSV_GPS_L5[15..6] - (RW) reserved CR
RESERVED16[31..16] - (RO) Reserved bits
=====================================================================================*/
#define CONN_CFG_EMI_CTL_GPS_L5_EMI_CTL_RSV_GPS_L5_ADDR CONN_CFG_EMI_CTL_GPS_L5_ADDR
#define CONN_CFG_EMI_CTL_GPS_L5_EMI_CTL_RSV_GPS_L5_MASK 0x0000FFC0 // EMI_CTL_RSV_GPS_L5[15..6]
#define CONN_CFG_EMI_CTL_GPS_L5_EMI_CTL_RSV_GPS_L5_SHFT 6
#define CONN_CFG_EMI_CTL_GPS_L5_INFRA_REQ_GPS_L5_ADDR CONN_CFG_EMI_CTL_GPS_L5_ADDR
#define CONN_CFG_EMI_CTL_GPS_L5_INFRA_REQ_GPS_L5_MASK 0x00000020 // INFRA_REQ_GPS_L5[5]
#define CONN_CFG_EMI_CTL_GPS_L5_INFRA_REQ_GPS_L5_SHFT 5
#define CONN_CFG_EMI_CTL_GPS_L5_SW_CONN_DDR_EN_GPS_L5_ADDR CONN_CFG_EMI_CTL_GPS_L5_ADDR
#define CONN_CFG_EMI_CTL_GPS_L5_SW_CONN_DDR_EN_GPS_L5_MASK 0x00000010 // SW_CONN_DDR_EN_GPS_L5[4]
#define CONN_CFG_EMI_CTL_GPS_L5_SW_CONN_DDR_EN_GPS_L5_SHFT 4
#define CONN_CFG_EMI_CTL_GPS_L5_SW_CONN_APSRC_REQ_GPS_L5_ADDR CONN_CFG_EMI_CTL_GPS_L5_ADDR
#define CONN_CFG_EMI_CTL_GPS_L5_SW_CONN_APSRC_REQ_GPS_L5_MASK 0x00000008 // SW_CONN_APSRC_REQ_GPS_L5[3]
#define CONN_CFG_EMI_CTL_GPS_L5_SW_CONN_APSRC_REQ_GPS_L5_SHFT 3
#define CONN_CFG_EMI_CTL_GPS_L5_SW_CONN_AP_BUS_REQ_GPS_L5_ADDR CONN_CFG_EMI_CTL_GPS_L5_ADDR
#define CONN_CFG_EMI_CTL_GPS_L5_SW_CONN_AP_BUS_REQ_GPS_L5_MASK 0x00000004 // SW_CONN_AP_BUS_REQ_GPS_L5[2]
#define CONN_CFG_EMI_CTL_GPS_L5_SW_CONN_AP_BUS_REQ_GPS_L5_SHFT 2
#define CONN_CFG_EMI_CTL_GPS_L5_SW_CONN_SRCCLKENA_GPS_L5_ADDR CONN_CFG_EMI_CTL_GPS_L5_ADDR
#define CONN_CFG_EMI_CTL_GPS_L5_SW_CONN_SRCCLKENA_GPS_L5_MASK 0x00000002 // SW_CONN_SRCCLKENA_GPS_L5[1]
#define CONN_CFG_EMI_CTL_GPS_L5_SW_CONN_SRCCLKENA_GPS_L5_SHFT 1
#define CONN_CFG_EMI_CTL_GPS_L5_EMI_REQ_GPS_L5_ADDR CONN_CFG_EMI_CTL_GPS_L5_ADDR
#define CONN_CFG_EMI_CTL_GPS_L5_EMI_REQ_GPS_L5_MASK 0x00000001 // EMI_REQ_GPS_L5[0]
#define CONN_CFG_EMI_CTL_GPS_L5_EMI_REQ_GPS_L5_SHFT 0
/* =====================================================================================
---EMI_PROBE (0x18011000 + 0x130)---
CONN_SRCCCLKENA[0] - (RO) xxx
CONN_AP_BUS[1] - (RO) xxx
CONN_APSRC[2] - (RO) xxx
CONN_DDR_EN[3] - (RO) xxx
CONN_SRCCCLKENA_ACK[4] - (RO) xxx
CONN_AP_BUS_ACK[5] - (RO) xxx
CONN_APSRC_ACK[6] - (RO) xxx
CONN_DDR_EN_ACK[7] - (RO) xxx
SRCCLKENA_ACK_SYNC[8] - (RO) xxx
AP_BUS_ACK_SYNC[9] - (RO) xxx
APSRC_ACK_SYNC[10] - (RO) xxx
DDR_EN_ACK_SYNC[11] - (RO) xxx
CONN2AP_BUS_IDLE[12] - (RO) xxx
CONN_OFF2ON_REQ[13] - (RO) xxx
CONN2AP_BUS_SLPPROT_EN[14] - (RO) xxx
CONN2AP_BUS_EMI_SLPPROT_EN[15] - (RO) xxx
SRCCLKENA_STABLE_REG[16] - (RO) xxx
APSRC_STABLE_REG[17] - (RO) xxx
AP_BUS_STABLE_REG[18] - (RO) xxx
DDR_EN_STABLE_REG[19] - (RO) xxx
SRCCLKENA_STABLE[20] - (RO) xxx
APSRC_STABLE[21] - (RO) xxx
AP_BUS_STABLE[22] - (RO) xxx
DDR_EN_STABLE[23] - (RO) xxx
EMI_REQ_ALL[24] - (RO) xxx
EMI_REQ_DIS[25] - (RO) xxx
DDR_TIMEOUT[26] - (RO) xxx
CONN2AP_EMI_ONLY_REQ[27] - (RO) xxx
HW_CONN_SRCCLKENA_EMI_DIS[28] - (RO) xxx
HW_CONN_AP_BUS_REQ_DIS[29] - (RO) xxx
HW_CONN_APSRC_REQ_DIS[30] - (RO) xxx
HW_CONN_DDR_EN_DIS[31] - (RO) xxx
=====================================================================================*/
#define CONN_CFG_EMI_PROBE_HW_CONN_DDR_EN_DIS_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_HW_CONN_DDR_EN_DIS_MASK 0x80000000 // HW_CONN_DDR_EN_DIS[31]
#define CONN_CFG_EMI_PROBE_HW_CONN_DDR_EN_DIS_SHFT 31
#define CONN_CFG_EMI_PROBE_HW_CONN_APSRC_REQ_DIS_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_HW_CONN_APSRC_REQ_DIS_MASK 0x40000000 // HW_CONN_APSRC_REQ_DIS[30]
#define CONN_CFG_EMI_PROBE_HW_CONN_APSRC_REQ_DIS_SHFT 30
#define CONN_CFG_EMI_PROBE_HW_CONN_AP_BUS_REQ_DIS_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_HW_CONN_AP_BUS_REQ_DIS_MASK 0x20000000 // HW_CONN_AP_BUS_REQ_DIS[29]
#define CONN_CFG_EMI_PROBE_HW_CONN_AP_BUS_REQ_DIS_SHFT 29
#define CONN_CFG_EMI_PROBE_HW_CONN_SRCCLKENA_EMI_DIS_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_HW_CONN_SRCCLKENA_EMI_DIS_MASK 0x10000000 // HW_CONN_SRCCLKENA_EMI_DIS[28]
#define CONN_CFG_EMI_PROBE_HW_CONN_SRCCLKENA_EMI_DIS_SHFT 28
#define CONN_CFG_EMI_PROBE_CONN2AP_EMI_ONLY_REQ_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_CONN2AP_EMI_ONLY_REQ_MASK 0x08000000 // CONN2AP_EMI_ONLY_REQ[27]
#define CONN_CFG_EMI_PROBE_CONN2AP_EMI_ONLY_REQ_SHFT 27
#define CONN_CFG_EMI_PROBE_DDR_TIMEOUT_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_DDR_TIMEOUT_MASK 0x04000000 // DDR_TIMEOUT[26]
#define CONN_CFG_EMI_PROBE_DDR_TIMEOUT_SHFT 26
#define CONN_CFG_EMI_PROBE_EMI_REQ_DIS_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_EMI_REQ_DIS_MASK 0x02000000 // EMI_REQ_DIS[25]
#define CONN_CFG_EMI_PROBE_EMI_REQ_DIS_SHFT 25
#define CONN_CFG_EMI_PROBE_EMI_REQ_ALL_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_EMI_REQ_ALL_MASK 0x01000000 // EMI_REQ_ALL[24]
#define CONN_CFG_EMI_PROBE_EMI_REQ_ALL_SHFT 24
#define CONN_CFG_EMI_PROBE_DDR_EN_STABLE_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_DDR_EN_STABLE_MASK 0x00800000 // DDR_EN_STABLE[23]
#define CONN_CFG_EMI_PROBE_DDR_EN_STABLE_SHFT 23
#define CONN_CFG_EMI_PROBE_AP_BUS_STABLE_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_AP_BUS_STABLE_MASK 0x00400000 // AP_BUS_STABLE[22]
#define CONN_CFG_EMI_PROBE_AP_BUS_STABLE_SHFT 22
#define CONN_CFG_EMI_PROBE_APSRC_STABLE_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_APSRC_STABLE_MASK 0x00200000 // APSRC_STABLE[21]
#define CONN_CFG_EMI_PROBE_APSRC_STABLE_SHFT 21
#define CONN_CFG_EMI_PROBE_SRCCLKENA_STABLE_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_SRCCLKENA_STABLE_MASK 0x00100000 // SRCCLKENA_STABLE[20]
#define CONN_CFG_EMI_PROBE_SRCCLKENA_STABLE_SHFT 20
#define CONN_CFG_EMI_PROBE_DDR_EN_STABLE_REG_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_DDR_EN_STABLE_REG_MASK 0x00080000 // DDR_EN_STABLE_REG[19]
#define CONN_CFG_EMI_PROBE_DDR_EN_STABLE_REG_SHFT 19
#define CONN_CFG_EMI_PROBE_AP_BUS_STABLE_REG_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_AP_BUS_STABLE_REG_MASK 0x00040000 // AP_BUS_STABLE_REG[18]
#define CONN_CFG_EMI_PROBE_AP_BUS_STABLE_REG_SHFT 18
#define CONN_CFG_EMI_PROBE_APSRC_STABLE_REG_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_APSRC_STABLE_REG_MASK 0x00020000 // APSRC_STABLE_REG[17]
#define CONN_CFG_EMI_PROBE_APSRC_STABLE_REG_SHFT 17
#define CONN_CFG_EMI_PROBE_SRCCLKENA_STABLE_REG_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_SRCCLKENA_STABLE_REG_MASK 0x00010000 // SRCCLKENA_STABLE_REG[16]
#define CONN_CFG_EMI_PROBE_SRCCLKENA_STABLE_REG_SHFT 16
#define CONN_CFG_EMI_PROBE_CONN2AP_BUS_EMI_SLPPROT_EN_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_CONN2AP_BUS_EMI_SLPPROT_EN_MASK 0x00008000 // CONN2AP_BUS_EMI_SLPPROT_EN[15]
#define CONN_CFG_EMI_PROBE_CONN2AP_BUS_EMI_SLPPROT_EN_SHFT 15
#define CONN_CFG_EMI_PROBE_CONN2AP_BUS_SLPPROT_EN_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_CONN2AP_BUS_SLPPROT_EN_MASK 0x00004000 // CONN2AP_BUS_SLPPROT_EN[14]
#define CONN_CFG_EMI_PROBE_CONN2AP_BUS_SLPPROT_EN_SHFT 14
#define CONN_CFG_EMI_PROBE_CONN_OFF2ON_REQ_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_CONN_OFF2ON_REQ_MASK 0x00002000 // CONN_OFF2ON_REQ[13]
#define CONN_CFG_EMI_PROBE_CONN_OFF2ON_REQ_SHFT 13
#define CONN_CFG_EMI_PROBE_CONN2AP_BUS_IDLE_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_CONN2AP_BUS_IDLE_MASK 0x00001000 // CONN2AP_BUS_IDLE[12]
#define CONN_CFG_EMI_PROBE_CONN2AP_BUS_IDLE_SHFT 12
#define CONN_CFG_EMI_PROBE_DDR_EN_ACK_SYNC_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_DDR_EN_ACK_SYNC_MASK 0x00000800 // DDR_EN_ACK_SYNC[11]
#define CONN_CFG_EMI_PROBE_DDR_EN_ACK_SYNC_SHFT 11
#define CONN_CFG_EMI_PROBE_APSRC_ACK_SYNC_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_APSRC_ACK_SYNC_MASK 0x00000400 // APSRC_ACK_SYNC[10]
#define CONN_CFG_EMI_PROBE_APSRC_ACK_SYNC_SHFT 10
#define CONN_CFG_EMI_PROBE_AP_BUS_ACK_SYNC_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_AP_BUS_ACK_SYNC_MASK 0x00000200 // AP_BUS_ACK_SYNC[9]
#define CONN_CFG_EMI_PROBE_AP_BUS_ACK_SYNC_SHFT 9
#define CONN_CFG_EMI_PROBE_SRCCLKENA_ACK_SYNC_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_SRCCLKENA_ACK_SYNC_MASK 0x00000100 // SRCCLKENA_ACK_SYNC[8]
#define CONN_CFG_EMI_PROBE_SRCCLKENA_ACK_SYNC_SHFT 8
#define CONN_CFG_EMI_PROBE_CONN_DDR_EN_ACK_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_CONN_DDR_EN_ACK_MASK 0x00000080 // CONN_DDR_EN_ACK[7]
#define CONN_CFG_EMI_PROBE_CONN_DDR_EN_ACK_SHFT 7
#define CONN_CFG_EMI_PROBE_CONN_APSRC_ACK_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_CONN_APSRC_ACK_MASK 0x00000040 // CONN_APSRC_ACK[6]
#define CONN_CFG_EMI_PROBE_CONN_APSRC_ACK_SHFT 6
#define CONN_CFG_EMI_PROBE_CONN_AP_BUS_ACK_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_CONN_AP_BUS_ACK_MASK 0x00000020 // CONN_AP_BUS_ACK[5]
#define CONN_CFG_EMI_PROBE_CONN_AP_BUS_ACK_SHFT 5
#define CONN_CFG_EMI_PROBE_CONN_SRCCCLKENA_ACK_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_CONN_SRCCCLKENA_ACK_MASK 0x00000010 // CONN_SRCCCLKENA_ACK[4]
#define CONN_CFG_EMI_PROBE_CONN_SRCCCLKENA_ACK_SHFT 4
#define CONN_CFG_EMI_PROBE_CONN_DDR_EN_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_CONN_DDR_EN_MASK 0x00000008 // CONN_DDR_EN[3]
#define CONN_CFG_EMI_PROBE_CONN_DDR_EN_SHFT 3
#define CONN_CFG_EMI_PROBE_CONN_APSRC_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_CONN_APSRC_MASK 0x00000004 // CONN_APSRC[2]
#define CONN_CFG_EMI_PROBE_CONN_APSRC_SHFT 2
#define CONN_CFG_EMI_PROBE_CONN_AP_BUS_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_CONN_AP_BUS_MASK 0x00000002 // CONN_AP_BUS[1]
#define CONN_CFG_EMI_PROBE_CONN_AP_BUS_SHFT 1
#define CONN_CFG_EMI_PROBE_CONN_SRCCCLKENA_ADDR CONN_CFG_EMI_PROBE_ADDR
#define CONN_CFG_EMI_PROBE_CONN_SRCCCLKENA_MASK 0x00000001 // CONN_SRCCCLKENA[0]
#define CONN_CFG_EMI_PROBE_CONN_SRCCCLKENA_SHFT 0
/* =====================================================================================
---EMI_PROBE_1 (0x18011000 + 0x134)---
EMI_PROBE_1[31..0] - (RO) xxx
=====================================================================================*/
#define CONN_CFG_EMI_PROBE_1_EMI_PROBE_1_ADDR CONN_CFG_EMI_PROBE_1_ADDR
#define CONN_CFG_EMI_PROBE_1_EMI_PROBE_1_MASK 0xFFFFFFFF // EMI_PROBE_1[31..0]
#define CONN_CFG_EMI_PROBE_1_EMI_PROBE_1_SHFT 0
#endif // __CONN_CFG_REGS_H__

3900
drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/CODA/conn_cfg_on.h Normal file
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1914
drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/CODA/conn_clkgen_top.h Normal file
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502
drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/CODA/conn_dbg_ctl.h Normal file
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@ -0,0 +1,502 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
//[File] : conn_dbg_ctl.h
//[Revision time] : Fri Jun 18 16:52:46 2021
//[Description] : This file is auto generated by CODA
//[Copyright] : Copyright (C) 2021 Mediatek Incorportion. All rights reserved.
#ifndef __CONN_DBG_CTL_REGS_H__
#define __CONN_DBG_CTL_REGS_H__
//****************************************************************************
//
// CONN_DBG_CTL CR Definitions
//
//****************************************************************************
#define CONN_DBG_CTL_BASE (CONN_REG_CONN_INFRA_DBG_CTL_ADDR) // 0x18023000
#define CONN_DBG_CTL_CLOCK_DETECT_ADDR (CONN_DBG_CTL_BASE + 0x000) // 3000
#define CONN_DBG_CTL_CONN_INFRA_MONFLAG_OUT_ADDR (CONN_DBG_CTL_BASE + 0x200) // 3200
#define CONN_DBG_CTL_CONN_INFRA_IO_TOP_DBG_SEL_ADDR (CONN_DBG_CTL_BASE + 0x204) // 3204
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_ADDR (CONN_DBG_CTL_BASE + 0x400) // 3400
#define CONN_DBG_CTL_CONN_INFRA_OFF_BUS_DBG_OUT_ADDR (CONN_DBG_CTL_BASE + 0x404) // 3404
#define CONN_DBG_CTL_CONN_INFRA_OFF_BUS_DBG_SEL_ADDR (CONN_DBG_CTL_BASE + 0x408) // 3408
#define CONN_DBG_CTL_CONN_INFRA_OFF_DEBUGSYS_CTRL_ADDR (CONN_DBG_CTL_BASE + 0x40C) // 340C
#define CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_INFO_ADDR (CONN_DBG_CTL_BASE + 0x410) // 3410
#define CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_ADDR_ADDR (CONN_DBG_CTL_BASE + 0x414) // 3414
#define CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_WDATA_ADDR (CONN_DBG_CTL_BASE + 0x418) // 3418
#define CONN_DBG_CTL_CONN_INFRA_VON_BUS_DEBUG_INFO_ADDR (CONN_DBG_CTL_BASE + 0x41C) // 341C
#define CONN_DBG_CTL_WF_MONFLAG_OFF_OUT_ADDR (CONN_DBG_CTL_BASE + 0x600) // 3600
#define CONN_DBG_CTL_WF_MCU_DBGOUT_SEL_ADDR (CONN_DBG_CTL_BASE + 0x604) // 3604
#define CONN_DBG_CTL_WF_MCU_GPR_BUS_DBGOUT_LOG_ADDR (CONN_DBG_CTL_BASE + 0x608) // 3608
#define CONN_DBG_CTL_WF_MCU_DBG_PC_LOG_SEL_ADDR (CONN_DBG_CTL_BASE + 0x60C) // 360C
#define CONN_DBG_CTL_WF_MCU_DBG_PC_LOG_ADDR (CONN_DBG_CTL_BASE + 0x610) // 3610
#define CONN_DBG_CTL_WF_MCU_DBG_GPR_LOG_SEL_ADDR (CONN_DBG_CTL_BASE + 0x614) // 3614
#define CONN_DBG_CTL_WF_MCU_DBG_EN_FR_HIF_ADDR (CONN_DBG_CTL_BASE + 0x618) // 3618
#define CONN_DBG_CTL_WF_MCU_DBG_SEL_FR_HIF_ADDR (CONN_DBG_CTL_BASE + 0x61C) // 361C
#define CONN_DBG_CTL_WF_CORE_PC_INDEX_FR_HIF_ADDR (CONN_DBG_CTL_BASE + 0x620) // 3620
#define CONN_DBG_CTL_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_DEBUGSYS_CTRL_ADDR (CONN_DBG_CTL_BASE + 0x628) // 3628
#define CONN_DBG_CTL_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_BUS_TIMEOUT_IRQ_ADDR (CONN_DBG_CTL_BASE + 0x62C) // 362C
#define CONN_DBG_CTL_BGF_MONFLAG_OFF_OUT_ADDR (CONN_DBG_CTL_BASE + 0xA00) // 3A00
#define CONN_DBG_CTL_CR_DBGCTL2BGF_OFF_DEBUG_SEL_ADDR (CONN_DBG_CTL_BASE + 0xA04) // 3A04
#define CONN_DBG_CTL_GPSAON2HOST_DEBUG_ADDR (CONN_DBG_CTL_BASE + 0xA08) // 3A08
#define CONN_DBG_CTL_DBG_BACKUP_0_ADDR (CONN_DBG_CTL_BASE + 0xE00) // 3E00
#define CONN_DBG_CTL_DBG_BACKUP_1_ADDR (CONN_DBG_CTL_BASE + 0xE04) // 3E04
#define CONN_DBG_CTL_DBG_BACKUP_2_ADDR (CONN_DBG_CTL_BASE + 0xE08) // 3E08
#define CONN_DBG_CTL_DBG_BACKUP_3_ADDR (CONN_DBG_CTL_BASE + 0xE0C) // 3E0C
#define CONN_DBG_CTL_DBG_BACKUP_4_ADDR (CONN_DBG_CTL_BASE + 0xE10) // 3E10
#define CONN_DBG_CTL_DBG_BACKUP_5_ADDR (CONN_DBG_CTL_BASE + 0xE14) // 3E14
#define CONN_DBG_CTL_DBG_BACKUP_6_ADDR (CONN_DBG_CTL_BASE + 0xE18) // 3E18
#define CONN_DBG_CTL_DBG_BACKUP_7_ADDR (CONN_DBG_CTL_BASE + 0xE1C) // 3E1C
#define CONN_DBG_CTL_CR_CONN_TEST_DO_SEL_ADDR (CONN_DBG_CTL_BASE + 0xE20) // 3E20
#define CONN_DBG_CTL_CR_AP2WF_HOST_ON_CFG_ADDR (CONN_DBG_CTL_BASE + 0xE24) // 3E24
/* =====================================================================================
---CLOCK_DETECT (0x18023000 + 0x000)---
CLK_DETECT_BUS_CLR_PULSE[0] - (WO) Host set this bit to reset bus detect state
This cr will generate a reset signal for bus clock detecion state
After write 1, you have to write 0 to release reset
HCLK_FR_CK_DETECT[1] - (RO) Connsys bus hclk detection status
0 : bus hclk non-alive
1 : bus hclk alive
User could write 1 to clear detection status.
After write 1 clear status and then read back to check clock status. It can check bus hclk alive or not.
OSC_CLK_DETECT[2] - (RO) Connsys osc clock detection status
0 : osc clock non-alive
1 : osc clock alive
User could write 1 to clear detection status.
After write 1 clear status and then read back to check clock status. It can check osc clock alive or not.
RESERVED3[31..3] - (RO) Reserved bits
=====================================================================================*/
#define CONN_DBG_CTL_CLOCK_DETECT_OSC_CLK_DETECT_ADDR CONN_DBG_CTL_CLOCK_DETECT_ADDR
#define CONN_DBG_CTL_CLOCK_DETECT_OSC_CLK_DETECT_MASK 0x00000004 // OSC_CLK_DETECT[2]
#define CONN_DBG_CTL_CLOCK_DETECT_OSC_CLK_DETECT_SHFT 2
#define CONN_DBG_CTL_CLOCK_DETECT_HCLK_FR_CK_DETECT_ADDR CONN_DBG_CTL_CLOCK_DETECT_ADDR
#define CONN_DBG_CTL_CLOCK_DETECT_HCLK_FR_CK_DETECT_MASK 0x00000002 // HCLK_FR_CK_DETECT[1]
#define CONN_DBG_CTL_CLOCK_DETECT_HCLK_FR_CK_DETECT_SHFT 1
#define CONN_DBG_CTL_CLOCK_DETECT_CLK_DETECT_BUS_CLR_PULSE_ADDR CONN_DBG_CTL_CLOCK_DETECT_ADDR
#define CONN_DBG_CTL_CLOCK_DETECT_CLK_DETECT_BUS_CLR_PULSE_MASK 0x00000001 // CLK_DETECT_BUS_CLR_PULSE[0]
#define CONN_DBG_CTL_CLOCK_DETECT_CLK_DETECT_BUS_CLR_PULSE_SHFT 0
/* =====================================================================================
---CONN_INFRA_MONFLAG_OUT (0x18023000 + 0x200)---
CONN_INFRA_MONFLAG_OUT[31..0] - (RO) xxx
=====================================================================================*/
#define CONN_DBG_CTL_CONN_INFRA_MONFLAG_OUT_CONN_INFRA_MONFLAG_OUT_ADDR CONN_DBG_CTL_CONN_INFRA_MONFLAG_OUT_ADDR
#define CONN_DBG_CTL_CONN_INFRA_MONFLAG_OUT_CONN_INFRA_MONFLAG_OUT_MASK 0xFFFFFFFF // CONN_INFRA_MONFLAG_OUT[31..0]
#define CONN_DBG_CTL_CONN_INFRA_MONFLAG_OUT_CONN_INFRA_MONFLAG_OUT_SHFT 0
/* =====================================================================================
---CONN_INFRA_IO_TOP_DBG_SEL (0x18023000 + 0x204)---
CONN_INFRA_IO_TOP_DBG_SEL[31..0] - (RW) xxx
=====================================================================================*/
#define CONN_DBG_CTL_CONN_INFRA_IO_TOP_DBG_SEL_CONN_INFRA_IO_TOP_DBG_SEL_ADDR CONN_DBG_CTL_CONN_INFRA_IO_TOP_DBG_SEL_ADDR
#define CONN_DBG_CTL_CONN_INFRA_IO_TOP_DBG_SEL_CONN_INFRA_IO_TOP_DBG_SEL_MASK 0xFFFFFFFF // CONN_INFRA_IO_TOP_DBG_SEL[31..0]
#define CONN_DBG_CTL_CONN_INFRA_IO_TOP_DBG_SEL_CONN_INFRA_IO_TOP_DBG_SEL_SHFT 0
/* =====================================================================================
---CONN_INFRA_BUS_TIMEOUT_IRQ (0x18023000 + 0x400)---
CONN_INFRA_OFF_BUS_TIMEOUT[0] - (RO) merge "CONN_INFRA_OFF_C6_TIMEOUT" & "CONN_INFRA_OFF_CONN2AP_TIMEOUT"
CONN_INFRA_OFF_VDNR_TIMEOUT_IRQ[1] - (RO) conn_infra_off_bus timeout (VDNR gen)
CONN_INFRA_OFF_AXI_LAYER_TIMEOUT[2] - (RO) conn_infra_off_axi_layer_bus timeout (hand-code)
CONN_INFRA_OFF_CONN2AP_TIMEOUT[3] - (RO) conn_infra_off_bus c12 AHB decoder timeout (hand-code)
CONN_INFRA_OFF_C6_TIMEOUT[4] - (RO) conn_infra_off_bus c6 AHB decoder timeout (hand-code)
CONN_VON_BUS_TIMEOUT[5] - (RO) conn_von_bus timeout (hand-code)
CONN_INFRA_ON_BUS_TIMEOUT_IRQ[6] - (RO) conn_infra_on_bus timeout (hand-code)
RESERVED7[31..7] - (RO) Reserved bits
=====================================================================================*/
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_ON_BUS_TIMEOUT_IRQ_ADDR CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_ADDR
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_ON_BUS_TIMEOUT_IRQ_MASK 0x00000040 // CONN_INFRA_ON_BUS_TIMEOUT_IRQ[6]
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_ON_BUS_TIMEOUT_IRQ_SHFT 6
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_VON_BUS_TIMEOUT_ADDR CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_ADDR
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_VON_BUS_TIMEOUT_MASK 0x00000020 // CONN_VON_BUS_TIMEOUT[5]
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_VON_BUS_TIMEOUT_SHFT 5
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_C6_TIMEOUT_ADDR CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_ADDR
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_C6_TIMEOUT_MASK 0x00000010 // CONN_INFRA_OFF_C6_TIMEOUT[4]
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_C6_TIMEOUT_SHFT 4
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_CONN2AP_TIMEOUT_ADDR CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_ADDR
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_CONN2AP_TIMEOUT_MASK 0x00000008 // CONN_INFRA_OFF_CONN2AP_TIMEOUT[3]
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_CONN2AP_TIMEOUT_SHFT 3
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_AXI_LAYER_TIMEOUT_ADDR CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_ADDR
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_AXI_LAYER_TIMEOUT_MASK 0x00000004 // CONN_INFRA_OFF_AXI_LAYER_TIMEOUT[2]
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_AXI_LAYER_TIMEOUT_SHFT 2
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_VDNR_TIMEOUT_IRQ_ADDR CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_ADDR
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_VDNR_TIMEOUT_IRQ_MASK 0x00000002 // CONN_INFRA_OFF_VDNR_TIMEOUT_IRQ[1]
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_VDNR_TIMEOUT_IRQ_SHFT 1
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_BUS_TIMEOUT_ADDR CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_ADDR
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_BUS_TIMEOUT_MASK 0x00000001 // CONN_INFRA_OFF_BUS_TIMEOUT[0]
#define CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_CONN_INFRA_OFF_BUS_TIMEOUT_SHFT 0
/* =====================================================================================
---CONN_INFRA_OFF_BUS_DBG_OUT (0x18023000 + 0x404)---
CONN_INFRA_OFF_BUS_DBG_OUT[31..0] - (RO) conn_infra_off_bus debug output (idle, gals_dbg, timeout_info)
=====================================================================================*/
#define CONN_DBG_CTL_CONN_INFRA_OFF_BUS_DBG_OUT_CONN_INFRA_OFF_BUS_DBG_OUT_ADDR CONN_DBG_CTL_CONN_INFRA_OFF_BUS_DBG_OUT_ADDR
#define CONN_DBG_CTL_CONN_INFRA_OFF_BUS_DBG_OUT_CONN_INFRA_OFF_BUS_DBG_OUT_MASK 0xFFFFFFFF // CONN_INFRA_OFF_BUS_DBG_OUT[31..0]
#define CONN_DBG_CTL_CONN_INFRA_OFF_BUS_DBG_OUT_CONN_INFRA_OFF_BUS_DBG_OUT_SHFT 0
/* =====================================================================================
---CONN_INFRA_OFF_BUS_DBG_SEL (0x18023000 + 0x408)---
CONN_INFRA_OFF_BUS_DBG_SEL[4..0] - (RW) conn_infra_off_bus debug selection
RESERVED5[31..5] - (RO) Reserved bits
=====================================================================================*/
#define CONN_DBG_CTL_CONN_INFRA_OFF_BUS_DBG_SEL_CONN_INFRA_OFF_BUS_DBG_SEL_ADDR CONN_DBG_CTL_CONN_INFRA_OFF_BUS_DBG_SEL_ADDR
#define CONN_DBG_CTL_CONN_INFRA_OFF_BUS_DBG_SEL_CONN_INFRA_OFF_BUS_DBG_SEL_MASK 0x0000001F // CONN_INFRA_OFF_BUS_DBG_SEL[4..0]
#define CONN_DBG_CTL_CONN_INFRA_OFF_BUS_DBG_SEL_CONN_INFRA_OFF_BUS_DBG_SEL_SHFT 0
/* =====================================================================================
---CONN_INFRA_OFF_DEBUGSYS_CTRL (0x18023000 + 0x40C)---
CONN_INFRA_OFF_DEBUGSYS_CTRL[31..0] - (RW) latch information when conn_von_bus timeout
=====================================================================================*/
#define CONN_DBG_CTL_CONN_INFRA_OFF_DEBUGSYS_CTRL_CONN_INFRA_OFF_DEBUGSYS_CTRL_ADDR CONN_DBG_CTL_CONN_INFRA_OFF_DEBUGSYS_CTRL_ADDR
#define CONN_DBG_CTL_CONN_INFRA_OFF_DEBUGSYS_CTRL_CONN_INFRA_OFF_DEBUGSYS_CTRL_MASK 0xFFFFFFFF // CONN_INFRA_OFF_DEBUGSYS_CTRL[31..0]
#define CONN_DBG_CTL_CONN_INFRA_OFF_DEBUGSYS_CTRL_CONN_INFRA_OFF_DEBUGSYS_CTRL_SHFT 0
/* =====================================================================================
---CONN_VON_BUS_APB_TIMEOUT_INFO (0x18023000 + 0x410)---
CONN_VON_BUS_APB_TIMEOUT_INFO[31..0] - (RO) latch information when conn_von_bus timeout
=====================================================================================*/
#define CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_INFO_CONN_VON_BUS_APB_TIMEOUT_INFO_ADDR CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_INFO_ADDR
#define CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_INFO_CONN_VON_BUS_APB_TIMEOUT_INFO_MASK 0xFFFFFFFF // CONN_VON_BUS_APB_TIMEOUT_INFO[31..0]
#define CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_INFO_CONN_VON_BUS_APB_TIMEOUT_INFO_SHFT 0
/* =====================================================================================
---CONN_VON_BUS_APB_TIMEOUT_ADDR (0x18023000 + 0x414)---
CONN_VON_BUS_APB_TIMEOUT_ADDR[31..0] - (RO) latch information when conn_von_bus timeout
=====================================================================================*/
#define CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_ADDR_CONN_VON_BUS_APB_TIMEOUT_ADDR_ADDR CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_ADDR_ADDR
#define CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_ADDR_CONN_VON_BUS_APB_TIMEOUT_ADDR_MASK 0xFFFFFFFF // CONN_VON_BUS_APB_TIMEOUT_ADDR[31..0]
#define CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_ADDR_CONN_VON_BUS_APB_TIMEOUT_ADDR_SHFT 0
/* =====================================================================================
---CONN_VON_BUS_APB_TIMEOUT_WDATA (0x18023000 + 0x418)---
CONN_VON_BUS_APB_TIMEOUT_WDATA[31..0] - (RO) latch information when conn_von_bus timeout
=====================================================================================*/
#define CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_WDATA_CONN_VON_BUS_APB_TIMEOUT_WDATA_ADDR CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_WDATA_ADDR
#define CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_WDATA_CONN_VON_BUS_APB_TIMEOUT_WDATA_MASK 0xFFFFFFFF // CONN_VON_BUS_APB_TIMEOUT_WDATA[31..0]
#define CONN_DBG_CTL_CONN_VON_BUS_APB_TIMEOUT_WDATA_CONN_VON_BUS_APB_TIMEOUT_WDATA_SHFT 0
/* =====================================================================================
---CONN_INFRA_VON_BUS_DEBUG_INFO (0x18023000 + 0x41C)---
CONN_INFRA_VON_BUS_DEBUG_INFO[31..0] - (RO) conn_von_bus debug information
=====================================================================================*/
#define CONN_DBG_CTL_CONN_INFRA_VON_BUS_DEBUG_INFO_CONN_INFRA_VON_BUS_DEBUG_INFO_ADDR CONN_DBG_CTL_CONN_INFRA_VON_BUS_DEBUG_INFO_ADDR
#define CONN_DBG_CTL_CONN_INFRA_VON_BUS_DEBUG_INFO_CONN_INFRA_VON_BUS_DEBUG_INFO_MASK 0xFFFFFFFF // CONN_INFRA_VON_BUS_DEBUG_INFO[31..0]
#define CONN_DBG_CTL_CONN_INFRA_VON_BUS_DEBUG_INFO_CONN_INFRA_VON_BUS_DEBUG_INFO_SHFT 0
/* =====================================================================================
---WF_MONFLAG_OFF_OUT (0x18023000 + 0x600)---
WF_MONFLAG_OFF_OUT[31..0] - (RO) xxx
=====================================================================================*/
#define CONN_DBG_CTL_WF_MONFLAG_OFF_OUT_WF_MONFLAG_OFF_OUT_ADDR CONN_DBG_CTL_WF_MONFLAG_OFF_OUT_ADDR
#define CONN_DBG_CTL_WF_MONFLAG_OFF_OUT_WF_MONFLAG_OFF_OUT_MASK 0xFFFFFFFF // WF_MONFLAG_OFF_OUT[31..0]
#define CONN_DBG_CTL_WF_MONFLAG_OFF_OUT_WF_MONFLAG_OFF_OUT_SHFT 0
/* =====================================================================================
---WF_MCU_DBGOUT_SEL (0x18023000 + 0x604)---
WF_MCU_DBGOUT_SEL[2..0] - (RW) xxx
RESERVED3[31..3] - (RO) Reserved bits
=====================================================================================*/
#define CONN_DBG_CTL_WF_MCU_DBGOUT_SEL_WF_MCU_DBGOUT_SEL_ADDR CONN_DBG_CTL_WF_MCU_DBGOUT_SEL_ADDR
#define CONN_DBG_CTL_WF_MCU_DBGOUT_SEL_WF_MCU_DBGOUT_SEL_MASK 0x00000007 // WF_MCU_DBGOUT_SEL[2..0]
#define CONN_DBG_CTL_WF_MCU_DBGOUT_SEL_WF_MCU_DBGOUT_SEL_SHFT 0
/* =====================================================================================
---WF_MCU_GPR_BUS_DBGOUT_LOG (0x18023000 + 0x608)---
WF_MCU_GPR_BUS_DBGOUT_LOG[31..0] - (RO) select by "WF_MCU_DBGOUT_SEL"
=====================================================================================*/
#define CONN_DBG_CTL_WF_MCU_GPR_BUS_DBGOUT_LOG_WF_MCU_GPR_BUS_DBGOUT_LOG_ADDR CONN_DBG_CTL_WF_MCU_GPR_BUS_DBGOUT_LOG_ADDR
#define CONN_DBG_CTL_WF_MCU_GPR_BUS_DBGOUT_LOG_WF_MCU_GPR_BUS_DBGOUT_LOG_MASK 0xFFFFFFFF // WF_MCU_GPR_BUS_DBGOUT_LOG[31..0]
#define CONN_DBG_CTL_WF_MCU_GPR_BUS_DBGOUT_LOG_WF_MCU_GPR_BUS_DBGOUT_LOG_SHFT 0
/* =====================================================================================
---WF_MCU_DBG_PC_LOG_SEL (0x18023000 + 0x60C)---
WF_MCU_DBG_PC_LOG_SEL[5..0] - (RW) xxx
RESERVED6[31..6] - (RO) Reserved bits
=====================================================================================*/
#define CONN_DBG_CTL_WF_MCU_DBG_PC_LOG_SEL_WF_MCU_DBG_PC_LOG_SEL_ADDR CONN_DBG_CTL_WF_MCU_DBG_PC_LOG_SEL_ADDR
#define CONN_DBG_CTL_WF_MCU_DBG_PC_LOG_SEL_WF_MCU_DBG_PC_LOG_SEL_MASK 0x0000003F // WF_MCU_DBG_PC_LOG_SEL[5..0]
#define CONN_DBG_CTL_WF_MCU_DBG_PC_LOG_SEL_WF_MCU_DBG_PC_LOG_SEL_SHFT 0
/* =====================================================================================
---WF_MCU_DBG_PC_LOG (0x18023000 + 0x610)---
WF_MCU_DBG_PC_LOG[31..0] - (RO) select by "WF_MCU_DBG_PC_LOG_SEL"
=====================================================================================*/
#define CONN_DBG_CTL_WF_MCU_DBG_PC_LOG_WF_MCU_DBG_PC_LOG_ADDR CONN_DBG_CTL_WF_MCU_DBG_PC_LOG_ADDR
#define CONN_DBG_CTL_WF_MCU_DBG_PC_LOG_WF_MCU_DBG_PC_LOG_MASK 0xFFFFFFFF // WF_MCU_DBG_PC_LOG[31..0]
#define CONN_DBG_CTL_WF_MCU_DBG_PC_LOG_WF_MCU_DBG_PC_LOG_SHFT 0
/* =====================================================================================
---WF_MCU_DBG_GPR_LOG_SEL (0x18023000 + 0x614)---
WF_MCU_DBG_GPR_LOG_SEL[5..0] - (RW) xxx
RESERVED6[31..6] - (RO) Reserved bits
=====================================================================================*/
#define CONN_DBG_CTL_WF_MCU_DBG_GPR_LOG_SEL_WF_MCU_DBG_GPR_LOG_SEL_ADDR CONN_DBG_CTL_WF_MCU_DBG_GPR_LOG_SEL_ADDR
#define CONN_DBG_CTL_WF_MCU_DBG_GPR_LOG_SEL_WF_MCU_DBG_GPR_LOG_SEL_MASK 0x0000003F // WF_MCU_DBG_GPR_LOG_SEL[5..0]
#define CONN_DBG_CTL_WF_MCU_DBG_GPR_LOG_SEL_WF_MCU_DBG_GPR_LOG_SEL_SHFT 0
/* =====================================================================================
---WF_MCU_DBG_EN_FR_HIF (0x18023000 + 0x618)---
WF_MCU_DBG_EN_FR_HIF[0] - (RW) xxx
RESERVED1[31..1] - (RO) Reserved bits
=====================================================================================*/
#define CONN_DBG_CTL_WF_MCU_DBG_EN_FR_HIF_WF_MCU_DBG_EN_FR_HIF_ADDR CONN_DBG_CTL_WF_MCU_DBG_EN_FR_HIF_ADDR
#define CONN_DBG_CTL_WF_MCU_DBG_EN_FR_HIF_WF_MCU_DBG_EN_FR_HIF_MASK 0x00000001 // WF_MCU_DBG_EN_FR_HIF[0]
#define CONN_DBG_CTL_WF_MCU_DBG_EN_FR_HIF_WF_MCU_DBG_EN_FR_HIF_SHFT 0
/* =====================================================================================
---WF_MCU_DBG_SEL_FR_HIF (0x18023000 + 0x61C)---
WF_MCU_DBG_SEL_FR_HIF[27..0] - (RW) xxx
RESERVED28[31..28] - (RO) Reserved bits
=====================================================================================*/
#define CONN_DBG_CTL_WF_MCU_DBG_SEL_FR_HIF_WF_MCU_DBG_SEL_FR_HIF_ADDR CONN_DBG_CTL_WF_MCU_DBG_SEL_FR_HIF_ADDR
#define CONN_DBG_CTL_WF_MCU_DBG_SEL_FR_HIF_WF_MCU_DBG_SEL_FR_HIF_MASK 0x0FFFFFFF // WF_MCU_DBG_SEL_FR_HIF[27..0]
#define CONN_DBG_CTL_WF_MCU_DBG_SEL_FR_HIF_WF_MCU_DBG_SEL_FR_HIF_SHFT 0
/* =====================================================================================
---WF_CORE_PC_INDEX_FR_HIF (0x18023000 + 0x620)---
WF_CORE_PC_INDEX_FR_HIF[5..0] - (RW) xxx
RESERVED6[31..6] - (RO) Reserved bits
=====================================================================================*/
#define CONN_DBG_CTL_WF_CORE_PC_INDEX_FR_HIF_WF_CORE_PC_INDEX_FR_HIF_ADDR CONN_DBG_CTL_WF_CORE_PC_INDEX_FR_HIF_ADDR
#define CONN_DBG_CTL_WF_CORE_PC_INDEX_FR_HIF_WF_CORE_PC_INDEX_FR_HIF_MASK 0x0000003F // WF_CORE_PC_INDEX_FR_HIF[5..0]
#define CONN_DBG_CTL_WF_CORE_PC_INDEX_FR_HIF_WF_CORE_PC_INDEX_FR_HIF_SHFT 0
/* =====================================================================================
---WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_DEBUGSYS_CTRL (0x18023000 + 0x628)---
WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_DEBUGSYS_CTRL[31..0] - (RW) xxx
=====================================================================================*/
#define CONN_DBG_CTL_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_DEBUGSYS_CTRL_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_DEBUGSYS_CTRL_ADDR CONN_DBG_CTL_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_DEBUGSYS_CTRL_ADDR
#define CONN_DBG_CTL_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_DEBUGSYS_CTRL_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_DEBUGSYS_CTRL_MASK 0xFFFFFFFF // WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_DEBUGSYS_CTRL[31..0]
#define CONN_DBG_CTL_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_DEBUGSYS_CTRL_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_DEBUGSYS_CTRL_SHFT 0
/* =====================================================================================
---WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_BUS_TIMEOUT_IRQ (0x18023000 + 0x62C)---
WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_BUS_TIMEOUT_IRQ[0] - (RO) xxx
RESERVED1[31..1] - (RO) Reserved bits
=====================================================================================*/
#define CONN_DBG_CTL_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_BUS_TIMEOUT_IRQ_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_BUS_TIMEOUT_IRQ_ADDR CONN_DBG_CTL_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_BUS_TIMEOUT_IRQ_ADDR
#define CONN_DBG_CTL_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_BUS_TIMEOUT_IRQ_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_BUS_TIMEOUT_IRQ_MASK 0x00000001 // WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_BUS_TIMEOUT_IRQ[0]
#define CONN_DBG_CTL_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_BUS_TIMEOUT_IRQ_WF_MCUSYS_INFRA_VDNR_GEN_DEBUG_CTRL_AO_BUS_TIMEOUT_IRQ_SHFT 0
/* =====================================================================================
---BGF_MONFLAG_OFF_OUT (0x18023000 + 0xA00)---
BGF_MONFLAG_OFF_OUT[31..0] - (RO) select by "CR_DBGCTL2BGF_OFF_DEBUG_SEL"
=====================================================================================*/
#define CONN_DBG_CTL_BGF_MONFLAG_OFF_OUT_BGF_MONFLAG_OFF_OUT_ADDR CONN_DBG_CTL_BGF_MONFLAG_OFF_OUT_ADDR
#define CONN_DBG_CTL_BGF_MONFLAG_OFF_OUT_BGF_MONFLAG_OFF_OUT_MASK 0xFFFFFFFF // BGF_MONFLAG_OFF_OUT[31..0]
#define CONN_DBG_CTL_BGF_MONFLAG_OFF_OUT_BGF_MONFLAG_OFF_OUT_SHFT 0
/* =====================================================================================
---CR_DBGCTL2BGF_OFF_DEBUG_SEL (0x18023000 + 0xA04)---
CR_DBGCTL2BGF_OFF_DEBUG_SEL[31..0] - (RW) xxx
=====================================================================================*/
#define CONN_DBG_CTL_CR_DBGCTL2BGF_OFF_DEBUG_SEL_CR_DBGCTL2BGF_OFF_DEBUG_SEL_ADDR CONN_DBG_CTL_CR_DBGCTL2BGF_OFF_DEBUG_SEL_ADDR
#define CONN_DBG_CTL_CR_DBGCTL2BGF_OFF_DEBUG_SEL_CR_DBGCTL2BGF_OFF_DEBUG_SEL_MASK 0xFFFFFFFF // CR_DBGCTL2BGF_OFF_DEBUG_SEL[31..0]
#define CONN_DBG_CTL_CR_DBGCTL2BGF_OFF_DEBUG_SEL_CR_DBGCTL2BGF_OFF_DEBUG_SEL_SHFT 0
/* =====================================================================================
---GPSAON2HOST_DEBUG (0x18023000 + 0xA08)---
GPSAON2HOST_DEBUG[11..0] - (RO) xxx
RESERVED12[31..12] - (RO) Reserved bits
=====================================================================================*/
#define CONN_DBG_CTL_GPSAON2HOST_DEBUG_GPSAON2HOST_DEBUG_ADDR CONN_DBG_CTL_GPSAON2HOST_DEBUG_ADDR
#define CONN_DBG_CTL_GPSAON2HOST_DEBUG_GPSAON2HOST_DEBUG_MASK 0x00000FFF // GPSAON2HOST_DEBUG[11..0]
#define CONN_DBG_CTL_GPSAON2HOST_DEBUG_GPSAON2HOST_DEBUG_SHFT 0
/* =====================================================================================
---DBG_BACKUP_0 (0x18023000 + 0xE00)---
DBG_BACKUP_0[31..0] - (RO) backup un-use
=====================================================================================*/
#define CONN_DBG_CTL_DBG_BACKUP_0_DBG_BACKUP_0_ADDR CONN_DBG_CTL_DBG_BACKUP_0_ADDR
#define CONN_DBG_CTL_DBG_BACKUP_0_DBG_BACKUP_0_MASK 0xFFFFFFFF // DBG_BACKUP_0[31..0]
#define CONN_DBG_CTL_DBG_BACKUP_0_DBG_BACKUP_0_SHFT 0
/* =====================================================================================
---DBG_BACKUP_1 (0x18023000 + 0xE04)---
DBG_BACKUP_1[31..0] - (RO) backup un-use
=====================================================================================*/
#define CONN_DBG_CTL_DBG_BACKUP_1_DBG_BACKUP_1_ADDR CONN_DBG_CTL_DBG_BACKUP_1_ADDR
#define CONN_DBG_CTL_DBG_BACKUP_1_DBG_BACKUP_1_MASK 0xFFFFFFFF // DBG_BACKUP_1[31..0]
#define CONN_DBG_CTL_DBG_BACKUP_1_DBG_BACKUP_1_SHFT 0
/* =====================================================================================
---DBG_BACKUP_2 (0x18023000 + 0xE08)---
DBG_BACKUP_2[31..0] - (RO) backup un-use
=====================================================================================*/
#define CONN_DBG_CTL_DBG_BACKUP_2_DBG_BACKUP_2_ADDR CONN_DBG_CTL_DBG_BACKUP_2_ADDR
#define CONN_DBG_CTL_DBG_BACKUP_2_DBG_BACKUP_2_MASK 0xFFFFFFFF // DBG_BACKUP_2[31..0]
#define CONN_DBG_CTL_DBG_BACKUP_2_DBG_BACKUP_2_SHFT 0
/* =====================================================================================
---DBG_BACKUP_3 (0x18023000 + 0xE0C)---
DBG_BACKUP_3[31..0] - (RO) backup un-use
=====================================================================================*/
#define CONN_DBG_CTL_DBG_BACKUP_3_DBG_BACKUP_3_ADDR CONN_DBG_CTL_DBG_BACKUP_3_ADDR
#define CONN_DBG_CTL_DBG_BACKUP_3_DBG_BACKUP_3_MASK 0xFFFFFFFF // DBG_BACKUP_3[31..0]
#define CONN_DBG_CTL_DBG_BACKUP_3_DBG_BACKUP_3_SHFT 0
/* =====================================================================================
---DBG_BACKUP_4 (0x18023000 + 0xE10)---
DBG_BACKUP_4[31..0] - (RO) backup un-use
=====================================================================================*/
#define CONN_DBG_CTL_DBG_BACKUP_4_DBG_BACKUP_4_ADDR CONN_DBG_CTL_DBG_BACKUP_4_ADDR
#define CONN_DBG_CTL_DBG_BACKUP_4_DBG_BACKUP_4_MASK 0xFFFFFFFF // DBG_BACKUP_4[31..0]
#define CONN_DBG_CTL_DBG_BACKUP_4_DBG_BACKUP_4_SHFT 0
/* =====================================================================================
---DBG_BACKUP_5 (0x18023000 + 0xE14)---
DBG_BACKUP_5[31..0] - (RO) backup un-use
=====================================================================================*/
#define CONN_DBG_CTL_DBG_BACKUP_5_DBG_BACKUP_5_ADDR CONN_DBG_CTL_DBG_BACKUP_5_ADDR
#define CONN_DBG_CTL_DBG_BACKUP_5_DBG_BACKUP_5_MASK 0xFFFFFFFF // DBG_BACKUP_5[31..0]
#define CONN_DBG_CTL_DBG_BACKUP_5_DBG_BACKUP_5_SHFT 0
/* =====================================================================================
---DBG_BACKUP_6 (0x18023000 + 0xE18)---
DBG_BACKUP_6[31..0] - (RO) backup un-use
=====================================================================================*/
#define CONN_DBG_CTL_DBG_BACKUP_6_DBG_BACKUP_6_ADDR CONN_DBG_CTL_DBG_BACKUP_6_ADDR
#define CONN_DBG_CTL_DBG_BACKUP_6_DBG_BACKUP_6_MASK 0xFFFFFFFF // DBG_BACKUP_6[31..0]
#define CONN_DBG_CTL_DBG_BACKUP_6_DBG_BACKUP_6_SHFT 0
/* =====================================================================================
---DBG_BACKUP_7 (0x18023000 + 0xE1C)---
DBG_BACKUP_7[31..0] - (RO) backup un-use
=====================================================================================*/
#define CONN_DBG_CTL_DBG_BACKUP_7_DBG_BACKUP_7_ADDR CONN_DBG_CTL_DBG_BACKUP_7_ADDR
#define CONN_DBG_CTL_DBG_BACKUP_7_DBG_BACKUP_7_MASK 0xFFFFFFFF // DBG_BACKUP_7[31..0]
#define CONN_DBG_CTL_DBG_BACKUP_7_DBG_BACKUP_7_SHFT 0
/* =====================================================================================
---CR_CONN_TEST_DO_SEL (0x18023000 + 0xE20)---
CR_CONN_TEST_DO_SEL[31..0] - (RW) xxx
=====================================================================================*/
#define CONN_DBG_CTL_CR_CONN_TEST_DO_SEL_CR_CONN_TEST_DO_SEL_ADDR CONN_DBG_CTL_CR_CONN_TEST_DO_SEL_ADDR
#define CONN_DBG_CTL_CR_CONN_TEST_DO_SEL_CR_CONN_TEST_DO_SEL_MASK 0xFFFFFFFF // CR_CONN_TEST_DO_SEL[31..0]
#define CONN_DBG_CTL_CR_CONN_TEST_DO_SEL_CR_CONN_TEST_DO_SEL_SHFT 0
/* =====================================================================================
---CR_AP2WF_HOST_ON_CFG (0x18023000 + 0xE24)---
CR_AP2WF_HOST_ON_CFG[15..0] - (RW) xxx
RESERVED16[31..16] - (RO) Reserved bits
=====================================================================================*/
#define CONN_DBG_CTL_CR_AP2WF_HOST_ON_CFG_CR_AP2WF_HOST_ON_CFG_ADDR CONN_DBG_CTL_CR_AP2WF_HOST_ON_CFG_ADDR
#define CONN_DBG_CTL_CR_AP2WF_HOST_ON_CFG_CR_AP2WF_HOST_ON_CFG_MASK 0x0000FFFF // CR_AP2WF_HOST_ON_CFG[15..0]
#define CONN_DBG_CTL_CR_AP2WF_HOST_ON_CFG_CR_AP2WF_HOST_ON_CFG_SHFT 0
#endif // __CONN_DBG_CTL_REGS_H__

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drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/CODA/conn_host_csr_top.h Normal file
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drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/CODA/conn_off_debug_ctrl_ao.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
//[File] : conn_off_debug_ctrl_ao.h
//[Revision time] : Fri Jun 18 16:52:54 2021
//[Description] : This file is auto generated by CODA
//[Copyright] : Copyright (C) 2021 Mediatek Incorportion. All rights reserved.
#ifndef __CONN_OFF_DEBUG_CTRL_AO_REGS_H__
#define __CONN_OFF_DEBUG_CTRL_AO_REGS_H__
//****************************************************************************
//
// CONN_OFF_DEBUG_CTRL_AO CR Definitions
//
//****************************************************************************
#define CONN_OFF_DEBUG_CTRL_AO_BASE (CONN_REG_CONN_INFRA_OFF_DEBUG_CTRL_AO_ADDR) // 0x1804D000
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_ADDR (CONN_OFF_DEBUG_CTRL_AO_BASE + 0x000) // D000
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL1_ADDR (CONN_OFF_DEBUG_CTRL_AO_BASE + 0x004) // D004
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL2_ADDR (CONN_OFF_DEBUG_CTRL_AO_BASE + 0x008) // D008
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT0_ADDR (CONN_OFF_DEBUG_CTRL_AO_BASE + 0x400) // D400
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT1_ADDR (CONN_OFF_DEBUG_CTRL_AO_BASE + 0x404) // D404
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT2_ADDR (CONN_OFF_DEBUG_CTRL_AO_BASE + 0x408) // D408
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT3_ADDR (CONN_OFF_DEBUG_CTRL_AO_BASE + 0x40C) // D40C
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT4_ADDR (CONN_OFF_DEBUG_CTRL_AO_BASE + 0x410) // D410
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT5_ADDR (CONN_OFF_DEBUG_CTRL_AO_BASE + 0x414) // D414
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT6_ADDR (CONN_OFF_DEBUG_CTRL_AO_BASE + 0x418) // D418
/* =====================================================================================
---CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0 (0x1804D000 + 0x000)---
timeout[0] - (RO) Timeout
timeout_type[1] - (RW) Method of timeout record
debug_en[2] - (RW) xxx
debug_cken[3] - (RW) xxx
debug_en_debugtop[4] - (RW) xxx
clk_detect[7..5] - (RO) xxx
timeout_irq[8] - (RO) xxx
timeout_clr[9] - (RW) xxx
RESERVED10[15..10] - (RO) Reserved bits
timeout_thres[31..16] - (RW) Setting timeout threshold
=====================================================================================*/
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_thres_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_thres_MASK 0xFFFF0000 // timeout_thres[31..16]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_thres_SHFT 16
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_clr_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_clr_MASK 0x00000200 // timeout_clr[9]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_clr_SHFT 9
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_irq_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_irq_MASK 0x00000100 // timeout_irq[8]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_irq_SHFT 8
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_clk_detect_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_clk_detect_MASK 0x000000E0 // clk_detect[7..5]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_clk_detect_SHFT 5
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_debug_en_debugtop_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_debug_en_debugtop_MASK 0x00000010 // debug_en_debugtop[4]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_debug_en_debugtop_SHFT 4
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_debug_cken_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_debug_cken_MASK 0x00000008 // debug_cken[3]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_debug_cken_SHFT 3
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_debug_en_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_debug_en_MASK 0x00000004 // debug_en[2]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_debug_en_SHFT 2
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_type_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_type_MASK 0x00000002 // timeout_type[1]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_type_SHFT 1
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_MASK 0x00000001 // timeout[0]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_timeout_SHFT 0
/* =====================================================================================
---CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL1 (0x1804D000 + 0x004)---
idle0_mask[31..0] - (RW) Mask idle0 trigger
=====================================================================================*/
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL1_idle0_mask_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL1_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL1_idle0_mask_MASK 0xFFFFFFFF // idle0_mask[31..0]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL1_idle0_mask_SHFT 0
/* =====================================================================================
---CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL2 (0x1804D000 + 0x008)---
idle1_mask[0] - (RW) Mask idle1 trigger
RESERVED1[31..1] - (RO) Reserved bits
=====================================================================================*/
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL2_idle1_mask_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL2_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL2_idle1_mask_MASK 0x00000001 // idle1_mask[0]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL2_idle1_mask_SHFT 0
/* =====================================================================================
---CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT0 (0x1804D000 + 0x400)---
sys_timer_value_0[31..0] - (RO) Time stamp values
=====================================================================================*/
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT0_sys_timer_value_0_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT0_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT0_sys_timer_value_0_MASK 0xFFFFFFFF // sys_timer_value_0[31..0]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT0_sys_timer_value_0_SHFT 0
/* =====================================================================================
---CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT1 (0x1804D000 + 0x404)---
sys_timer_value_1[31..0] - (RO) Time stamp values
=====================================================================================*/
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT1_sys_timer_value_1_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT1_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT1_sys_timer_value_1_MASK 0xFFFFFFFF // sys_timer_value_1[31..0]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT1_sys_timer_value_1_SHFT 0
/* =====================================================================================
---CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT2 (0x1804D000 + 0x408)---
debug_result2[31..0] - (RO) debug signal values
=====================================================================================*/
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT2_debug_result2_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT2_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT2_debug_result2_MASK 0xFFFFFFFF // debug_result2[31..0]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT2_debug_result2_SHFT 0
/* =====================================================================================
---CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT3 (0x1804D000 + 0x40C)---
debug_result3[31..0] - (RO) debug signal values
=====================================================================================*/
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT3_debug_result3_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT3_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT3_debug_result3_MASK 0xFFFFFFFF // debug_result3[31..0]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT3_debug_result3_SHFT 0
/* =====================================================================================
---CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT4 (0x1804D000 + 0x410)---
debug_result4[31..0] - (RO) debug signal values
=====================================================================================*/
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT4_debug_result4_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT4_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT4_debug_result4_MASK 0xFFFFFFFF // debug_result4[31..0]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT4_debug_result4_SHFT 0
/* =====================================================================================
---CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT5 (0x1804D000 + 0x414)---
debug_result5[31..0] - (RO) debug signal values
=====================================================================================*/
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT5_debug_result5_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT5_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT5_debug_result5_MASK 0xFFFFFFFF // debug_result5[31..0]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT5_debug_result5_SHFT 0
/* =====================================================================================
---CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT6 (0x1804D000 + 0x418)---
debug_result6[31..0] - (RO) debug signal values
=====================================================================================*/
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT6_debug_result6_ADDR CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT6_ADDR
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT6_debug_result6_MASK 0xFFFFFFFF // debug_result6[31..0]
#define CONN_OFF_DEBUG_CTRL_AO_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_RESULT6_debug_result6_SHFT 0
#endif // __CONN_OFF_DEBUG_CTRL_AO_REGS_H__

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
//[File] : conn_on_bus_bcrm.h
//[Revision time] : Fri Jun 18 16:52:52 2021
//[Description] : This file is auto generated by CODA
//[Copyright] : Copyright (C) 2021 Mediatek Incorportion. All rights reserved.
#ifndef __CONN_ON_BUS_BCRM_REGS_H__
#define __CONN_ON_BUS_BCRM_REGS_H__
//****************************************************************************
//
// CONN_ON_BUS_BCRM CR Definitions
//
//****************************************************************************
#define CONN_ON_BUS_BCRM_BASE (CONN_REG_CONN_INFRA_ON_BUS_BCRM_ADDR) // 0x1803B000
#define CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_lnk_von2on_apb_to_conn_infra_on_host_bus_kh0_APB_GALS_RX_CTRL_0_ADDR (CONN_ON_BUS_BCRM_BASE + 0x000) // B000
#define CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_kh0_CTRL_0_ADDR (CONN_ON_BUS_BCRM_BASE + 0x004) // B004
#define CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_kh1_CTRL_0_ADDR (CONN_ON_BUS_BCRM_BASE + 0x008) // B008
#define CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_lnk_off2on_apb_to_conn_infra_on_conn_bus_kc0_APB_GALS_RX_CTRL_0_ADDR (CONN_ON_BUS_BCRM_BASE + 0x00c) // B00C
#define CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_kc0_CTRL_0_ADDR (CONN_ON_BUS_BCRM_BASE + 0x010) // B010
#define CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_kc1_CTRL_0_ADDR (CONN_ON_BUS_BCRM_BASE + 0x014) // B014
/* =====================================================================================
---conn_infra_on_host_bus_u_lnk_von2on_apb_to_conn_infra_on_host_bus_kh0_APB_GALS_RX_CTRL_0 (0x1803B000 + 0x000)---
conn_infra_on_host_bus__u_lnk_von2on_apb_to_conn_infra_on_host_bus_kh0_APB_GALS_RX__rx_clock_cg_en[0] - (RW) xxx
RESERVED1[31..1] - (RO) Reserved bits
=====================================================================================*/
#define CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_lnk_von2on_apb_to_conn_infra_on_host_bus_kh0_APB_GALS_RX_CTRL_0_conn_infra_on_host_bus__u_lnk_von2on_apb_to_conn_infra_on_host_bus_kh0_APB_GALS_RX__rx_clock_cg_en_ADDR CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_lnk_von2on_apb_to_conn_infra_on_host_bus_kh0_APB_GALS_RX_CTRL_0_ADDR
#define CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_lnk_von2on_apb_to_conn_infra_on_host_bus_kh0_APB_GALS_RX_CTRL_0_conn_infra_on_host_bus__u_lnk_von2on_apb_to_conn_infra_on_host_bus_kh0_APB_GALS_RX__rx_clock_cg_en_MASK 0x00000001 // conn_infra_on_host_bus__u_lnk_von2on_apb_to_conn_infra_on_host_bus_kh0_APB_GALS_RX__rx_clock_cg_en[0]
#define CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_lnk_von2on_apb_to_conn_infra_on_host_bus_kh0_APB_GALS_RX_CTRL_0_conn_infra_on_host_bus__u_lnk_von2on_apb_to_conn_infra_on_host_bus_kh0_APB_GALS_RX__rx_clock_cg_en_SHFT 0
/* =====================================================================================
---conn_infra_on_host_bus_u_kh0_CTRL_0 (0x1803B000 + 0x004)---
conn_infra_on_host_bus__u_kh0__way_en[1..0] - (RW) xxx
RESERVED2[31..2] - (RO) Reserved bits
=====================================================================================*/
#define CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_kh0_CTRL_0_conn_infra_on_host_bus__u_kh0__way_en_ADDR CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_kh0_CTRL_0_ADDR
#define CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_kh0_CTRL_0_conn_infra_on_host_bus__u_kh0__way_en_MASK 0x00000003 // conn_infra_on_host_bus__u_kh0__way_en[1..0]
#define CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_kh0_CTRL_0_conn_infra_on_host_bus__u_kh0__way_en_SHFT 0
/* =====================================================================================
---conn_infra_on_host_bus_u_kh1_CTRL_0 (0x1803B000 + 0x008)---
conn_infra_on_host_bus__u_kh1__way_en[15..0] - (RW) xxx
RESERVED16[31..16] - (RO) Reserved bits
=====================================================================================*/
#define CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_kh1_CTRL_0_conn_infra_on_host_bus__u_kh1__way_en_ADDR CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_kh1_CTRL_0_ADDR
#define CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_kh1_CTRL_0_conn_infra_on_host_bus__u_kh1__way_en_MASK 0x0000FFFF // conn_infra_on_host_bus__u_kh1__way_en[15..0]
#define CONN_ON_BUS_BCRM_conn_infra_on_host_bus_u_kh1_CTRL_0_conn_infra_on_host_bus__u_kh1__way_en_SHFT 0
/* =====================================================================================
---conn_infra_on_conn_bus_u_lnk_off2on_apb_to_conn_infra_on_conn_bus_kc0_APB_GALS_RX_CTRL_0 (0x1803B000 + 0x00c)---
conn_infra_on_conn_bus__u_lnk_off2on_apb_to_conn_infra_on_conn_bus_kc0_APB_GALS_RX__rx_clock_cg_en[0] - (RW) xxx
RESERVED1[31..1] - (RO) Reserved bits
=====================================================================================*/
#define CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_lnk_off2on_apb_to_conn_infra_on_conn_bus_kc0_APB_GALS_RX_CTRL_0_conn_infra_on_conn_bus__u_lnk_off2on_apb_to_conn_infra_on_conn_bus_kc0_APB_GALS_RX__rx_clock_cg_en_ADDR CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_lnk_off2on_apb_to_conn_infra_on_conn_bus_kc0_APB_GALS_RX_CTRL_0_ADDR
#define CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_lnk_off2on_apb_to_conn_infra_on_conn_bus_kc0_APB_GALS_RX_CTRL_0_conn_infra_on_conn_bus__u_lnk_off2on_apb_to_conn_infra_on_conn_bus_kc0_APB_GALS_RX__rx_clock_cg_en_MASK 0x00000001 // conn_infra_on_conn_bus__u_lnk_off2on_apb_to_conn_infra_on_conn_bus_kc0_APB_GALS_RX__rx_clock_cg_en[0]
#define CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_lnk_off2on_apb_to_conn_infra_on_conn_bus_kc0_APB_GALS_RX_CTRL_0_conn_infra_on_conn_bus__u_lnk_off2on_apb_to_conn_infra_on_conn_bus_kc0_APB_GALS_RX__rx_clock_cg_en_SHFT 0
/* =====================================================================================
---conn_infra_on_conn_bus_u_kc0_CTRL_0 (0x1803B000 + 0x010)---
conn_infra_on_conn_bus__u_kc0__way_en[0] - (RW) xxx
RESERVED1[31..1] - (RO) Reserved bits
=====================================================================================*/
#define CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_kc0_CTRL_0_conn_infra_on_conn_bus__u_kc0__way_en_ADDR CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_kc0_CTRL_0_ADDR
#define CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_kc0_CTRL_0_conn_infra_on_conn_bus__u_kc0__way_en_MASK 0x00000001 // conn_infra_on_conn_bus__u_kc0__way_en[0]
#define CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_kc0_CTRL_0_conn_infra_on_conn_bus__u_kc0__way_en_SHFT 0
/* =====================================================================================
---conn_infra_on_conn_bus_u_kc1_CTRL_0 (0x1803B000 + 0x014)---
conn_infra_on_conn_bus__u_kc1__way_en[15..0] - (RW) xxx
RESERVED16[31..16] - (RO) Reserved bits
=====================================================================================*/
#define CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_kc1_CTRL_0_conn_infra_on_conn_bus__u_kc1__way_en_ADDR CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_kc1_CTRL_0_ADDR
#define CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_kc1_CTRL_0_conn_infra_on_conn_bus__u_kc1__way_en_MASK 0x0000FFFF // conn_infra_on_conn_bus__u_kc1__way_en[15..0]
#define CONN_ON_BUS_BCRM_conn_infra_on_conn_bus_u_kc1_CTRL_0_conn_infra_on_conn_bus__u_kc1__way_en_SHFT 0
#endif // __CONN_ON_BUS_BCRM_REGS_H__

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
//[File] : conn_therm_ctl.h
//[Revision time] : Fri Jun 18 16:52:49 2021
//[Description] : This file is auto generated by CODA
//[Copyright] : Copyright (C) 2021 Mediatek Incorportion. All rights reserved.
#ifndef __CONN_THERM_CTL_REGS_H__
#define __CONN_THERM_CTL_REGS_H__
//****************************************************************************
//
// CONN_THERM_CTL CR Definitions
//
//****************************************************************************
#define CONN_THERM_CTL_BASE (CONN_REG_CONN_THERM_CTL_ADDR) // 0x18040000
#define CONN_THERM_CTL_THERMCR0_ADDR (CONN_THERM_CTL_BASE + 0x000) // 0000
#define CONN_THERM_CTL_THERMCR1_ADDR (CONN_THERM_CTL_BASE + 0x004) // 0004
#define CONN_THERM_CTL_THERMCR2_ADDR (CONN_THERM_CTL_BASE + 0x008) // 0008
#define CONN_THERM_CTL_THERMISR_ADDR (CONN_THERM_CTL_BASE + 0x00C) // 000C
#define CONN_THERM_CTL_THERM_ACL_ADDR (CONN_THERM_CTL_BASE + 0x010) // 0010
#define CONN_THERM_CTL_THERM_ATHERM_ADDR (CONN_THERM_CTL_BASE + 0x014) // 0014
#define CONN_THERM_CTL_THERM_AADDR_ADDR (CONN_THERM_CTL_BASE + 0x018) // 0018
#define CONN_THERM_CTL_THERMEN1_ADDR (CONN_THERM_CTL_BASE + 0x01C) // 001C
#define CONN_THERM_CTL_THERMEN2_ADDR (CONN_THERM_CTL_BASE + 0x020) // 0020
#define CONN_THERM_CTL_THERMEN3_ADDR (CONN_THERM_CTL_BASE + 0x024) // 0024
#define CONN_THERM_CTL_THERMEN4_ADDR (CONN_THERM_CTL_BASE + 0x028) // 0028
/* =====================================================================================
---THERMCR0 (0x18040000 + 0x000)---
THERM_RAW_VAL[6..0] - (RO) This value is the MSB 7-bit of the average of Thermal ADC output data with 6-bits each 8 samples. The average value = SUM(8 samples) / 4. It is valid only when THERM_CAL_EN is asserted and THERM_BUSY is not asserted.
RESERVED7[7] - (RO) Reserved bits
THERM_CAL_VAL[14..8] - (RW) The written data is used as the prior value y(n-1). The read value is the y(n) of AR Model.
RESERVED15[15] - (RO) Reserved bits
THERM_BUSY[16] - (RO) 1: MT6628 is waiting for Thermal stable or sampling Thermal value or calculating now.
0: MT6628 is idle now.
RESERVED17[17] - (RO) Reserved bits
THERM_TRIGGER[18] - (RW) Trigger MT6628 to do thermal calculation right now
When THERM_CAL_EN is asserted and write 1 will trigger Thermal sample procedure, and write 0 has no meaning. Read always return 0.
THERM_CAL_EN[19] - (RW) This field is used to enable the Automatic Detection. The Thermal periodic of Automatic Detection is set by UPDATE_TIME in THERMCR3 If software driver attempt to program or change the value of THERMCR0, this bit should be set to 0.
RESERVED20[23..20] - (RO) Reserved bits
THERM_MEASURE_CNT[28..24] - (RW) Guard time to prevent busy signal de-assert as mcu sleep and busy assert simultaneously. count by therm_x1_fr_ck
RESERVED29[31..29] - (RO) Reserved bits
=====================================================================================*/
#define CONN_THERM_CTL_THERMCR0_THERM_MEASURE_CNT_ADDR CONN_THERM_CTL_THERMCR0_ADDR
#define CONN_THERM_CTL_THERMCR0_THERM_MEASURE_CNT_MASK 0x1F000000 // THERM_MEASURE_CNT[28..24]
#define CONN_THERM_CTL_THERMCR0_THERM_MEASURE_CNT_SHFT 24
#define CONN_THERM_CTL_THERMCR0_THERM_CAL_EN_ADDR CONN_THERM_CTL_THERMCR0_ADDR
#define CONN_THERM_CTL_THERMCR0_THERM_CAL_EN_MASK 0x00080000 // THERM_CAL_EN[19]
#define CONN_THERM_CTL_THERMCR0_THERM_CAL_EN_SHFT 19
#define CONN_THERM_CTL_THERMCR0_THERM_TRIGGER_ADDR CONN_THERM_CTL_THERMCR0_ADDR
#define CONN_THERM_CTL_THERMCR0_THERM_TRIGGER_MASK 0x00040000 // THERM_TRIGGER[18]
#define CONN_THERM_CTL_THERMCR0_THERM_TRIGGER_SHFT 18
#define CONN_THERM_CTL_THERMCR0_THERM_BUSY_ADDR CONN_THERM_CTL_THERMCR0_ADDR
#define CONN_THERM_CTL_THERMCR0_THERM_BUSY_MASK 0x00010000 // THERM_BUSY[16]
#define CONN_THERM_CTL_THERMCR0_THERM_BUSY_SHFT 16
#define CONN_THERM_CTL_THERMCR0_THERM_CAL_VAL_ADDR CONN_THERM_CTL_THERMCR0_ADDR
#define CONN_THERM_CTL_THERMCR0_THERM_CAL_VAL_MASK 0x00007F00 // THERM_CAL_VAL[14..8]
#define CONN_THERM_CTL_THERMCR0_THERM_CAL_VAL_SHFT 8
#define CONN_THERM_CTL_THERMCR0_THERM_RAW_VAL_ADDR CONN_THERM_CTL_THERMCR0_ADDR
#define CONN_THERM_CTL_THERMCR0_THERM_RAW_VAL_MASK 0x0000007F // THERM_RAW_VAL[6..0]
#define CONN_THERM_CTL_THERMCR0_THERM_RAW_VAL_SHFT 0
/* =====================================================================================
---THERMCR1 (0x18040000 + 0x004)---
THERM_MAX[6..0] - (RW) This value is set to be the upper bound y(n) of AR model. If y(n) of transmit power is larger than(>=) THERM_MAX, interrupt will issued
THERM_EXCEED_EN[7] - (RW) To enable thermal exceed function
As enable, rf_paon will be gated when THERMCR0.THERM_CAL_VAL >= THERMCR1.THERM_MAX
THERM_MIN[14..8] - (RW) This value is set to be the lower bound y(n) of AR model. If y(n) of transmit power is smaller than (<=)THERM_MIN, interrupt will issued
RESERVED15[15] - (RO) Reserved bits
THERM_AR_FACTOR[17..16] - (RW) This field is used to set the parameter for the MT6628 Thermal measure. The formula is y(n)=(1-a)*y(n-1) + a*x(n).
is the MSB 7-bit value of ALC
2'b11: a=1
2'b10: a=1/4
2'b01: a=1/16
2'b00: a=1/32
RESERVED18[23..18] - (RO) Reserved bits
THERM_2ND_MAX[30..24] - (RW) This value is set to be the upper bound y(n) of AR model. If y(n) of transmit power is larger than (>=)THERM_2ND MAX, interrupt will issued
RESERVED31[31] - (RO) Reserved bits
=====================================================================================*/
#define CONN_THERM_CTL_THERMCR1_THERM_2ND_MAX_ADDR CONN_THERM_CTL_THERMCR1_ADDR
#define CONN_THERM_CTL_THERMCR1_THERM_2ND_MAX_MASK 0x7F000000 // THERM_2ND_MAX[30..24]
#define CONN_THERM_CTL_THERMCR1_THERM_2ND_MAX_SHFT 24
#define CONN_THERM_CTL_THERMCR1_THERM_AR_FACTOR_ADDR CONN_THERM_CTL_THERMCR1_ADDR
#define CONN_THERM_CTL_THERMCR1_THERM_AR_FACTOR_MASK 0x00030000 // THERM_AR_FACTOR[17..16]
#define CONN_THERM_CTL_THERMCR1_THERM_AR_FACTOR_SHFT 16
#define CONN_THERM_CTL_THERMCR1_THERM_MIN_ADDR CONN_THERM_CTL_THERMCR1_ADDR
#define CONN_THERM_CTL_THERMCR1_THERM_MIN_MASK 0x00007F00 // THERM_MIN[14..8]
#define CONN_THERM_CTL_THERMCR1_THERM_MIN_SHFT 8
#define CONN_THERM_CTL_THERMCR1_THERM_EXCEED_EN_ADDR CONN_THERM_CTL_THERMCR1_ADDR
#define CONN_THERM_CTL_THERMCR1_THERM_EXCEED_EN_MASK 0x00000080 // THERM_EXCEED_EN[7]
#define CONN_THERM_CTL_THERMCR1_THERM_EXCEED_EN_SHFT 7
#define CONN_THERM_CTL_THERMCR1_THERM_MAX_ADDR CONN_THERM_CTL_THERMCR1_ADDR
#define CONN_THERM_CTL_THERMCR1_THERM_MAX_MASK 0x0000007F // THERM_MAX[6..0]
#define CONN_THERM_CTL_THERMCR1_THERM_MAX_SHFT 0
/* =====================================================================================
---THERMCR2 (0x18040000 + 0x008)---
UPDATE_TIME[5..0] - (RW) This value specify how long we update the value of thermal sensor y(n)
RESERVED6[7..6] - (RO) Reserved bits
RG_THAD_RSV[15..8] - (RW) reserve bit
THERMAL_MIN_INT_EN[16] - (RW) enable interruption for Thermal_min_int
RESERVED17[19..17] - (RO) Reserved bits
THERMAL_SCND_MAX_INT_EN[20] - (RW) enable interruption for Thermal_scnd_max_int
RESERVED21[23..21] - (RO) Reserved bits
THERMAL_MAX_INT_EN[24] - (RW) enable interruption for Thermal_max_int
RESERVED25[31..25] - (RO) Reserved bits
=====================================================================================*/
#define CONN_THERM_CTL_THERMCR2_THERMAL_MAX_INT_EN_ADDR CONN_THERM_CTL_THERMCR2_ADDR
#define CONN_THERM_CTL_THERMCR2_THERMAL_MAX_INT_EN_MASK 0x01000000 // THERMAL_MAX_INT_EN[24]
#define CONN_THERM_CTL_THERMCR2_THERMAL_MAX_INT_EN_SHFT 24
#define CONN_THERM_CTL_THERMCR2_THERMAL_SCND_MAX_INT_EN_ADDR CONN_THERM_CTL_THERMCR2_ADDR
#define CONN_THERM_CTL_THERMCR2_THERMAL_SCND_MAX_INT_EN_MASK 0x00100000 // THERMAL_SCND_MAX_INT_EN[20]
#define CONN_THERM_CTL_THERMCR2_THERMAL_SCND_MAX_INT_EN_SHFT 20
#define CONN_THERM_CTL_THERMCR2_THERMAL_MIN_INT_EN_ADDR CONN_THERM_CTL_THERMCR2_ADDR
#define CONN_THERM_CTL_THERMCR2_THERMAL_MIN_INT_EN_MASK 0x00010000 // THERMAL_MIN_INT_EN[16]
#define CONN_THERM_CTL_THERMCR2_THERMAL_MIN_INT_EN_SHFT 16
#define CONN_THERM_CTL_THERMCR2_RG_THAD_RSV_ADDR CONN_THERM_CTL_THERMCR2_ADDR
#define CONN_THERM_CTL_THERMCR2_RG_THAD_RSV_MASK 0x0000FF00 // RG_THAD_RSV[15..8]
#define CONN_THERM_CTL_THERMCR2_RG_THAD_RSV_SHFT 8
#define CONN_THERM_CTL_THERMCR2_UPDATE_TIME_ADDR CONN_THERM_CTL_THERMCR2_ADDR
#define CONN_THERM_CTL_THERMCR2_UPDATE_TIME_MASK 0x0000003F // UPDATE_TIME[5..0]
#define CONN_THERM_CTL_THERMCR2_UPDATE_TIME_SHFT 0
/* =====================================================================================
---THERMISR (0x18040000 + 0x00C)---
RESERVED0[15..0] - (RO) Reserved bits
THERMAL_MIN_INT[16] - (W1C) If value of thermal sensor y(n) is smaller THERM_MIN
RESERVED17[19..17] - (RO) Reserved bits
THERMAL_SCND_MAX_INT[20] - (W1C) If value of thermal sensor y(n) is larger THERM_2ND_MAX
RESERVED21[23..21] - (RO) Reserved bits
THERMAL_MAX_INT[24] - (W1C) If value of thermal sensor y(n) is larger THERM_MAX
RESERVED25[31..25] - (RO) Reserved bits
=====================================================================================*/
#define CONN_THERM_CTL_THERMISR_THERMAL_MAX_INT_ADDR CONN_THERM_CTL_THERMISR_ADDR
#define CONN_THERM_CTL_THERMISR_THERMAL_MAX_INT_MASK 0x01000000 // THERMAL_MAX_INT[24]
#define CONN_THERM_CTL_THERMISR_THERMAL_MAX_INT_SHFT 24
#define CONN_THERM_CTL_THERMISR_THERMAL_SCND_MAX_INT_ADDR CONN_THERM_CTL_THERMISR_ADDR
#define CONN_THERM_CTL_THERMISR_THERMAL_SCND_MAX_INT_MASK 0x00100000 // THERMAL_SCND_MAX_INT[20]
#define CONN_THERM_CTL_THERMISR_THERMAL_SCND_MAX_INT_SHFT 20
#define CONN_THERM_CTL_THERMISR_THERMAL_MIN_INT_ADDR CONN_THERM_CTL_THERMISR_ADDR
#define CONN_THERM_CTL_THERMISR_THERMAL_MIN_INT_MASK 0x00010000 // THERMAL_MIN_INT[16]
#define CONN_THERM_CTL_THERMISR_THERMAL_MIN_INT_SHFT 16
/* =====================================================================================
---THERM_ACL (0x18040000 + 0x010)---
ADIE_TOPCLK_EN[31..0] - (RW) A-die top clock enable setting.
=====================================================================================*/
#define CONN_THERM_CTL_THERM_ACL_ADIE_TOPCLK_EN_ADDR CONN_THERM_CTL_THERM_ACL_ADDR
#define CONN_THERM_CTL_THERM_ACL_ADIE_TOPCLK_EN_MASK 0xFFFFFFFF // ADIE_TOPCLK_EN[31..0]
#define CONN_THERM_CTL_THERM_ACL_ADIE_TOPCLK_EN_SHFT 0
/* =====================================================================================
---THERM_ATHERM (0x18040000 + 0x014)---
ADIE_THERM_CTL[31..0] - (RW) A-die thermal control setting
=====================================================================================*/
#define CONN_THERM_CTL_THERM_ATHERM_ADIE_THERM_CTL_ADDR CONN_THERM_CTL_THERM_ATHERM_ADDR
#define CONN_THERM_CTL_THERM_ATHERM_ADIE_THERM_CTL_MASK 0xFFFFFFFF // ADIE_THERM_CTL[31..0]
#define CONN_THERM_CTL_THERM_ATHERM_ADIE_THERM_CTL_SHFT 0
/* =====================================================================================
---THERM_AADDR (0x18040000 + 0x018)---
ADIE_CLK_ADDR[11..0] - (RW) Adie clk_en address: a00
ADIE_CLK_GRP[14..12] - (RW) Adie clk_en spi group: 5
RESERVED15[15] - (RO) Reserved bits
ADIE_THERM_ADDR[27..16] - (RW) Adie therm_ctl address: 030
ADIE_THERM_GRP[30..28] - (RW) Adie therm_ctl spi group: 5
RESERVED31[31] - (RO) Reserved bits
=====================================================================================*/
#define CONN_THERM_CTL_THERM_AADDR_ADIE_THERM_GRP_ADDR CONN_THERM_CTL_THERM_AADDR_ADDR
#define CONN_THERM_CTL_THERM_AADDR_ADIE_THERM_GRP_MASK 0x70000000 // ADIE_THERM_GRP[30..28]
#define CONN_THERM_CTL_THERM_AADDR_ADIE_THERM_GRP_SHFT 28
#define CONN_THERM_CTL_THERM_AADDR_ADIE_THERM_ADDR_ADDR CONN_THERM_CTL_THERM_AADDR_ADDR
#define CONN_THERM_CTL_THERM_AADDR_ADIE_THERM_ADDR_MASK 0x0FFF0000 // ADIE_THERM_ADDR[27..16]
#define CONN_THERM_CTL_THERM_AADDR_ADIE_THERM_ADDR_SHFT 16
#define CONN_THERM_CTL_THERM_AADDR_ADIE_CLK_GRP_ADDR CONN_THERM_CTL_THERM_AADDR_ADDR
#define CONN_THERM_CTL_THERM_AADDR_ADIE_CLK_GRP_MASK 0x00007000 // ADIE_CLK_GRP[14..12]
#define CONN_THERM_CTL_THERM_AADDR_ADIE_CLK_GRP_SHFT 12
#define CONN_THERM_CTL_THERM_AADDR_ADIE_CLK_ADDR_ADDR CONN_THERM_CTL_THERM_AADDR_ADDR
#define CONN_THERM_CTL_THERM_AADDR_ADIE_CLK_ADDR_MASK 0x00000FFF // ADIE_CLK_ADDR[11..0]
#define CONN_THERM_CTL_THERM_AADDR_ADIE_CLK_ADDR_SHFT 0
/* =====================================================================================
---THERMEN1 (0x18040000 + 0x01C)---
THERM_RAW_VAL_1[6..0] - (RO) raw value for subsys 1
RESERVED7[7] - (RO) Reserved bits
THERM_CAL_VAL_1[14..8] - (RO) cal value for subsys 1, RO
RESERVED15[15] - (RO) Reserved bits
THERM_BUSY_1[16] - (RO) bust bit for subsys 1
RESERVED17[17] - (RO) Reserved bits
THERM_TRIGGER_1[18] - (RW) trigger for subsys 1
THERM_CAL_EN_1[19] - (RW) enable for subsys_1
RESERVED20[31..20] - (RO) Reserved bits
=====================================================================================*/
#define CONN_THERM_CTL_THERMEN1_THERM_CAL_EN_1_ADDR CONN_THERM_CTL_THERMEN1_ADDR
#define CONN_THERM_CTL_THERMEN1_THERM_CAL_EN_1_MASK 0x00080000 // THERM_CAL_EN_1[19]
#define CONN_THERM_CTL_THERMEN1_THERM_CAL_EN_1_SHFT 19
#define CONN_THERM_CTL_THERMEN1_THERM_TRIGGER_1_ADDR CONN_THERM_CTL_THERMEN1_ADDR
#define CONN_THERM_CTL_THERMEN1_THERM_TRIGGER_1_MASK 0x00040000 // THERM_TRIGGER_1[18]
#define CONN_THERM_CTL_THERMEN1_THERM_TRIGGER_1_SHFT 18
#define CONN_THERM_CTL_THERMEN1_THERM_BUSY_1_ADDR CONN_THERM_CTL_THERMEN1_ADDR
#define CONN_THERM_CTL_THERMEN1_THERM_BUSY_1_MASK 0x00010000 // THERM_BUSY_1[16]
#define CONN_THERM_CTL_THERMEN1_THERM_BUSY_1_SHFT 16
#define CONN_THERM_CTL_THERMEN1_THERM_CAL_VAL_1_ADDR CONN_THERM_CTL_THERMEN1_ADDR
#define CONN_THERM_CTL_THERMEN1_THERM_CAL_VAL_1_MASK 0x00007F00 // THERM_CAL_VAL_1[14..8]
#define CONN_THERM_CTL_THERMEN1_THERM_CAL_VAL_1_SHFT 8
#define CONN_THERM_CTL_THERMEN1_THERM_RAW_VAL_1_ADDR CONN_THERM_CTL_THERMEN1_ADDR
#define CONN_THERM_CTL_THERMEN1_THERM_RAW_VAL_1_MASK 0x0000007F // THERM_RAW_VAL_1[6..0]
#define CONN_THERM_CTL_THERMEN1_THERM_RAW_VAL_1_SHFT 0
/* =====================================================================================
---THERMEN2 (0x18040000 + 0x020)---
THERM_RAW_VAL_2[6..0] - (RO) raw value for subsys 2
RESERVED7[7] - (RO) Reserved bits
THERM_CAL_VAL_2[14..8] - (RO) cal value for subsys 2, RO
RESERVED15[15] - (RO) Reserved bits
THERM_BUSY_2[16] - (RO) bust bit for subsys 2
RESERVED17[17] - (RO) Reserved bits
THERM_TRIGGER_2[18] - (RW) trigger for subsys 2
THERM_CAL_EN_2[19] - (RW) enable for subsys_2
RESERVED20[31..20] - (RO) Reserved bits
=====================================================================================*/
#define CONN_THERM_CTL_THERMEN2_THERM_CAL_EN_2_ADDR CONN_THERM_CTL_THERMEN2_ADDR
#define CONN_THERM_CTL_THERMEN2_THERM_CAL_EN_2_MASK 0x00080000 // THERM_CAL_EN_2[19]
#define CONN_THERM_CTL_THERMEN2_THERM_CAL_EN_2_SHFT 19
#define CONN_THERM_CTL_THERMEN2_THERM_TRIGGER_2_ADDR CONN_THERM_CTL_THERMEN2_ADDR
#define CONN_THERM_CTL_THERMEN2_THERM_TRIGGER_2_MASK 0x00040000 // THERM_TRIGGER_2[18]
#define CONN_THERM_CTL_THERMEN2_THERM_TRIGGER_2_SHFT 18
#define CONN_THERM_CTL_THERMEN2_THERM_BUSY_2_ADDR CONN_THERM_CTL_THERMEN2_ADDR
#define CONN_THERM_CTL_THERMEN2_THERM_BUSY_2_MASK 0x00010000 // THERM_BUSY_2[16]
#define CONN_THERM_CTL_THERMEN2_THERM_BUSY_2_SHFT 16
#define CONN_THERM_CTL_THERMEN2_THERM_CAL_VAL_2_ADDR CONN_THERM_CTL_THERMEN2_ADDR
#define CONN_THERM_CTL_THERMEN2_THERM_CAL_VAL_2_MASK 0x00007F00 // THERM_CAL_VAL_2[14..8]
#define CONN_THERM_CTL_THERMEN2_THERM_CAL_VAL_2_SHFT 8
#define CONN_THERM_CTL_THERMEN2_THERM_RAW_VAL_2_ADDR CONN_THERM_CTL_THERMEN2_ADDR
#define CONN_THERM_CTL_THERMEN2_THERM_RAW_VAL_2_MASK 0x0000007F // THERM_RAW_VAL_2[6..0]
#define CONN_THERM_CTL_THERMEN2_THERM_RAW_VAL_2_SHFT 0
/* =====================================================================================
---THERMEN3 (0x18040000 + 0x024)---
THERM_RAW_VAL_3[6..0] - (RO) raw value for subsys 3
RESERVED7[7] - (RO) Reserved bits
THERM_CAL_VAL_3[14..8] - (RO) cal value for subsys 3, RO
RESERVED15[15] - (RO) Reserved bits
THERM_BUSY_3[16] - (RO) bust bit for subsys 3
RESERVED17[17] - (RO) Reserved bits
THERM_TRIGGER_3[18] - (RW) trigger for subsys 3
THERM_CAL_EN_3[19] - (RW) enable for subsys_3
RESERVED20[31..20] - (RO) Reserved bits
=====================================================================================*/
#define CONN_THERM_CTL_THERMEN3_THERM_CAL_EN_3_ADDR CONN_THERM_CTL_THERMEN3_ADDR
#define CONN_THERM_CTL_THERMEN3_THERM_CAL_EN_3_MASK 0x00080000 // THERM_CAL_EN_3[19]
#define CONN_THERM_CTL_THERMEN3_THERM_CAL_EN_3_SHFT 19
#define CONN_THERM_CTL_THERMEN3_THERM_TRIGGER_3_ADDR CONN_THERM_CTL_THERMEN3_ADDR
#define CONN_THERM_CTL_THERMEN3_THERM_TRIGGER_3_MASK 0x00040000 // THERM_TRIGGER_3[18]
#define CONN_THERM_CTL_THERMEN3_THERM_TRIGGER_3_SHFT 18
#define CONN_THERM_CTL_THERMEN3_THERM_BUSY_3_ADDR CONN_THERM_CTL_THERMEN3_ADDR
#define CONN_THERM_CTL_THERMEN3_THERM_BUSY_3_MASK 0x00010000 // THERM_BUSY_3[16]
#define CONN_THERM_CTL_THERMEN3_THERM_BUSY_3_SHFT 16
#define CONN_THERM_CTL_THERMEN3_THERM_CAL_VAL_3_ADDR CONN_THERM_CTL_THERMEN3_ADDR
#define CONN_THERM_CTL_THERMEN3_THERM_CAL_VAL_3_MASK 0x00007F00 // THERM_CAL_VAL_3[14..8]
#define CONN_THERM_CTL_THERMEN3_THERM_CAL_VAL_3_SHFT 8
#define CONN_THERM_CTL_THERMEN3_THERM_RAW_VAL_3_ADDR CONN_THERM_CTL_THERMEN3_ADDR
#define CONN_THERM_CTL_THERMEN3_THERM_RAW_VAL_3_MASK 0x0000007F // THERM_RAW_VAL_3[6..0]
#define CONN_THERM_CTL_THERMEN3_THERM_RAW_VAL_3_SHFT 0
/* =====================================================================================
---THERMEN4 (0x18040000 + 0x028)---
THERM_RAW_VAL_4[6..0] - (RO) raw value for subsys 4
RESERVED7[7] - (RO) Reserved bits
THERM_CAL_VAL_4[14..8] - (RO) cal value for subsys 4, RO
RESERVED15[15] - (RO) Reserved bits
THERM_BUSY_4[16] - (RO) bust bit for subsys 4
RESERVED17[17] - (RO) Reserved bits
THERM_TRIGGER_4[18] - (RW) trigger for subsys 4
THERM_CAL_EN_4[19] - (RW) enable for subsys_4
RESERVED20[31..20] - (RO) Reserved bits
=====================================================================================*/
#define CONN_THERM_CTL_THERMEN4_THERM_CAL_EN_4_ADDR CONN_THERM_CTL_THERMEN4_ADDR
#define CONN_THERM_CTL_THERMEN4_THERM_CAL_EN_4_MASK 0x00080000 // THERM_CAL_EN_4[19]
#define CONN_THERM_CTL_THERMEN4_THERM_CAL_EN_4_SHFT 19
#define CONN_THERM_CTL_THERMEN4_THERM_TRIGGER_4_ADDR CONN_THERM_CTL_THERMEN4_ADDR
#define CONN_THERM_CTL_THERMEN4_THERM_TRIGGER_4_MASK 0x00040000 // THERM_TRIGGER_4[18]
#define CONN_THERM_CTL_THERMEN4_THERM_TRIGGER_4_SHFT 18
#define CONN_THERM_CTL_THERMEN4_THERM_BUSY_4_ADDR CONN_THERM_CTL_THERMEN4_ADDR
#define CONN_THERM_CTL_THERMEN4_THERM_BUSY_4_MASK 0x00010000 // THERM_BUSY_4[16]
#define CONN_THERM_CTL_THERMEN4_THERM_BUSY_4_SHFT 16
#define CONN_THERM_CTL_THERMEN4_THERM_CAL_VAL_4_ADDR CONN_THERM_CTL_THERMEN4_ADDR
#define CONN_THERM_CTL_THERMEN4_THERM_CAL_VAL_4_MASK 0x00007F00 // THERM_CAL_VAL_4[14..8]
#define CONN_THERM_CTL_THERMEN4_THERM_CAL_VAL_4_SHFT 8
#define CONN_THERM_CTL_THERMEN4_THERM_RAW_VAL_4_ADDR CONN_THERM_CTL_THERMEN4_ADDR
#define CONN_THERM_CTL_THERMEN4_THERM_RAW_VAL_4_MASK 0x0000007F // THERM_RAW_VAL_4[6..0]
#define CONN_THERM_CTL_THERMEN4_THERM_RAW_VAL_4_SHFT 0
#endif // __CONN_THERM_CTL_REGS_H__

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drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/CODA/conn_von_bus_bcrm.h Normal file
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@ -0,0 +1,323 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
//[File] : conn_von_bus_bcrm.h
//[Revision time] : Fri Jun 18 16:52:53 2021
//[Description] : This file is auto generated by CODA
//[Copyright] : Copyright (C) 2021 Mediatek Incorportion. All rights reserved.
#ifndef __CONN_VON_BUS_BCRM_REGS_H__
#define __CONN_VON_BUS_BCRM_REGS_H__
//****************************************************************************
//
// CONN_VON_BUS_BCRM CR Definitions
//
//****************************************************************************
#define CONN_VON_BUS_BCRM_BASE (CONN_REG_CONN_VON_BUS_BCRM_ADDR) // 0x18020000
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0_ADDR (CONN_VON_BUS_BCRM_BASE + 0x000) // 0000
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_0_ADDR (CONN_VON_BUS_BCRM_BASE + 0x004) // 0004
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_1_ADDR (CONN_VON_BUS_BCRM_BASE + 0x008) // 0008
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_2_ADDR (CONN_VON_BUS_BCRM_BASE + 0x00c) // 000C
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_APB_GALS_TX_CTRL_0_ADDR (CONN_VON_BUS_BCRM_BASE + 0x010) // 0010
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h0_CTRL_0_ADDR (CONN_VON_BUS_BCRM_BASE + 0x014) // 0014
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_0_ADDR (CONN_VON_BUS_BCRM_BASE + 0x018) // 0018
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_1_ADDR (CONN_VON_BUS_BCRM_BASE + 0x01c) // 001C
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_2_ADDR (CONN_VON_BUS_BCRM_BASE + 0x020) // 0020
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_3_ADDR (CONN_VON_BUS_BCRM_BASE + 0x024) // 0024
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_ADDR (CONN_VON_BUS_BCRM_BASE + 0x028) // 0028
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_ADDR (CONN_VON_BUS_BCRM_BASE + 0x02c) // 002C
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_0_ADDR (CONN_VON_BUS_BCRM_BASE + 0x030) // 0030
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_1_ADDR (CONN_VON_BUS_BCRM_BASE + 0x034) // 0034
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_2_ADDR (CONN_VON_BUS_BCRM_BASE + 0x038) // 0038
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_3_ADDR (CONN_VON_BUS_BCRM_BASE + 0x03c) // 003C
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_4_ADDR (CONN_VON_BUS_BCRM_BASE + 0x040) // 0040
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_5_ADDR (CONN_VON_BUS_BCRM_BASE + 0x044) // 0044
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_6_ADDR (CONN_VON_BUS_BCRM_BASE + 0x048) // 0048
/* =====================================================================================
---conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0 (0x18020000 + 0x000)---
conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__error_flag_en[0] - (RW) xxx
conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__rg_cmd_cnt_clr[1] - (RW) xxx
conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__rg_monitor_mode[2] - (RW) xxx
RESERVED3[31..3] - (RO) Reserved bits
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__rg_monitor_mode_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__rg_monitor_mode_MASK 0x00000004 // conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__rg_monitor_mode[2]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__rg_monitor_mode_SHFT 2
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__rg_cmd_cnt_clr_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__rg_cmd_cnt_clr_MASK 0x00000002 // conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__rg_cmd_cnt_clr[1]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__rg_cmd_cnt_clr_SHFT 1
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__error_flag_en_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__error_flag_en_MASK 0x00000001 // conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__error_flag_en[0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h1_to_von2off_AHB_S_PWR_PROT__error_flag_en_SHFT 0
/* =====================================================================================
---conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_0 (0x18020000 + 0x004)---
conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__way_en_ready[0] - (RO) xxx
conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__force_pready_high[1] - (RW) xxx
RESERVED2[31..2] - (RO) Reserved bits
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__force_pready_high_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__force_pready_high_MASK 0x00000002 // conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__force_pready_high[1]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__force_pready_high_SHFT 1
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__way_en_ready_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__way_en_ready_MASK 0x00000001 // conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__way_en_ready[0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__way_en_ready_SHFT 0
/* =====================================================================================
---conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_1 (0x18020000 + 0x008)---
conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__device_APC_con[31..0] - (RW) xxx
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_1_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__device_APC_con_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_1_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_1_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__device_APC_con_MASK 0xFFFFFFFF // conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__device_APC_con[31..0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_1_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__device_APC_con_SHFT 0
/* =====================================================================================
---conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_2 (0x18020000 + 0x00c)---
conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__way_en[0] - (RW) xxx
RESERVED1[31..1] - (RO) Reserved bits
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_2_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__way_en_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_2_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_2_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__way_en_MASK 0x00000001 // conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__way_en[0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB_CTRL_2_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_SBUS2APB__way_en_SHFT 0
/* =====================================================================================
---conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_APB_GALS_TX_CTRL_0 (0x18020000 + 0x010)---
conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_APB_GALS_TX__error_flag_en[0] - (RW) Enables error flag, controls the time-out counter
RESERVED1[31..1] - (RO) Reserved bits
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_APB_GALS_TX_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_APB_GALS_TX__error_flag_en_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_APB_GALS_TX_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_APB_GALS_TX_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_APB_GALS_TX__error_flag_en_MASK 0x00000001 // conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_APB_GALS_TX__error_flag_en[0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_lnk_conn_von_bus_h3_to_von2on_apb_APB_GALS_TX_CTRL_0_conn_von_bus__u_lnk_conn_von_bus_h3_to_von2on_apb_APB_GALS_TX__error_flag_en_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h0_CTRL_0 (0x18020000 + 0x014)---
conn_von_bus__u_h0__postwrite_dis[0] - (RW) xxx
conn_von_bus__u_h0__ahb_flush_thre[2..1] - (RW) xxx
conn_von_bus__u_h0__err_flag_en[3] - (RW) xxx
RESERVED4[31..4] - (RO) Reserved bits
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h0_CTRL_0_conn_von_bus__u_h0__err_flag_en_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h0_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h0_CTRL_0_conn_von_bus__u_h0__err_flag_en_MASK 0x00000008 // conn_von_bus__u_h0__err_flag_en[3]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h0_CTRL_0_conn_von_bus__u_h0__err_flag_en_SHFT 3
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h0_CTRL_0_conn_von_bus__u_h0__ahb_flush_thre_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h0_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h0_CTRL_0_conn_von_bus__u_h0__ahb_flush_thre_MASK 0x00000006 // conn_von_bus__u_h0__ahb_flush_thre[2..1]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h0_CTRL_0_conn_von_bus__u_h0__ahb_flush_thre_SHFT 1
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h0_CTRL_0_conn_von_bus__u_h0__postwrite_dis_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h0_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h0_CTRL_0_conn_von_bus__u_h0__postwrite_dis_MASK 0x00000001 // conn_von_bus__u_h0__postwrite_dis[0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h0_CTRL_0_conn_von_bus__u_h0__postwrite_dis_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h1_CTRL_0 (0x18020000 + 0x018)---
conn_von_bus__u_h1__ctrl_update_status[0] - (RO) xxx
conn_von_bus__u_h1__reg_slave_way_en[2..1] - (RW) xxx
RESERVED3[31..3] - (RO) Reserved bits
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_0_conn_von_bus__u_h1__reg_slave_way_en_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_0_conn_von_bus__u_h1__reg_slave_way_en_MASK 0x00000006 // conn_von_bus__u_h1__reg_slave_way_en[2..1]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_0_conn_von_bus__u_h1__reg_slave_way_en_SHFT 1
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_0_conn_von_bus__u_h1__ctrl_update_status_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_0_conn_von_bus__u_h1__ctrl_update_status_MASK 0x00000001 // conn_von_bus__u_h1__ctrl_update_status[0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_0_conn_von_bus__u_h1__ctrl_update_status_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h1_CTRL_1 (0x18020000 + 0x01c)---
conn_von_bus__u_h1__device_apc_con_bit31_bit0[31..0] - (RW) xxx
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_1_conn_von_bus__u_h1__device_apc_con_bit31_bit0_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_1_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_1_conn_von_bus__u_h1__device_apc_con_bit31_bit0_MASK 0xFFFFFFFF // conn_von_bus__u_h1__device_apc_con_bit31_bit0[31..0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_1_conn_von_bus__u_h1__device_apc_con_bit31_bit0_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h1_CTRL_2 (0x18020000 + 0x020)---
conn_von_bus__u_h1__device_apc_con_bit63_bit32[31..0] - (RW) xxx
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_2_conn_von_bus__u_h1__device_apc_con_bit63_bit32_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_2_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_2_conn_von_bus__u_h1__device_apc_con_bit63_bit32_MASK 0xFFFFFFFF // conn_von_bus__u_h1__device_apc_con_bit63_bit32[31..0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_2_conn_von_bus__u_h1__device_apc_con_bit63_bit32_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h1_CTRL_3 (0x18020000 + 0x024)---
conn_von_bus__u_h1__error_flag_en[0] - (RW) xxx
RESERVED1[31..1] - (RO) Reserved bits
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_3_conn_von_bus__u_h1__error_flag_en_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_3_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_3_conn_von_bus__u_h1__error_flag_en_MASK 0x00000001 // conn_von_bus__u_h1__error_flag_en[0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h1_CTRL_3_conn_von_bus__u_h1__error_flag_en_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h2_CTRL_0 (0x18020000 + 0x028)---
conn_von_bus__u_h2__ctrl_update_status[1..0] - (RO) xxx
conn_von_bus__u_h2__reg_layer_way_en[3..2] - (RW) xxx
conn_von_bus__u_h2__reg_slave_way_en[4] - (RW) xxx
conn_von_bus__u_h2__reg_qos_en[5] - (RW) xxx
conn_von_bus__u_h2__error_flag_en[6] - (RW) xxx
RESERVED7[31..7] - (RO) Reserved bits
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__error_flag_en_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__error_flag_en_MASK 0x00000040 // conn_von_bus__u_h2__error_flag_en[6]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__error_flag_en_SHFT 6
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__reg_qos_en_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__reg_qos_en_MASK 0x00000020 // conn_von_bus__u_h2__reg_qos_en[5]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__reg_qos_en_SHFT 5
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__reg_slave_way_en_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__reg_slave_way_en_MASK 0x00000010 // conn_von_bus__u_h2__reg_slave_way_en[4]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__reg_slave_way_en_SHFT 4
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__reg_layer_way_en_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__reg_layer_way_en_MASK 0x0000000C // conn_von_bus__u_h2__reg_layer_way_en[3..2]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__reg_layer_way_en_SHFT 2
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__ctrl_update_status_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__ctrl_update_status_MASK 0x00000003 // conn_von_bus__u_h2__ctrl_update_status[1..0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h2_CTRL_0_conn_von_bus__u_h2__ctrl_update_status_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h3_CTRL_0 (0x18020000 + 0x02c)---
conn_von_bus__u_h3__ctrl_update_status[0] - (RO) xxx
conn_von_bus__u_h3__reg_slave_way_en[2..1] - (RW) xxx
conn_von_bus__u_h3__reg_force_slast[3] - (RW) xxx
conn_von_bus__u_h3__error_flag_en[4] - (RW) xxx
RESERVED5[31..5] - (RO) Reserved bits
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_conn_von_bus__u_h3__error_flag_en_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_conn_von_bus__u_h3__error_flag_en_MASK 0x00000010 // conn_von_bus__u_h3__error_flag_en[4]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_conn_von_bus__u_h3__error_flag_en_SHFT 4
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_conn_von_bus__u_h3__reg_force_slast_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_conn_von_bus__u_h3__reg_force_slast_MASK 0x00000008 // conn_von_bus__u_h3__reg_force_slast[3]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_conn_von_bus__u_h3__reg_force_slast_SHFT 3
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_conn_von_bus__u_h3__reg_slave_way_en_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_conn_von_bus__u_h3__reg_slave_way_en_MASK 0x00000006 // conn_von_bus__u_h3__reg_slave_way_en[2..1]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_conn_von_bus__u_h3__reg_slave_way_en_SHFT 1
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_conn_von_bus__u_h3__ctrl_update_status_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_conn_von_bus__u_h3__ctrl_update_status_MASK 0x00000001 // conn_von_bus__u_h3__ctrl_update_status[0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h3_CTRL_0_conn_von_bus__u_h3__ctrl_update_status_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h4_CTRL_0 (0x18020000 + 0x030)---
conn_von_bus__u_h4__way_en_ready[4..0] - (RO) xxx
conn_von_bus__u_h4__force_pready_high[9..5] - (RW) xxx
RESERVED10[31..10] - (RO) Reserved bits
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_0_conn_von_bus__u_h4__force_pready_high_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_0_conn_von_bus__u_h4__force_pready_high_MASK 0x000003E0 // conn_von_bus__u_h4__force_pready_high[9..5]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_0_conn_von_bus__u_h4__force_pready_high_SHFT 5
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_0_conn_von_bus__u_h4__way_en_ready_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_0_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_0_conn_von_bus__u_h4__way_en_ready_MASK 0x0000001F // conn_von_bus__u_h4__way_en_ready[4..0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_0_conn_von_bus__u_h4__way_en_ready_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h4_CTRL_1 (0x18020000 + 0x034)---
conn_von_bus__u_h4__device_APC_con_bit31_bit0[31..0] - (RW) xxx
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_1_conn_von_bus__u_h4__device_APC_con_bit31_bit0_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_1_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_1_conn_von_bus__u_h4__device_APC_con_bit31_bit0_MASK 0xFFFFFFFF // conn_von_bus__u_h4__device_APC_con_bit31_bit0[31..0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_1_conn_von_bus__u_h4__device_APC_con_bit31_bit0_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h4_CTRL_2 (0x18020000 + 0x038)---
conn_von_bus__u_h4__device_APC_con_bit63_bit32[31..0] - (RW) xxx
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_2_conn_von_bus__u_h4__device_APC_con_bit63_bit32_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_2_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_2_conn_von_bus__u_h4__device_APC_con_bit63_bit32_MASK 0xFFFFFFFF // conn_von_bus__u_h4__device_APC_con_bit63_bit32[31..0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_2_conn_von_bus__u_h4__device_APC_con_bit63_bit32_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h4_CTRL_3 (0x18020000 + 0x03c)---
conn_von_bus__u_h4__device_APC_con_bit95_bit64[31..0] - (RW) xxx
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_3_conn_von_bus__u_h4__device_APC_con_bit95_bit64_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_3_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_3_conn_von_bus__u_h4__device_APC_con_bit95_bit64_MASK 0xFFFFFFFF // conn_von_bus__u_h4__device_APC_con_bit95_bit64[31..0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_3_conn_von_bus__u_h4__device_APC_con_bit95_bit64_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h4_CTRL_4 (0x18020000 + 0x040)---
conn_von_bus__u_h4__device_APC_con_bit127_bit96[31..0] - (RW) xxx
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_4_conn_von_bus__u_h4__device_APC_con_bit127_bit96_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_4_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_4_conn_von_bus__u_h4__device_APC_con_bit127_bit96_MASK 0xFFFFFFFF // conn_von_bus__u_h4__device_APC_con_bit127_bit96[31..0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_4_conn_von_bus__u_h4__device_APC_con_bit127_bit96_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h4_CTRL_5 (0x18020000 + 0x044)---
conn_von_bus__u_h4__device_APC_con_bit159_bit128[31..0] - (RW) xxx
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_5_conn_von_bus__u_h4__device_APC_con_bit159_bit128_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_5_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_5_conn_von_bus__u_h4__device_APC_con_bit159_bit128_MASK 0xFFFFFFFF // conn_von_bus__u_h4__device_APC_con_bit159_bit128[31..0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_5_conn_von_bus__u_h4__device_APC_con_bit159_bit128_SHFT 0
/* =====================================================================================
---conn_von_bus_u_h4_CTRL_6 (0x18020000 + 0x048)---
conn_von_bus__u_h4__way_en[4..0] - (RW) xxx
RESERVED5[31..5] - (RO) Reserved bits
=====================================================================================*/
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_6_conn_von_bus__u_h4__way_en_ADDR CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_6_ADDR
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_6_conn_von_bus__u_h4__way_en_MASK 0x0000001F // conn_von_bus__u_h4__way_en[4..0]
#define CONN_VON_BUS_BCRM_conn_von_bus_u_h4_CTRL_6_conn_von_bus__u_h4__way_en_SHFT 0
#endif // __CONN_VON_BUS_BCRM_REGS_H__

1604
drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/CODA/conn_wt_slp_ctl_reg.h Normal file
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52
drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/mt6879.h Normal file
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@ -0,0 +1,52 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#ifndef _PLATFORM_MT6879_H_
#define _PLATFORM_MT6879_H_
#define ADIE_6637 0x6637
#define ADIE_6635 0x6635
enum conn_semaphore_type
{
CONN_SEMA_CHIP_POWER_ON_INDEX = 0,
CONN_SEMA_CALIBRATION_INDEX = 1,
CONN_SEMA_FW_DL_INDEX = 2,
CONN_SEMA_CLOCK_SWITCH_INDEX = 3,
CONN_SEMA_PINMUX_INDEX = 4,
CONN_SEMA_CCIF_INDEX = 5,
CONN_SEMA_COEX_INDEX = 6,
CONN_SEMA_USB_EP0_INDEX = 7,
CONN_SEMA_USB_SHARED_INFO_INDEX = 8,
CONN_SEMA_USB_SUSPEND_INDEX = 9,
CONN_SEMA_USB_RESUME_INDEX = 10,
CONN_SEMA_PCIE_INDEX = 11,
CONN_SEMA_RFSPI_INDEX = 12,
CONN_SEMA_EFUSE_INDEX = 13,
CONN_SEMA_THERMAL_INDEX = 14,
CONN_SEMA_FLASH_INDEX = 15,
CONN_SEMA_DEBUG_INDEX = 16,
CONN_SEMA_WIFI_LP_INDEX = 17,
CONN_SEMA_PATCH_DL_INDEX = 18,
CONN_SEMA_SHARED_VAR_INDEX = 19,
CONN_SEMA_BGF_UART0_INDEX = 20,
CONN_SEMA_BGF_UART1_INDEX = 21,
CONN_SEMA_SDIO_CLK_INDEX = 22,
CONN_SEMA_CONN_INFRA_COMMON_SYSRAM_INDEX = 23,
CONN_SEMA_NUM_MAX = 25 /* can't be omitted */
};
struct consys_plat_thermal_data_mt6879 {
int thermal_b;
int slop_molecule;
int offset;
};
int consys_platform_spm_conn_ctrl_mt6879(unsigned int enable);
int consys_co_clock_type_mt6879(void);
void update_thermal_data_mt6879(struct consys_plat_thermal_data_mt6879* input);
unsigned int consys_get_adie_chipid_mt6879(void);
#endif /* _PLATFORM_MT6879_H_ */

39
drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/mt6879_connsyslog.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#ifndef _PLATFORM_MT6879_CONNSYSLOG_H_
#define _PLATFORM_MT6879_CONNSYSLOG_H_
#include "connsyslog_hw_config.h"
#include "connsys_debug_utility.h"
#ifdef CONFIG_FPGA_EARLY_PORTING
#define CONNLOG_EMI_OFFSET_WIFI 0x000c8000
#define CONNLOG_EMI_OFFSET_BT 0x0002F000
#else
#define CONNLOG_EMI_OFFSET_WIFI 0x00465400
#define CONNLOG_EMI_OFFSET_BT 0x00033c00
#endif
#define CONNLOG_EMI_SIZE_WIFI (192*1024)
#define CONNLOG_EMI_SIZE_BT (64*1024)
#define CONNLOG_EMI_BLOCK_WIFI (128*1024)
#define CONNLOG_EMI_BLOCK_WIFI_MCU (32*1024)
#define CONNLOG_EMI_BLOCK_BT (32*1024)
#define CONNLOG_EMI_BLOCK_BT_MCU (16*1024)
static struct connlog_emi_config g_connsyslog_config[CONN_DEBUG_TYPE_END] = {
/* Wi-Fi config */
{CONNLOG_EMI_OFFSET_WIFI, CONNLOG_EMI_SIZE_WIFI,
{{CONN_DEBUG_TYPE_WIFI, CONNLOG_EMI_BLOCK_WIFI},
{CONN_DEBUG_TYPE_WIFI_MCU, CONNLOG_EMI_BLOCK_WIFI_MCU}}},
{CONNLOG_EMI_OFFSET_BT, CONNLOG_EMI_SIZE_BT,
{{CONN_DEBUG_TYPE_BT, CONNLOG_EMI_BLOCK_BT},
{CONN_DEBUG_TYPE_BT_MCU, CONNLOG_EMI_BLOCK_BT_MCU}}},
};
#endif /* _PLATFORM_MT6879_CONNSYSLOG_H_ */

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#ifndef _PLATFORM_MT6879_CONSYS_REG_H_
#define _PLATFORM_MT6879_CONSYS_REG_H_
#include "consys_reg_base.h"
enum consys_base_addr_index {
INFRACFG_AO_BASE_INDEX = 0, /* 0x1000_1000 infracfg_ao */
GPIO_BASE_INDEX = 1, /* 0x1000_5000 GPIO */
IOCFG_RT_BASE_INDEX = 2, /* 0x11ec_0000 IOCFG_RT */
CONN_INFRA_RGU_ON_BASE_INDEX = 3, /* 0x1800_0000 conn_infra_rgu_on */
CONN_INFRA_CFG_ON_BASE_INDEX = 4, /* 0x1800_1000 conn_infra_cfg_on */
CONN_WT_SLP_CTL_REG_BASE_INDEX = 5, /* 0x1800_3000 conn_wt_slp_ctl_reg */
CONN_INFRA_BUS_CR_ON_BASE_INDEX = 6, /* 0x1800_e000 conn_infra_bus_cr_on */
CONN_INFRA_CFG_BASE_INDEX = 7, /* 0x1801_1000 conn_infra_cfg */
CONN_INFRA_CLKGEN_TOP_BASE_INDEX = 8, /* 0x1801_2000 conn_infra_clkgen_top */
CONN_VON_BUS_BCRM_BASE_INDEX = 9, /* 0x1802_0000 conn_von_bus_bcrm */
CONN_INFRA_DBG_CTL_BASE_INDEX = 10, /* 0x1802_3000 conn_dbg_ctl */
CONN_INFRA_ON_BUS_BCRM_BASE_INDEX = 11, /* 0x1803_b000 conn_infra_on_bus_bcrm */
CONN_THERM_CTL_BASE_INDEX = 12, /* 0x1804_0000 conn_therm_ctl */
CONN_AFE_CTL_BASE_INDEX = 13, /* 0x1804_1000 conn_afe_ctl */
CONN_RF_SPI_MST_REG_BASE_INDEX = 14, /* 0x1804_2000 conn_rf_spi_mst_reg */
CONN_INFRA_BUS_CR_BASE_INDEX = 15, /* 0x1804_b000 conn_infra_bus_cr */
CONN_INFRA_OFF_DEBUG_CTRL_AO_BASE_INDEX = 16, /* 0x1804_d000 conn_infra_off_debug_ctrl_ao */
CONN_INFRA_OFF_BUS_BCRM_BASE_INDEX = 17, /* 0x1804_f000 conn_infra_off_bus_bcrm */
CONN_INFRA_SYSRAM_SW_CR_BASE_INDEX = 18, /* 0x1805_3800 conn_infra_sysram_sw_cr */
CONN_HOST_CSR_TOP_BASE_INDEX = 19, /* 0x1806_0000 conn_host_csr_top */
CONN_SEMAPHORE_BASE_INDEX = 20, /* 0x1807_0000 conn_semaphore */
SPM_BASE_INDEX = 21, /* 0x1c00_1000 spm */
TOP_RGU_BASE_INDEX = 22, /* 0x1c00_7000 top_rgu */
CONSYS_BASE_ADDR_MAX
};
struct consys_base_addr {
struct consys_reg_base_addr reg_base_addr[CONSYS_BASE_ADDR_MAX];
};
extern struct consys_base_addr conn_reg_mt6879;
#define CONN_REG_INFRACFG_AO_ADDR conn_reg_mt6879.reg_base_addr[INFRACFG_AO_BASE_INDEX].vir_addr
#define CONN_REG_GPIO_ADDR conn_reg_mt6879.reg_base_addr[GPIO_BASE_INDEX].vir_addr
#define CONN_REG_IOCFG_RT_ADDR conn_reg_mt6879.reg_base_addr[IOCFG_RT_BASE_INDEX].vir_addr
#define CONN_REG_CONN_INFRA_RGU_ON_ADDR conn_reg_mt6879.reg_base_addr[CONN_INFRA_RGU_ON_BASE_INDEX].vir_addr
#define CONN_REG_CONN_INFRA_CFG_ON_ADDR conn_reg_mt6879.reg_base_addr[CONN_INFRA_CFG_ON_BASE_INDEX].vir_addr
#define CONN_REG_CONN_WT_SLP_CTL_REG_ADDR conn_reg_mt6879.reg_base_addr[CONN_WT_SLP_CTL_REG_BASE_INDEX].vir_addr
#define CONN_REG_CONN_INFRA_BUS_CR_ON_ADDR conn_reg_mt6879.reg_base_addr[CONN_INFRA_BUS_CR_ON_BASE_INDEX].vir_addr
#define CONN_REG_CONN_INFRA_CFG_ADDR conn_reg_mt6879.reg_base_addr[CONN_INFRA_CFG_BASE_INDEX].vir_addr
#define CONN_REG_CONN_INFRA_CLKGEN_TOP_ADDR conn_reg_mt6879.reg_base_addr[CONN_INFRA_CLKGEN_TOP_BASE_INDEX].vir_addr
#define CONN_REG_CONN_VON_BUS_BCRM_ADDR conn_reg_mt6879.reg_base_addr[CONN_VON_BUS_BCRM_BASE_INDEX].vir_addr
#define CONN_REG_CONN_INFRA_DBG_CTL_ADDR conn_reg_mt6879.reg_base_addr[CONN_INFRA_DBG_CTL_BASE_INDEX].vir_addr
#define CONN_REG_CONN_INFRA_ON_BUS_BCRM_ADDR conn_reg_mt6879.reg_base_addr[CONN_INFRA_ON_BUS_BCRM_BASE_INDEX].vir_addr
#define CONN_REG_CONN_THERM_CTL_ADDR conn_reg_mt6879.reg_base_addr[CONN_THERM_CTL_BASE_INDEX].vir_addr
#define CONN_REG_CONN_AFE_CTL_ADDR conn_reg_mt6879.reg_base_addr[CONN_AFE_CTL_BASE_INDEX].vir_addr
#define CONN_REG_CONN_RF_SPI_MST_REG_ADDR conn_reg_mt6879.reg_base_addr[CONN_RF_SPI_MST_REG_BASE_INDEX].vir_addr
#define CONN_REG_CONN_INFRA_BUS_CR_ADDR conn_reg_mt6879.reg_base_addr[CONN_INFRA_BUS_CR_BASE_INDEX].vir_addr
#define CONN_REG_CONN_INFRA_OFF_DEBUG_CTRL_AO_ADDR conn_reg_mt6879.reg_base_addr[CONN_INFRA_OFF_DEBUG_CTRL_AO_BASE_INDEX].vir_addr
#define CONN_REG_CONN_INFRA_OFF_BUS_BCRM_ADDR conn_reg_mt6879.reg_base_addr[CONN_INFRA_OFF_BUS_BCRM_BASE_INDEX].vir_addr
#define CONN_REG_CONN_INFRA_SYSRAM_SW_CR_ADDR conn_reg_mt6879.reg_base_addr[CONN_INFRA_SYSRAM_SW_CR_BASE_INDEX].vir_addr
#define CONN_REG_CONN_HOST_CSR_TOP_ADDR conn_reg_mt6879.reg_base_addr[CONN_HOST_CSR_TOP_BASE_INDEX].vir_addr
#define CONN_REG_CONN_SEMAPHORE_ADDR conn_reg_mt6879.reg_base_addr[CONN_SEMAPHORE_BASE_INDEX].vir_addr
#define CONN_REG_SPM_ADDR conn_reg_mt6879.reg_base_addr[SPM_BASE_INDEX].vir_addr
#define CONN_REG_TOP_RGU_ADDR conn_reg_mt6879.reg_base_addr[TOP_RGU_BASE_INDEX].vir_addr
struct consys_base_addr* get_conn_reg_base_addr_mt6879(void);
#endif /* _PLATFORM_MT6879_CONSYS_REG_H_ */

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#ifndef _PLATFORM_MT6879_CONSYS_REG_OFFSET_H_
#define _PLATFORM_MT6879_CONSYS_REG_OFFSET_H_
#include "mt6879_consys_reg.h"
/**********************************************************************
* infracfg_ao
* Base: 0x1000_1000
* Min offset: 0x10001050
* Max offset: 0x10001ee0
* Size: 0xee4
*********************************************************************/
#define INFRACFG_AO_REG_BASE (CONN_REG_INFRACFG_AO_ADDR)
#define INFRACFG_AO_INFRASYS_PROTECT_EN_STA_0 (INFRACFG_AO_REG_BASE+0xC40)
#define INFRACFG_AO_INFRASYS_PROTECT_EN_STA_1 (INFRACFG_AO_REG_BASE+0xC50)
#define INFRACFG_AO_INFRASYS_PROTECT_RDY_STA_1 (INFRACFG_AO_REG_BASE+0xC5C)
#define INFRACFG_AO_MCU_CONNSYS_PROTECT_EN_STA_0 (INFRACFG_AO_REG_BASE+0xC90)
#define INFRACFG_AO_MCU_CONNSYS_PROTECT_RDY_STA_0 (INFRACFG_AO_REG_BASE+0xC9C)
/**********************************************************************
* GPIO
* Base: 0x1000_5000
* Min offset: 0x0
* Max offset: 0xa68
* Size: 0xa6c
*********************************************************************/
#define GPIO_REG_BASE (CONN_REG_GPIO_ADDR)
#define GPIO_DIR6_SET (GPIO_REG_BASE + 0x0064)
#define GPIO_DOUT6_SET (GPIO_REG_BASE + 0x0164)
#define GPIO_MODE16 (GPIO_REG_BASE + 0x0400)
#define GPIO_MODE23 (GPIO_REG_BASE + 0x0470)
#define GPIO_MODE24 (GPIO_REG_BASE + 0x0480)
#define GPIO_MODE25 (GPIO_REG_BASE + 0x0490)
/**********************************************************************
* IOCFG_RT
* Base: 0x11EC0000
* Size: 0xa14
*********************************************************************/
#define IOCFG_RT_REG_BASE (CONN_REG_IOCFG_RT_ADDR)
#define IOCFG_RT_DRV_CFG0 (IOCFG_RT_REG_BASE + 0x0000)
#define IOCFG_RT_DRV_CFG0_SET (IOCFG_RT_REG_BASE + 0x0004)
#define IOCFG_RT_PD_CFG0_SET (IOCFG_RT_REG_BASE + 0x0084)
#define IOCFG_RT_PD_CFG0_CLR (IOCFG_RT_REG_BASE + 0x0088)
#define IOCFG_RT_PU_CFG0_SET (IOCFG_RT_REG_BASE + 0x00a4)
#define IOCFG_RT_PU_CFG0_CLR (IOCFG_RT_REG_BASE + 0x00a8)
/**********************************************************************
* conn_infra_rgu_on
* Base: 0x1800_0000
* Size: 0x470
*********************************************************************/
#include "conn_rgu_on.h"
/**********************************************************************
* conn_infra_cfg_on
* Base: 0x1800_1000
* Size: 0x658
*********************************************************************/
#include "conn_cfg_on.h"
/**********************************************************************
* conn_wt_slp_ctl_reg
* Base: 0x1800_3000
* Size: 0x204
*********************************************************************/
#include "conn_wt_slp_ctl_reg.h"
/**********************************************************************
* conn_infra_bus_cr_on
* Base: 0x1800_e000
* Min offset: 0x1800e000
* Max offset: 0x1800e120
* Size: 0x124
*********************************************************************/
#include "conn_bus_cr_on.h"
/**********************************************************************
* conn_infra_cfg
* Base: 0x1801_1000
* Size: 0x138
*********************************************************************/
#include "conn_cfg.h"
#define CONN_HW_VER 0x02050100
/**********************************************************************
* conn_infra_clkgen_top
* Base: 0x1801_2000
* Size: 0x098
*********************************************************************/
#include "conn_clkgen_top.h"
/**********************************************************************
* conn_von_bus_bcrm
* Base: 0x1802_0000
* Size: 0x04c
*********************************************************************/
#include "conn_von_bus_bcrm.h"
/**********************************************************************
* conn_dbg_ctl
* Base: 0x1802_3000
* Size: 0xe28
*********************************************************************/
#include "conn_dbg_ctl.h"
/**********************************************************************
* conn_infra_on_bus_bcrm
* Base: 0x1803_b000
* Size: 0x018
*********************************************************************/
#include "conn_on_bus_bcrm.h"
/**********************************************************************
* conn_therm_ctl
* Base: 0x1804_0000
* Size: 0x2c
*********************************************************************/
#include "conn_therm_ctl.h"
/**********************************************************************
* conn_afe_ctl
* Base: 0x1804_1000
* Size: 0x128
*********************************************************************/
#include "conn_afe_ctl.h"
/**********************************************************************
* conn_rf_spi_mst_reg
* Base: 0x1804_2000
* Size: 0x324
*********************************************************************/
#include "conn_rf_spi_mst_reg.h"
/* For RFSPI table usage */
#define CONN_RF_SPI_MST_REG_SPI_STA_OFFSET 0x0000
#define CONN_RF_SPI_MST_REG_SPI_WF_ADDR_OFFSET 0x0010
#define CONN_RF_SPI_MST_REG_SPI_WF_WDAT_OFFSET 0x0014
#define CONN_RF_SPI_MST_REG_SPI_WF_RDAT_OFFSET 0x0018
#define CONN_RF_SPI_MST_REG_SPI_BT_ADDR_OFFSET 0x0020
#define CONN_RF_SPI_MST_REG_SPI_BT_WDAT_OFFSET 0x0024
#define CONN_RF_SPI_MST_REG_SPI_BT_RDAT_OFFSET 0x0028
#define CONN_RF_SPI_MST_REG_SPI_FM_ADDR_OFFSET 0x0030
#define CONN_RF_SPI_MST_REG_SPI_FM_WDAT_OFFSET 0x0034
#define CONN_RF_SPI_MST_REG_SPI_FM_RDAT_OFFSET 0x0038
#define CONN_RF_SPI_MST_REG_SPI_TOP_ADDR_OFFSET 0x0050
#define CONN_RF_SPI_MST_REG_SPI_TOP_WDAT_OFFSET 0x0054
#define CONN_RF_SPI_MST_REG_SPI_TOP_RDAT_OFFSET 0x0058
#define CONN_RF_SPI_MST_REG_SPI_GPS_GPS_ADDR_OFFSET 0x0210
#define CONN_RF_SPI_MST_REG_SPI_GPS_GPS_WDAT_OFFSET 0x0214
#define CONN_RF_SPI_MST_REG_SPI_GPS_GPS_RDAT_OFFSET 0x0218
/**********************************************************************
* conn_infra_bus_cr
* Base: 0x1804_b000
* Size: 0x414
*********************************************************************/
#include "conn_bus_cr.h"
/**********************************************************************
* conn_infra_off_debug_ctrl_ao
* Base: 0x1804_d000
* Size: 0x41c
*********************************************************************/
#include "conn_off_debug_ctrl_ao.h"
/**********************************************************************
* conn_infra_off_bus_bcrm
* Base: 0x1804_f000
* Size: 0x148
*********************************************************************/
#include "conn_off_bus_bcrm.h"
/**********************************************************************
* conn_infra_sysram_sw_cr
* Base: 0x1805_3800
* Size: 4K (0x1805_3800~0x1805_4000)
*********************************************************************/
#define CONN_INFRA_SYSRAM_SW_CR_BASE (CONN_REG_CONN_INFRA_SYSRAM_SW_CR_ADDR)
#define CONN_INFRA_SYSRAM_SW_CR_A_DIE_CHIP_ID (CONN_INFRA_SYSRAM_SW_CR_BASE + 0x000)
#define CONN_INFRA_SYSRAM_SW_CR_A_DIE_EFUSE_DATA_0 (CONN_INFRA_SYSRAM_SW_CR_BASE + 0x004)
#define CONN_INFRA_SYSRAM_SW_CR_A_DIE_EFUSE_DATA_1 (CONN_INFRA_SYSRAM_SW_CR_BASE + 0x008)
#define CONN_INFRA_SYSRAM_SW_CR_A_DIE_EFUSE_DATA_2 (CONN_INFRA_SYSRAM_SW_CR_BASE + 0x00C)
#define CONN_INFRA_SYSRAM_SW_CR_A_DIE_EFUSE_DATA_3 (CONN_INFRA_SYSRAM_SW_CR_BASE + 0x010)
#define CONN_INFRA_SYSRAM_SW_CR_D_DIE_EFUSE (CONN_INFRA_SYSRAM_SW_CR_BASE + 0x020)
#define CONN_INFRA_SYSRAM_SW_CR_RADIO_STATUS (CONN_INFRA_SYSRAM_SW_CR_BASE + 0x034)
#define CONN_INFRA_SYSRAM_SW_CR_BUILD_MODE (CONN_INFRA_SYSRAM_SW_CR_BASE + 0x038)
#define CONN_INFRA_SYSRAM_SW_CR_CLOCK_TYPE (CONN_INFRA_SYSRAM_SW_CR_BASE + 0x03C)
#define CONN_INFRA_SYSRAM_SW_CR_MCU_LOG_CONTROL (CONN_INFRA_SYSRAM_SW_CR_BASE + 0x040)
/* Need to clean full region */
#define CONN_INFRA_SYSRAM_BASE 0x18050000
#define CONN_INFRA_SYSRAM_SIZE (20 * 1024)
/**********************************************************************
* conn_host_csr_top
* Base: 0x1806_0000
* Size: 0xc08
*********************************************************************/
#include "conn_host_csr_top.h"
/**********************************************************************
* conn_semaphore
* Base: 0x1807_0000
* Size: 0x8004
*********************************************************************/
#include "conn_semaphore.h"
/**********************************************************************/
/* A-die CR */
/**********************************************************************/
#define ATOP_CHIP_ID 0x02c
#define ATOP_RG_TOP_THADC_BG 0x034
#define ATOP_RG_TOP_THADC 0x038
#define ATOP_WRI_CTR2 0x064
#define ATOP_RG_ENCAL_WBTAC_IF_SW 0x070
#define ATOP_SMCTK11 0x0BC
#define ATOP_EFUSE_CTRL 0x108
#define ATOP_EFUSE_RDATA0 0x130
#define ATOP_EFUSE_RDATA1 0x134
#define ATOP_EFUSE_RDATA2 0x138
#define ATOP_EFUSE_RDATA3 0x13c
#define ATOP_RG_WF0_TOP_01 0x380
#define ATOP_RG_WF0_BG 0x384
#define ATOP_RG_WF1_TOP_01 0x390
#define ATOP_RG_WF1_BG 0x394
#define ATOP_RG_TOP_XTAL_01 0xA18
#define ATOP_RG_TOP_XTAL_02 0xA1C
/**********************************************************************
* spm
* Base: 0x1c00_1000
* Size: 0xfb0
*********************************************************************/
#define SPM_REG_BASE (CONN_REG_SPM_ADDR)
#define SPM_POWERON_CONFIG_EN (SPM_REG_BASE + 0x0000)
#define SPM_CONN_PWR_CON (SPM_REG_BASE + 0x0E04)
#define SPM_OTHER_PWR_STATUS (SPM_REG_BASE + 0x0E04)
#define SPM_PWR_STATUS_2ND (SPM_REG_BASE + 0x0E04)
/**********************************************************************
* TOPRGU
* Base: 0x1c00_7000
* Size: 0x51c
*********************************************************************/
#define TOPRGU_REG_BASE (CONN_REG_TOP_RGU_ADDR)
#define TOPRGU_WDT_SWSYSRST (TOPRGU_REG_BASE + 0x200)
/**********************************************************************
* Misc
*********************************************************************/
#define RC_CENTRAL_CFG1 0x1C00D004
#define DCXO_DIGCLK_ELR 0x7f4
#endif /* _PLATFORM_MT6879_CONSYS_REG_OFFSET_H_ */

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2020 MediaTek Inc.
*/
/* AUTO-GENERATED FILE. DO NOT MODIFY.
*
* This file, mt6879_debug_gen.h was automatically generated
* by the tool from the DEBUG data DE provided.
* It should not be modified by hand.
*
* Reference debug file,
* - [Lxxxn]connsys_power_debug.xlsx (Modified date: 2021-08-18)
* - [Lxxxn]conn_infra_bus_debug_ctrl.xlsx (Modified date: 2021-10-14)
*/
#ifndef _PLATFORM_MT6879_DEBUG_GEN_H_
#define _PLATFORM_MT6879_DEBUG_GEN_H_
#define CONN_DEBUG_INFO_SIZE 256
#define DEBUG_TAG_SIZE 10
struct conn_debug_info_mt6879 {
char tag[CONN_DEBUG_INFO_SIZE][DEBUG_TAG_SIZE];
unsigned int wr_addr[CONN_DEBUG_INFO_SIZE];
int wr_addr_lsb[CONN_DEBUG_INFO_SIZE];
int wr_addr_msb[CONN_DEBUG_INFO_SIZE];
unsigned int wr_data[CONN_DEBUG_INFO_SIZE];
unsigned int rd_addr[CONN_DEBUG_INFO_SIZE];
unsigned int rd_data[CONN_DEBUG_INFO_SIZE];
int length;
};
void consys_debug_init_mt6879_debug_gen(void);
void consys_debug_deinit_mt6879_debug_gen(void);
void update_debug_read_info_mt6879_debug_gen(
struct conn_debug_info_mt6879 *info,
char *tag,
unsigned int rd_addr,
unsigned int rd_data);
void update_debug_write_info_mt6879_debug_gen(
struct conn_debug_info_mt6879 *info,
char *tag,
unsigned int wr_addr,
int wr_addr_lsb,
int wr_addr_msb,
unsigned int wr_data);
void consys_print_power_debug_dbg_level_0_mt6879_debug_gen(
int level,
struct conn_debug_info_mt6879 *pdbg_level_0_info);
void consys_print_power_debug_dbg_level_1_mt6879_debug_gen(
int level,
struct conn_debug_info_mt6879 *pdbg_level_1_info);
void consys_print_power_debug_dbg_level_2_mt6879_debug_gen(
int level,
struct conn_debug_info_mt6879 *pdbg_level_2_info);
void consys_print_bus_debug_dbg_level_1_mt6879_debug_gen(
int level,
struct conn_debug_info_mt6879 *pdbg_level_1_info);
void consys_print_bus_debug_dbg_level_2_mt6879_debug_gen(
int level,
struct conn_debug_info_mt6879 *pdbg_level_2_info);
void consys_print_bus_slpprot_debug_dbg_level_2_mt6879_debug_gen(
int level,
struct conn_debug_info_mt6879 *pdbg_level_2_info);
void consys_print_bus_slpprot_debug_dbg_level_0_mt6879_debug_gen(
int level,
struct conn_debug_info_mt6879 *pdbg_level_0_info);
/*************************************************************************************/
/* Base: SPM_REG_BASE (0x1C00_1000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_SPM_REQ_STA_1_OFFSET_ADDR 0x83C
#define CONSYS_DBG_GEN_SPM_REQ_STA_2_OFFSET_ADDR 0x840
#define CONSYS_DBG_GEN_CONN_PWR_CON_OFFSET_ADDR 0xE04
/*************************************************************************************/
/* Base: CONSYS_DBG_GEN_SRCLKENRC_BASE_ADDR (0x1C00_D000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_SRCLKENRC_BASE_ADDR 0x1C00D000
#define CONSYS_DBG_GEN_CMD_STA_0_OFFSET_ADDR 0x104
#define CONSYS_DBG_GEN_M06_REQ_STA_0_OFFSET_ADDR 0x12C
#define CONSYS_DBG_GEN_M07_REQ_STA_0_OFFSET_ADDR 0x130
#define CONSYS_DBG_GEN_M08_REQ_STA_0_OFFSET_ADDR 0x134
#define CONSYS_DBG_GEN_M09_REQ_STA_0_OFFSET_ADDR 0x138
#define CONSYS_DBG_GEN_DEBUG_TRACE_0_LSB_OFFSET_ADDR 0x700
#define CONSYS_DBG_GEN_DEBUG_TRACE_0_MSB_OFFSET_ADDR 0x704
#define CONSYS_DBG_GEN_DEBUG_TRACE_1_LSB_OFFSET_ADDR 0x708
#define CONSYS_DBG_GEN_DEBUG_TRACE_1_MSB_OFFSET_ADDR 0x70C
#define CONSYS_DBG_GEN_DEBUG_TRACE_2_LSB_OFFSET_ADDR 0x710
#define CONSYS_DBG_GEN_DEBUG_TRACE_2_MSB_OFFSET_ADDR 0x714
#define CONSYS_DBG_GEN_DEBUG_TRACE_3_LSB_OFFSET_ADDR 0x718
#define CONSYS_DBG_GEN_DEBUG_TRACE_3_MSB_OFFSET_ADDR 0x71C
#define CONSYS_DBG_GEN_DEBUG_TRACE_4_LSB_OFFSET_ADDR 0x720
#define CONSYS_DBG_GEN_DEBUG_TRACE_4_MSB_OFFSET_ADDR 0x724
#define CONSYS_DBG_GEN_DEBUG_TRACE_5_LSB_OFFSET_ADDR 0x728
#define CONSYS_DBG_GEN_DEBUG_TRACE_5_MSB_OFFSET_ADDR 0x72C
#define CONSYS_DBG_GEN_DEBUG_TRACE_6_LSB_OFFSET_ADDR 0x730
#define CONSYS_DBG_GEN_DEBUG_TRACE_6_MSB_OFFSET_ADDR 0x734
#define CONSYS_DBG_GEN_DEBUG_TRACE_7_LSB_OFFSET_ADDR 0x738
#define CONSYS_DBG_GEN_DEBUG_TRACE_7_MSB_OFFSET_ADDR 0x73C
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_LSB_OFFSET_ADDR 0x740
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_MSB_OFFSET_ADDR 0x744
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_LSB_OFFSET_ADDR 0x748
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_MSB_OFFSET_ADDR 0x74C
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_LSB_OFFSET_ADDR 0x750
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_MSB_OFFSET_ADDR 0x754
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_LSB_OFFSET_ADDR 0x758
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_MSB_OFFSET_ADDR 0x75C
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_LSB_OFFSET_ADDR 0x760
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_MSB_OFFSET_ADDR 0x764
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_LSB_OFFSET_ADDR 0x768
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_MSB_OFFSET_ADDR 0x76C
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_LSB_OFFSET_ADDR 0x770
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_MSB_OFFSET_ADDR 0x774
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_LSB_OFFSET_ADDR 0x778
#define CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_MSB_OFFSET_ADDR 0x77C
/*************************************************************************************/
/* Base: CONSYS_DBG_GEN_TOPCKGEN_BASE_ADDR (0x1000_0000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_TOPCKGEN_BASE_ADDR 0x10000000
#define CONSYS_DBG_GEN_CLK_CFG_17_OFFSET_ADDR 0x180
/*************************************************************************************/
/* Base: CONN_HOST_CSR_TOP_BASE (0x1806_0000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR 0x15C
#define CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR 0xa04
#define CONSYS_DBG_GEN_CONNSYS_PWR_STATES_OFFSET_ADDR 0xA10
/*************************************************************************************/
/* Base: CONN_CFG_BASE (0x1801_1000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_PLL_STATUS_OFFSET_ADDR 0x30
#define CONSYS_DBG_GEN_EMI_CTL_0_OFFSET_ADDR 0x100
#define CONSYS_DBG_GEN_EMI_PROBE_1_OFFSET_ADDR 0x134
/*************************************************************************************/
/* Base: CONN_CLKGEN_TOP_BASE (0x1801_2000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_CKGEN_BUS_OFFSET_ADDR 0x50
/*************************************************************************************/
/* Base: CONN_CFG_ON_BASE (0x1800_1000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_CONN_INFRA_CFG_RC_STATUS_OFFSET_ADDR 0x344
#define CONSYS_DBG_GEN_CONN_INFRA_CONN2AP_SLP_STATUS_OFFSET_ADDR 0x404
#define CONSYS_DBG_GEN_CONN_INFRA_CONN2AP_EMI_SLP_STATUS_OFFSET_ADDR 0x408
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_BUS_SLP_STATUS_OFFSET_ADDR 0x434
#define CONSYS_DBG_GEN_CONN_INFRA_WF_SLP_STATUS_OFFSET_ADDR 0x444
#define CONSYS_DBG_GEN_GALS_CONN2BT_SLP_STATUS_OFFSET_ADDR 0x454
#define CONSYS_DBG_GEN_GALS_BT2CONN_SLP_STATUS_OFFSET_ADDR 0x464
#define CONSYS_DBG_GEN_GALS_CONN2GPS_SLP_STATUS_OFFSET_ADDR 0x474
#define CONSYS_DBG_GEN_GALS_GPS2CONN_SLP_STATUS_OFFSET_ADDR 0x484
/*************************************************************************************/
/* Base: CONN_RGU_ON_BASE (0x1800_0000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_WFSYS_ON_TOP_PWR_ST_OFFSET_ADDR 0x400
#define CONSYS_DBG_GEN_BGFSYS_ON_TOP_PWR_ST_OFFSET_ADDR 0x404
/*************************************************************************************/
/* Base: CONN_WT_SLP_CTL_REG_BASE (0x1800_3000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_WB_CK_STA_OFFSET_ADDR 0xA8
#define CONSYS_DBG_GEN_WB_SLP_TOP_CK_0_OFFSET_ADDR 0x120
#define CONSYS_DBG_GEN_WB_SLP_TOP_CK_1_OFFSET_ADDR 0x124
#define CONSYS_DBG_GEN_WB_SLP_TOP_CK_2_OFFSET_ADDR 0x128
#define CONSYS_DBG_GEN_WB_SLP_TOP_CK_3_OFFSET_ADDR 0x12C
#define CONSYS_DBG_GEN_WB_SLP_TOP_CK_4_OFFSET_ADDR 0x130
#define CONSYS_DBG_GEN_WB_SLP_TOP_CK_5_OFFSET_ADDR 0x134
/*************************************************************************************/
/* Base: CONSYS_DBG_GEN_CONN_INFRA_SYSRAM_BASE_OFFSET_ADDR (0x1805_0000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_CONN_INFRA_SYSRAM_BASE_OFFSET_ADDR 0x18050000
/*************************************************************************************/
/* Base: CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR (0x1802_3000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR 0x18023000
#define CONSYS_DBG_GEN_CONN_INFRA_BUS_TIMEOUT_IRQ_OFFSET_ADDR 0x400
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_BUS_DBG_OUT_OFFSET_ADDR 0x404
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_BUS_DBG_SEL_OFFSET_ADDR 0x408
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUGSYS_CTRL_OFFSET_ADDR 0x40c
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_INFO_OFFSET_ADDR 0x410
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_ADDR_OFFSET_ADDR 0x414
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_WDATA_OFFSET_ADDR 0x418
#define CONSYS_DBG_GEN_CONN_INFRA_VON_BUS_DEBUG_INFO_OFFSET_ADDR 0x41c
/*************************************************************************************/
/* Base: CONN_BUS_CR_ON_BASE (0x1800_e000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_0_OFFSET_ADDR 0x3c
#define CONSYS_DBG_GEN_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_1_OFFSET_ADDR 0x40
#define CONSYS_DBG_GEN_CONN_INFRA_ON_BUS_APB_TIMEOUT_INFO_2_OFFSET_ADDR 0x44
/*************************************************************************************/
/* Base: CONN_OFF_DEBUG_CTRL_AO_BASE (0x1804_d000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUG_CTRL_AO_1804d000_OFFSET_ADDR 0x0
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUG_CTRL_AO_1804d004_OFFSET_ADDR 0x4
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUG_CTRL_AO_1804d008_OFFSET_ADDR 0x8
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUG_CTRL_AO_1804d400_OFFSET_ADDR 0x400
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUG_CTRL_AO_1804d404_OFFSET_ADDR 0x404
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUG_CTRL_AO_1804d408_OFFSET_ADDR 0x408
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUG_CTRL_AO_1804d40c_OFFSET_ADDR 0x40c
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUG_CTRL_AO_1804d410_OFFSET_ADDR 0x410
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUG_CTRL_AO_1804d414_OFFSET_ADDR 0x414
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUG_CTRL_AO_1804d418_OFFSET_ADDR 0x418
/*************************************************************************************/
/* Base: INFRACFG_AO_REG_BASE (0x1000_1000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_INFRASYS_PROTECT_RDY_STA_1_OFFSET_ADDR 0xc5c
#define CONSYS_DBG_GEN_MCU_CONNSYS_PROTECT_RDY_STA_0_OFFSET_ADDR 0xc9c
#endif /* _PLATFORM_MT6879_DEBUG_GEN_H_ */

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drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/mt6879_emi.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#ifndef _PLATFORM_MT6879_EMI_H_
#define _PLATFORM_MT6879_EMI_H_
#endif /* _PLATFORM_MT6879_EMI_H_ */

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drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/mt6879_pmic.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#ifndef _PLATFORM_MT6879_PMIC_H_
#define _PLATFORM_MT6879_PMIC_H_
#define MT6363_BUCK_VS2_VOTER_CON0_SET_ADDR 0x149b
#define MT6363_BUCK_VS2_VOTER_CON0_CLR_ADDR 0x149c
#define MT6363_RG_LDO_VRFIO18_MON_ADDR 0x1bd1
#define MT6363_RG_LDO_VRFIO18_RC6_OP_EN_ADDR 0x1bd2
#define MT6363_RG_LDO_VRFIO18_RC6_OP_CFG_ADDR 0x1bd5
#define MT6363_RG_LDO_VRFIO18_RC6_OP_MODE_ADDR 0x1bd8
#define MT6363_RG_LDO_VRFIO18_RC7_OP_EN_ADDR 0x1bd2
#define MT6363_RG_LDO_VRFIO18_RC7_OP_CFG_ADDR 0x1bd5
#define MT6363_RG_LDO_VRFIO18_RC7_OP_MODE_ADDR 0x1bd8
#define MT6363_RG_LDO_VRFIO18_RC8_OP_EN_ADDR 0x1bd3
#define MT6363_RG_LDO_VRFIO18_RC8_OP_CFG_ADDR 0x1bd6
#define MT6363_RG_LDO_VRFIO18_RC8_OP_MODE_ADDR 0x1bd9
#define MT6363_RG_LDO_VRFIO18_RC9_OP_EN_ADDR 0x1bd3
#define MT6363_RG_LDO_VRFIO18_RC9_OP_CFG_ADDR 0x1bd6
#define MT6363_RG_LDO_VRFIO18_RC9_OP_MODE_ADDR 0x1bd9
#define MT6363_RG_LDO_VRFIO18_HW0_OP_EN_ADDR 0x1bd4
#define MT6363_RG_LDO_VRFIO18_HW0_OP_CFG_ADDR 0x1bd7
#define MT6363_RG_LDO_VRFIO18_HW0_OP_MODE_ADDR 0x1bda
#define MT6363_RG_LDO_VCN13_MON_ADDR 0x1d0b
#define MT6363_RG_LDO_VCN13_RC6_OP_EN_ADDR 0x1d14
#define MT6363_RG_LDO_VCN13_RC6_OP_CFG_ADDR 0x1d17
#define MT6363_RG_LDO_VCN13_RC6_OP_MODE_ADDR 0x1d1a
#define MT6363_RG_LDO_VCN13_RC7_OP_EN_ADDR 0x1d14
#define MT6363_RG_LDO_VCN13_RC7_OP_CFG_ADDR 0x1d17
#define MT6363_RG_LDO_VCN13_RC7_OP_MODE_ADDR 0x1d1a
#define MT6363_RG_LDO_VCN13_RC8_OP_EN_ADDR 0x1d15
#define MT6363_RG_LDO_VCN13_RC8_OP_CFG_ADDR 0x1d18
#define MT6363_RG_LDO_VCN13_RC8_OP_MODE_ADDR 0x1d1b
#define MT6363_RG_LDO_VCN13_RC9_OP_EN_ADDR 0x1d15
#define MT6363_RG_LDO_VCN13_RC9_OP_CFG_ADDR 0x1d18
#define MT6363_RG_LDO_VCN13_RC9_OP_MODE_ADDR 0x1d1b
#define MT6363_RG_LDO_VCN13_HW0_OP_EN_ADDR 0x1d16
#define MT6363_RG_LDO_VCN13_HW0_OP_CFG_ADDR 0x1d19
#define MT6363_RG_LDO_VCN13_HW0_OP_MODE_ADDR 0x1d1c
#define MT6368_RG_LDO_VCN33_1_MON_ADDR 0x1cc4
#define MT6368_RG_LDO_VCN33_1_RC7_OP_EN_ADDR 0x1cc5
#define MT6368_RG_LDO_VCN33_1_RC7_OP_CFG_ADDR 0x1cc8
#define MT6368_RG_LDO_VCN33_1_RC7_OP_MODE_ADDR 0x1ccb
#define MT6368_RG_LDO_VCN33_1_RC8_OP_EN_ADDR 0x1cc6
#define MT6368_RG_LDO_VCN33_1_RC8_OP_CFG_ADDR 0x1cc9
#define MT6368_RG_LDO_VCN33_1_RC8_OP_MODE_ADDR 0x1ccc
#define MT6368_RG_LDO_VCN33_1_HW0_OP_EN_ADDR 0x1cc7
#define MT6368_RG_LDO_VCN33_1_HW0_OP_CFG_ADDR 0x1cca
#define MT6368_RG_LDO_VCN33_1_HW0_OP_MODE_ADDR 0x1ccd
#define MT6368_RG_LDO_VCN33_2_MON_ADDR 0x1cd2
#define MT6368_RG_LDO_VCN33_2_RC8_OP_EN_ADDR 0x1cd4
#define MT6368_RG_LDO_VCN33_2_RC8_OP_CFG_ADDR 0x1cd7
#define MT6368_RG_LDO_VCN33_2_RC8_OP_MODE_ADDR 0x1cda
#define MT6368_RG_LDO_VCN33_2_HW0_OP_EN_ADDR 0x1cd5
#define MT6368_RG_LDO_VCN33_2_HW0_OP_CFG_ADDR 0x1cd8
#define MT6368_RG_LDO_VCN33_2_HW0_OP_MODE_ADDR 0x1cdb
#define MT6368_RG_LDO_VANT18_MON_ADDR 0x1c27
#define MT6368_RG_LDO_VANT18_RC6_OP_EN_ADDR 0x1c28
#define MT6368_RG_LDO_VANT18_RC6_OP_CFG_ADDR 0x1c2b
#define MT6368_RG_LDO_VANT18_RC6_OP_MODE_ADDR 0x1c2e
#define MT6368_RG_LDO_VANT18_RC10_OP_EN_ADDR 0x1c29
#define MT6368_RG_LDO_VANT18_RC10_OP_CFG_ADDR 0x1c2c
#define MT6368_RG_LDO_VANT18_RC10_OP_MODE_ADDR 0x1c2f
#define MT6368_RG_LDO_VANT18_HW0_OP_EN_ADDR 0x1c2a
#define MT6368_RG_LDO_VANT18_HW0_OP_CFG_ADDR 0x1c2d
#define MT6368_RG_LDO_VANT18_HW0_OP_MODE_ADDR 0x1c30
void consys_pmic_debug_log_mt6879(void);
#endif /* _PLATFORM_MT6879_PMIC_H_ */

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drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/mt6879_pos.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#ifndef _PLATFORM_MT6879_POS_H_
#define _PLATFORM_MT6879_POS_H_
#include <linux/types.h>
unsigned int consys_emi_set_remapping_reg_mt6879(phys_addr_t, phys_addr_t);
int consys_conninfra_on_power_ctrl_mt6879(unsigned int enable);
int consys_conninfra_wakeup_mt6879(void);
int consys_conninfra_sleep_mt6879(void);
void consys_set_if_pinmux_mt6879(unsigned int enable);
int consys_polling_chipid_mt6879(void);
int connsys_d_die_cfg_mt6879(void);
int connsys_spi_master_cfg_mt6879(unsigned int);
int connsys_a_die_cfg_mt6879(void);
int connsys_afe_wbg_cal_mt6879(void);
int connsys_subsys_pll_initial_mt6879(void);
int connsys_low_power_setting_mt6879(unsigned int, unsigned int);
int consys_sema_acquire_timeout_mt6879(unsigned int index, unsigned int usec);
void consys_sema_release_mt6879(unsigned int index);
int consys_spi_read_mt6879(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data);
int consys_spi_write_mt6879(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data);
int consys_spi_update_bits_mt6879(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data, unsigned int mask);
int consys_spi_clock_switch_mt6879(enum connsys_spi_speed_type type);
int consys_subsys_status_update_mt6879(bool, int);
bool consys_is_rc_mode_enable_mt6879(void);
int connsys_adie_top_ck_en_ctl_mt6879(bool);
int consys_get_sleep_mode_mt6879(void);
int consys_spi_read_nolock_mt6879(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data);
int consys_spi_write_nolock_mt6879(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data);
#ifndef CONFIG_FPGA_EARLY_PORTING
void consys_spi_write_offset_range_nolock_mt6879(
enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int value,
unsigned int reg_offset, unsigned int value_offset, unsigned int size);
#endif
#endif /* _PLATFORM_MT6879_POS_H_ */

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drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/include/mt6879_pos_gen.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2020 MediaTek Inc.
*/
/* AUTO-GENERATED FILE. DO NOT MODIFY.
*
* This file, mt6879_pos_gen.h was automatically generated
* by the tool from the POS data DE provided.
* It should not be modified by hand.
*
* Reference POS file,
* - Fxxxxc_power_on_sequence_20210816.xlsx
* - Fxxxxc_conn_infra_sub_task_210811.xlsx
* - conn_infra_cmdbt_instr_autogen_20210902.txt
*/
#ifndef _PLATFORM_MT6879_POS_GEN_H_
#define _PLATFORM_MT6879_POS_GEN_H_
void consys_set_if_pinmux_mt6879_gen(unsigned int enable);
void consys_set_gpio_tcxo_mode_mt6879_gen(unsigned int tcxo_mode, unsigned int enable);
int consys_conninfra_on_power_ctrl_mt6879_gen(unsigned int enable);
void consys_update_ap2conn_hclk_mt6879_gen(void);
int consys_polling_chipid_mt6879_gen(unsigned int *pconsys_ver_id);
unsigned int consys_emi_set_remapping_reg_mt6879_gen(
phys_addr_t con_emi_base_addr,
phys_addr_t md_shared_emi_base_addr,
unsigned int emi_base_addr_offset);
void consys_init_conninfra_sysram_mt6879_gen(void);
void connsys_get_d_die_efuse_mt6879_gen(unsigned int *p_d_die_efuse);
int connsys_d_die_cfg_mt6879_gen(void);
void connsys_wt_slp_top_ctrl_adie6637_mt6879_gen(void);
int connsys_a_die_switch_to_gpio_mode_mt6879_gen(void);
int connsys_adie_top_ck_en_ctl_mt6879_gen(unsigned int enable);
int connsys_a_die_cfg_adie6637_deassert_adie_reset_mt6879_gen(void);
int connsys_a_die_cfg_adie6637_read_adie_id_mt6879_gen(
unsigned int *padie_id,
unsigned int *phw_ver_id);
int connsys_a_die_cfg_adie6637_PART1_mt6879_gen(void);
int connsys_a_die_efuse_read_adie6637_check_efuse_valid_mt6879_gen(bool *pefuse_valid);
void connsys_a_die_efuse_read_adie6637_get_efuse_count_mt6879_gen(unsigned int *pefuse_count);
int connsys_a_die_efuse_read_adie6637_get_efuse0_info_mt6879_gen(
bool efuse_valid,
unsigned int *pefuse0);
int connsys_a_die_efuse_read_adie6637_get_efuse1_info_mt6879_gen(
bool efuse_valid,
unsigned int *pefuse1);
int connsys_a_die_efuse_read_adie6637_get_efuse2_info_mt6879_gen(
bool efuse_valid,
unsigned int *pefuse2);
int connsys_a_die_efuse_read_adie6637_get_efuse3_info_mt6879_gen(
bool efuse_valid,
unsigned int *pefuse3);
int connsys_a_die_thermal_cal_adie6637_conf_mt6879_gen(
bool efuse_valid,
unsigned int *pefuse_list,
unsigned int efuse_size,
int *pslop_molecule,
int *pthermal_b,
int *poffset);
int connsys_a_die_cfg_adie6637_PART2_mt6879_gen(unsigned int hw_ver_id);
int connsys_a_die_cfg_deassert_adie_reset_mt6879_gen(void);
int connsys_a_die_cfg_read_adie_id_mt6879_gen(unsigned int *padie_id, unsigned int *phw_ver_id);
int connsys_a_die_efuse_read_get_efuse_info_mt6879_gen(
void __iomem **psysram_efuse_list,
int *pslop_molecule,
int *pthermal_b,
int *poffset);
int connsys_a_die_cfg_PART2_mt6879_gen(unsigned int hw_ver_id);
int connsys_a_die_switch_to_conn_mode_mt6879_gen(void);
void connsys_wt_slp_top_power_saving_ctrl_adie6637_sleep_mode_1_mt6879_gen(void);
void connsys_wt_slp_top_power_saving_ctrl_adie6637_sleep_mode_2_mt6879_gen(void);
void connsys_wt_slp_top_power_saving_ctrl_adie6637_mt6879_gen(
unsigned int hw_version,
unsigned int sleep_mode);
int connsys_afe_wbg_cal_mt6879_gen(
unsigned int spi_semaphore_index,
unsigned int spi_semaphore_timeout_usec);
int connsys_subsys_pll_initial_xtal_26000k_mt6879_gen(void);
int connsys_low_power_setting_mt6879_gen(void);
int consys_conninfra_wakeup_mt6879_gen(void);
int connsys_adie_clock_buffer_setting_mt6879_gen(
unsigned int curr_status,
unsigned int next_status,
unsigned int hw_version,
unsigned int spi_semaphore_index,
unsigned int spi_semaphore_timeout_usec);
int consys_conninfra_sleep_mt6879_gen(void);
/****************************************************************************************************/
/* Base: GPIO_REG_BASE (0x1000_5000) */
/****************************************************************************************************/
#define CONSYS_GEN_GPIO_DIR6_OFFSET_ADDR 0x60
#define CONSYS_GEN_GPIO_DOUT6_OFFSET_ADDR 0x160
#define CONSYS_GEN_GPIO_MODE21_OFFSET_ADDR 0x450
#define CONSYS_GEN_GPIO_MODE23_OFFSET_ADDR 0x470
#define CONSYS_GEN_GPIO_MODE24_OFFSET_ADDR 0x480
#define CONSYS_GEN_GPIO_MODE25_OFFSET_ADDR 0x490
/****************************************************************************************************/
/* Base: IOCFG_RT_REG_BASE (0x11EC_0000) */
/****************************************************************************************************/
#define CONSYS_GEN_DRV_CFG2_OFFSET_ADDR 0x20
#define CONSYS_GEN_PD_CFG0_OFFSET_ADDR 0x80
#define CONSYS_GEN_PU_CFG0_OFFSET_ADDR 0xA0
/****************************************************************************************************/
/* Base: SPM_REG_BASE (0x1C00_1000) */
/****************************************************************************************************/
#define CONSYS_GEN_POWERON_CONFIG_EN_OFFSET_ADDR 0x0
#define CONSYS_GEN_CONN_PWR_CON_OFFSET_ADDR 0xE04
/****************************************************************************************************/
/* Base: INFRACFG_AO_REG_BASE (0x1000_1000) */
/****************************************************************************************************/
#define CONSYS_GEN_INFRASYS_PROTECT_EN_STA_0_OFFSET_ADDR 0xC40
#define CONSYS_GEN_INFRASYS_PROTECT_RDY_STA_0_OFFSET_ADDR 0xC4C
#define CONSYS_GEN_INFRASYS_PROTECT_EN_STA_1_OFFSET_ADDR 0xC50
#define CONSYS_GEN_INFRASYS_PROTECT_RDY_STA_1_OFFSET_ADDR 0xC5C
#define CONSYS_GEN_MCU_CONNSYS_PROTECT_EN_STA_0_OFFSET_ADDR 0xC90
#define CONSYS_GEN_MCU_CONNSYS_PROTECT_RDY_STA_0_OFFSET_ADDR 0xC9C
/****************************************************************************************************/
/* Base: CONSYS_GEN_TOPCKGEN_BASE_ADDR (0x1000_0000) */
/****************************************************************************************************/
#define CONSYS_GEN_TOPCKGEN_BASE_ADDR 0x10000000
#define CONSYS_GEN_CLK_CFG_UPDATE2_OFFSET_ADDR 0xc
#define CONSYS_GEN_CLK_CFG_16_SET_OFFSET_ADDR 0x114
#define CONSYS_GEN_CLK_CFG_16_CLR_OFFSET_ADDR 0x118
/****************************************************************************************************/
/* Base: CONN_CFG_BASE (0x1801_1000) */
/****************************************************************************************************/
#define CONSYS_GEN_IP_VERSION_OFFSET_ADDR 0x0
#define CONSYS_GEN_EFUSE_OFFSET_ADDR 0x20
#define CONSYS_GEN_CMDBT_FETCH_START_ADDR0_OFFSET_ADDR 0x50
#define CONSYS_GEN_EMI_CTL_0_OFFSET_ADDR 0x100
/****************************************************************************************************/
/* Base: CONSYS_GEN_CONN_HW_VER (0x0205_0100) */
/****************************************************************************************************/
#define CONSYS_GEN_CONN_HW_VER 0x2050100
/****************************************************************************************************/
/* Base: CONN_BUS_CR_BASE (0x1804_B000) */
/****************************************************************************************************/
#define CONSYS_GEN_CONN_INFRA_OFF_BUS_TIMEOUT_CTRL_OFFSET_ADDR 0x24
#define CONSYS_GEN_CONN_INFRA_CONN2AP_EMI_PATH_ADDR_START_OFFSET_ADDR 0x70
#define CONSYS_GEN_CONN_INFRA_CONN2AP_EMI_PATH_ADDR_END_OFFSET_ADDR 0x74
#define CONSYS_GEN_CONN2AP_REMAP_MCU_EMI_BASE_ADDR_OFFSET_ADDR 0x354
#define CONSYS_GEN_CONN2AP_REMAP_MD_SHARE_EMI_BASE_ADDR_OFFSET_ADDR 0x35C
#define CONSYS_GEN_CONN2AP_REMAP_WF_PERI_BASE_ADDR_OFFSET_ADDR 0x364
#define CONSYS_GEN_CONN2AP_REMAP_BT_PERI_BASE_ADDR_OFFSET_ADDR 0x368
#define CONSYS_GEN_CONN2AP_REMAP_GPS_PERI_BASE_ADDR_OFFSET_ADDR 0x36C
#define CONSYS_GEN_SCPSYS_SRAM_BASE_ADDR_OFFSET_ADDR 0x370
#define CONSYS_GEN_LIGHT_SECURITY_CTRL_OFFSET_ADDR 0x374
/****************************************************************************************************/
/* Base: CONSYS_GEN_CONN_INFRA_SYSRAM_BASE_OFFSET_ADDR (0x1805_0000) */
/****************************************************************************************************/
#define CONSYS_GEN_CONN_INFRA_SYSRAM_BASE_OFFSET_ADDR 0x18050000
/****************************************************************************************************/
/* Base: CONN_RGU_ON_BASE (0x1800_0000) */
/****************************************************************************************************/
#define CONSYS_GEN_WFSYS_ON_TOP_PWR_CTL_OFFSET_ADDR 0x10
#define CONSYS_GEN_BGFYS_ON_TOP_PWR_CTL_OFFSET_ADDR 0x20
#define CONSYS_GEN_SYSRAM_HWCTL_PDN_OFFSET_ADDR 0x50
#define CONSYS_GEN_SYSRAM_HWCTL_SLP_OFFSET_ADDR 0x54
#define CONSYS_GEN_CO_EXT_MEM_HWCTL_PDN_OFFSET_ADDR 0x70
#define CONSYS_GEN_CO_EXT_MEM_HWCTL_SLP_OFFSET_ADDR 0x74
/****************************************************************************************************/
/* Base: CONN_WT_SLP_CTL_REG_BASE (0x1800_3000) */
/****************************************************************************************************/
#define CONSYS_GEN_WB_SLP_CTL_OFFSET_ADDR 0x4
#define CONSYS_GEN_WB_BG_ADDR1_OFFSET_ADDR 0x10
#define CONSYS_GEN_WB_BG_ADDR2_OFFSET_ADDR 0x14
#define CONSYS_GEN_WB_BG_ADDR3_OFFSET_ADDR 0x18
#define CONSYS_GEN_WB_BG_ADDR4_OFFSET_ADDR 0x1C
#define CONSYS_GEN_WB_BG_ADDR5_OFFSET_ADDR 0x20
#define CONSYS_GEN_WB_BG_ADDR6_OFFSET_ADDR 0x24
#define CONSYS_GEN_WB_BG_ON1_OFFSET_ADDR 0x30
#define CONSYS_GEN_WB_BG_ON2_OFFSET_ADDR 0x34
#define CONSYS_GEN_WB_BG_ON3_OFFSET_ADDR 0x38
#define CONSYS_GEN_WB_BG_ON4_OFFSET_ADDR 0x3C
#define CONSYS_GEN_WB_BG_ON5_OFFSET_ADDR 0x40
#define CONSYS_GEN_WB_BG_ON6_OFFSET_ADDR 0x44
#define CONSYS_GEN_WB_BG_OFF1_OFFSET_ADDR 0x50
#define CONSYS_GEN_WB_BG_OFF2_OFFSET_ADDR 0x54
#define CONSYS_GEN_WB_BG_OFF3_OFFSET_ADDR 0x58
#define CONSYS_GEN_WB_BG_OFF4_OFFSET_ADDR 0x5C
#define CONSYS_GEN_WB_BG_OFF5_OFFSET_ADDR 0x60
#define CONSYS_GEN_WB_BG_OFF6_OFFSET_ADDR 0x64
#define CONSYS_GEN_WB_WF_CK_ADDR_OFFSET_ADDR 0x70
#define CONSYS_GEN_WB_WF_WAKE_ADDR_OFFSET_ADDR 0x74
#define CONSYS_GEN_WB_WF_ZPS_ADDR_OFFSET_ADDR 0x78
#define CONSYS_GEN_WB_BT_CK_ADDR_OFFSET_ADDR 0x7C
#define CONSYS_GEN_WB_BT_WAKE_ADDR_OFFSET_ADDR 0x80
#define CONSYS_GEN_WB_TOP_CK_ADDR_OFFSET_ADDR 0x84
#define CONSYS_GEN_WB_GPS_CK_ADDR_OFFSET_ADDR 0x88
#define CONSYS_GEN_WB_WF_B0_CMD_ADDR_OFFSET_ADDR 0x8c
#define CONSYS_GEN_WB_WF_B1_CMD_ADDR_OFFSET_ADDR 0x90
#define CONSYS_GEN_WB_GPS_RFBUF_ADR_OFFSET_ADDR 0x94
#define CONSYS_GEN_WB_GPS_L5_EN_ADDR_OFFSET_ADDR 0x98
#define CONSYS_GEN_WB_SLP_TOP_CK_0_OFFSET_ADDR 0x120
/****************************************************************************************************/
/* Base: CONN_CFG_ON_BASE (0x1800_1000) */
/****************************************************************************************************/
#define CONSYS_GEN_ADIE_CTL_OFFSET_ADDR 0x10
#define CONSYS_GEN_CONN_INFRA_CFG_PWRCTRL0_OFFSET_ADDR 0x200
#define CONSYS_GEN_CONN_INFRA_CFG_PWRCTRL1_OFFSET_ADDR 0x210
#define CONSYS_GEN_OSC_CTL_0_OFFSET_ADDR 0x300
#define CONSYS_GEN_OSC_CTL_1_OFFSET_ADDR 0x304
#define CONSYS_GEN_CONN_INFRA_CFG_RC_CTL_0_OFFSET_ADDR 0x340
#define CONSYS_GEN_CONN_INFRA_CFG_RC_CTL_1_OFFSET_ADDR 0x348
#define CONSYS_GEN_CONN_INFRA_CFG_RC_CTL_0_GPS_OFFSET_ADDR 0x350
#define CONSYS_GEN_CONN_INFRA_CFG_RC_CTL_1_GPS_OFFSET_ADDR 0x354
#define CONSYS_GEN_CONN_INFRA_CFG_RC_CTL_0_BT_OFFSET_ADDR 0x360
#define CONSYS_GEN_CONN_INFRA_CFG_RC_CTL_1_BT_OFFSET_ADDR 0x364
#define CONSYS_GEN_CONN_INFRA_CFG_RC_CTL_0_WF_OFFSET_ADDR 0x370
#define CONSYS_GEN_CONN_INFRA_CFG_RC_CTL_1_WF_OFFSET_ADDR 0x374
#define CONSYS_GEN_CONN_INFRA_CFG_RC_CTL_0_TOP_OFFSET_ADDR 0x380
#define CONSYS_GEN_CONN_INFRA_CFG_RC_CTL_1_TOP_OFFSET_ADDR 0x384
/****************************************************************************************************/
/* Base: SYS_SPI_TOP (MT6637) */
/****************************************************************************************************/
#define CONSYS_GEN_ADIE6637_ATOP_RG_TOP_PULL 0xC
#define CONSYS_GEN_ADIE6637_ATOP_CHIP_ID 0x2C
#define CONSYS_GEN_ADIE6637_ATOP_RG_TOP_THADC_BG 0x34
#define CONSYS_GEN_ADIE6637_ATOP_RG_TOP_THADC 0x38
#define CONSYS_GEN_ADIE6637_ATOP_WRI_CTR2 0x64
#define CONSYS_GEN_ADIE6637_ATOP_RG_ENCAL_WFBT_IF_SW_01 0x70
#define CONSYS_GEN_ADIE6637_ATOP_SMCTK11 0xBC
#define CONSYS_GEN_ADIE6637_ATOP_EFUSE_CTRL 0x108
#define CONSYS_GEN_ADIE6637_ATOP_EFUSE_RDATA0 0x130
#define CONSYS_GEN_ADIE6637_ATOP_EFUSE_RDATA1 0x134
#define CONSYS_GEN_ADIE6637_ATOP_EFUSE_RDATA2 0x138
#define CONSYS_GEN_ADIE6637_ATOP_EFUSE_RDATA3 0x13c
#define CONSYS_GEN_ADIE6637_ATOP_RG_FMCTL4 0x160
#define CONSYS_GEN_ADIE6637_ATOP_RG_BT0_BG_TIME 0x304
#define CONSYS_GEN_ADIE6637_ATOP_RG_BT0_ISO_TIME 0x308
#define CONSYS_GEN_ADIE6637_ATOP_RG_WF0_BG 0x344
#define CONSYS_GEN_ADIE6637_ATOP_RG_WF1_RFLDO_TIME 0x358
#define CONSYS_GEN_ADIE6637_ATOP_RG_WF1_BG 0x374
#define CONSYS_GEN_ADIE6637_ATOP_RG_WF2_POS_01 0x380
#define CONSYS_GEN_ADIE6637_ATOP_RG_WF2_TIME_COUNT_01 0x384
#define CONSYS_GEN_ADIE6637_ATOP_RG_WF2_POS_02 0x390
#define CONSYS_GEN_ADIE6637_ATOP_RG_WF2_TIME_COUNT_02 0x394
#define CONSYS_GEN_ADIE6637_ATOP_RG_BT0_XOBUF_TIME 0x430
#define CONSYS_GEN_ADIE6637_ATOP_RG_BT0_CKEN_TIME 0x438
#define CONSYS_GEN_ADIE6637_ATOP_RG_WF0_TOP_01 0x754
#define CONSYS_GEN_ADIE6637_ATOP_RG_WF1_TOP_01 0x758
#define CONSYS_GEN_ADIE6637_ATOP_RG_TOP_XO_02 0xB04
#define CONSYS_GEN_ADIE6637_ATOP_RG_TOP_XO_03 0xB08
#define CONSYS_GEN_ADIE6637_ATOP_RG_TOP_XO_07 0xB18
#define CONSYS_GEN_ADIE6637_ATOP_RG_WF1_RFDIG_OFF_TIME 0xDF8
#define CONSYS_GEN_ADIE6637_ATOP_RG_WAKEUPSLEEP_PON_OFF 0xFFC
/****************************************************************************************************/
/* Base: CONN_RF_SPI_MST_REG_BASE (0x1804_2000) */
/****************************************************************************************************/
#define CONSYS_GEN_FM_CTRL_OFFSET_ADDR 0xC
/****************************************************************************************************/
/* Base: CONN_THERM_CTL_BASE (0x1804_0000) */
/****************************************************************************************************/
#define CONSYS_GEN_THERM_AADDR_OFFSET_ADDR 0x18
/****************************************************************************************************/
/* Base: SYS_SPI_TOP */
/****************************************************************************************************/
#define CONSYS_GEN_ATOP_RG_ENCAL_WBTAC_IF_SW 0x70
#define CONSYS_GEN_ATOP_RG_TOP_XO_2 0xb04
#define CONSYS_GEN_ATOP_RG_TOP_XO_3 0xb08
#define CONSYS_GEN_ATOP_RG_TOP_XO_7 0xb18
/****************************************************************************************************/
/* Base: CONN_AFE_CTL_BASE (0x1804_1000) */
/****************************************************************************************************/
#define CONSYS_GEN_RG_DIG_EN_01_OFFSET_ADDR 0x0
#define CONSYS_GEN_RG_DIG_EN_02_OFFSET_ADDR 0x4
#define CONSYS_GEN_RG_DIG_EN_03_OFFSET_ADDR 0x8
#define CONSYS_GEN_RG_DIG_TOP_01_OFFSET_ADDR 0xC
#define CONSYS_GEN_RG_WBG_BT0_TX_03_OFFSET_ADDR 0x58
#define CONSYS_GEN_RG_WBG_WF0_TX_03_OFFSET_ADDR 0x78
#define CONSYS_GEN_RG_WBG_WF1_TX_03_OFFSET_ADDR 0x94
#define CONSYS_GEN_RG_PLL_STB_TIME_OFFSET_ADDR 0xF4
/****************************************************************************************************/
/* Base: CONN_BUS_CR_ON_BASE (0x1800_E000) */
/****************************************************************************************************/
#define CONSYS_GEN_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_OFFSET_ADDR 0x38
#define CONSYS_GEN_CONN_VON_BUS_DCM_CTL_1_OFFSET_ADDR 0x104
#define CONSYS_GEN_CONN_OFF_BUS_DCM_CTL_1_OFFSET_ADDR 0x110
/****************************************************************************************************/
/* Base: CONN_OFF_DEBUG_CTRL_AO_BASE (0x1804_D000) */
/****************************************************************************************************/
#define CONSYS_GEN_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_OFFSET_ADDR 0x0
/****************************************************************************************************/
/* Base: CONN_CLKGEN_TOP_BASE (0x1801_2000) */
/****************************************************************************************************/
#define CONSYS_GEN_CKGEN_BUS_BPLL_DIV_1_OFFSET_ADDR 0x0
#define CONSYS_GEN_CKGEN_BUS_BPLL_DIV_2_OFFSET_ADDR 0x4
#define CONSYS_GEN_CKGEN_BUS_WPLL_DIV_1_OFFSET_ADDR 0x8
#define CONSYS_GEN_CKGEN_BUS_WPLL_DIV_2_OFFSET_ADDR 0xC
#define CONSYS_GEN_CLKGEN_RFSPI_CK_CTRL_OFFSET_ADDR 0x38
#define CONSYS_GEN_CKGEN_BUS_OFFSET_ADDR 0x50
#define CONSYS_GEN_CKGEN_COEX_0_OFFSET_ADDR 0x60
#define CONSYS_GEN_CKGEN_COEX_1_OFFSET_ADDR 0x70
/****************************************************************************************************/
/* Base: CONN_HOST_CSR_TOP_BASE (0x1806_0000) */
/****************************************************************************************************/
#define CONSYS_GEN_CONN_INFRA_WAKEPU_TOP_OFFSET_ADDR 0x1a0
#define CONSYS_GEN_HOST_CONN_INFRA_SLP_CNT_CTL_OFFSET_ADDR 0x380
#endif /* _PLATFORM_MT6879_POS_GEN_H_ */

596
drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/mt6879.c Normal file
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@ -0,0 +1,596 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#define pr_fmt(fmt) KBUILD_MODNAME "@(%s:%d) " fmt, __func__, __LINE__
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/math64.h>
#include <linux/of.h>
#include <linux/types.h>
#include <mtk_clkbuf_ctl.h>
#include <linux/pm_runtime.h>
#include <connectivity_build_in_adapter.h>
#include "osal.h"
#include "conninfra.h"
#include "conninfra_conf.h"
#include "consys_hw.h"
#include "consys_reg_mng.h"
#include "consys_reg_util.h"
#include "mt6879.h"
#include "mt6879_pos.h"
#include "mt6879_consys_reg.h"
#include "mt6879_consys_reg_offset.h"
#include "mt6879_connsyslog.h"
#include "clock_mng.h"
#include "coredump_mng.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
#define PLATFORM_SOC_CHIP 0x6879
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
static int consys_clk_get_from_dts_mt6879(struct platform_device *pdev);
static int consys_clock_buffer_ctrl_mt6879(unsigned int enable);
static unsigned int consys_soc_chipid_get_mt6879(void);
static void consys_clock_fail_dump_mt6879(void);
static unsigned int consys_get_hw_ver_mt6879(void);
static int consys_thermal_query_mt6879(void);
/* Power state relative */
static int consys_enable_power_dump_mt6879(void);
static int consys_reset_power_state_mt6879(void);
static int consys_power_state_dump_mt6879(void);
static unsigned long long consys_soc_timestamp_get_mt6879(void);
static unsigned int consys_adie_detection_mt6879(void);
static void consys_set_mcu_control_mt6879(int type, bool onoff);
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
struct consys_hw_ops_struct g_consys_hw_ops_mt6879 = {
/* load from dts */
/* TODO: mtcmos should move to a independent module */
.consys_plt_clk_get_from_dts = consys_clk_get_from_dts_mt6879,
/* clock */
.consys_plt_clock_buffer_ctrl = consys_clock_buffer_ctrl_mt6879,
.consys_plt_co_clock_type = consys_co_clock_type_mt6879,
/* POS */
.consys_plt_conninfra_on_power_ctrl = consys_conninfra_on_power_ctrl_mt6879,
.consys_plt_set_if_pinmux = consys_set_if_pinmux_mt6879,
.consys_plt_polling_consys_chipid = consys_polling_chipid_mt6879,
.consys_plt_d_die_cfg = connsys_d_die_cfg_mt6879,
.consys_plt_spi_master_cfg = connsys_spi_master_cfg_mt6879,
.consys_plt_a_die_cfg = connsys_a_die_cfg_mt6879,
.consys_plt_afe_wbg_cal = connsys_afe_wbg_cal_mt6879,
.consys_plt_subsys_pll_initial = connsys_subsys_pll_initial_mt6879,
.consys_plt_low_power_setting = connsys_low_power_setting_mt6879,
.consys_plt_soc_chipid_get = consys_soc_chipid_get_mt6879,
.consys_plt_conninfra_wakeup = consys_conninfra_wakeup_mt6879,
.consys_plt_conninfra_sleep = consys_conninfra_sleep_mt6879,
.consys_plt_is_rc_mode_enable = consys_is_rc_mode_enable_mt6879,
/* debug */
.consys_plt_clock_fail_dump = consys_clock_fail_dump_mt6879,
.consys_plt_get_hw_ver = consys_get_hw_ver_mt6879,
.consys_plt_spi_read = consys_spi_read_mt6879,
.consys_plt_spi_write = consys_spi_write_mt6879,
.consys_plt_spi_update_bits = consys_spi_update_bits_mt6879,
.consys_plt_spi_clock_switch = consys_spi_clock_switch_mt6879,
.consys_plt_subsys_status_update = consys_subsys_status_update_mt6879,
.consys_plt_thermal_query = consys_thermal_query_mt6879,
.consys_plt_enable_power_dump = consys_enable_power_dump_mt6879,
.consys_plt_reset_power_state = consys_power_state_dump_mt6879,
.consys_plt_power_state = consys_power_state_dump_mt6879,
.consys_plt_soc_timestamp_get = consys_soc_timestamp_get_mt6879,
.consys_plt_adie_detection = consys_adie_detection_mt6879,
.consys_plt_set_mcu_control = consys_set_mcu_control_mt6879,
};
extern struct consys_hw_ops_struct g_consys_hw_ops_mt6879;
extern struct consys_reg_mng_ops g_dev_consys_reg_ops_mt6879;
extern struct consys_platform_emi_ops g_consys_platform_emi_ops_mt6879;
extern struct consys_platform_pmic_ops g_consys_platform_pmic_ops_mt6879;
extern struct consys_platform_coredump_ops g_consys_platform_coredump_ops_mt6879;
const struct conninfra_plat_data mt6879_plat_data = {
.chip_id = PLATFORM_SOC_CHIP,
.consys_hw_version = CONN_HW_VER,
.hw_ops = &g_consys_hw_ops_mt6879,
.reg_ops = &g_dev_consys_reg_ops_mt6879,
.platform_emi_ops = &g_consys_platform_emi_ops_mt6879,
.platform_pmic_ops = &g_consys_platform_pmic_ops_mt6879,
.platform_coredump_ops = &g_consys_platform_coredump_ops_mt6879,
.connsyslog_config = &g_connsyslog_config,
};
static struct consys_plat_thermal_data_mt6879 g_consys_plat_therm_data;
int consys_co_clock_type_mt6879(void)
{
const struct conninfra_conf *conf;
struct regmap *map = consys_clock_mng_get_regmap();
int value;
/* Default solution */
conf = conninfra_conf_get_cfg();
if (NULL == conf) {
pr_err("[%s] Get conf fail", __func__);
return -1;
}
pr_info("[%s] conf->tcxo_gpio=%d conn_hw_env.tcxo_support=%d",
__func__, conf->tcxo_gpio, conn_hw_env.tcxo_support);
/* TODO: for co-clock mode, there are two case: 26M and 52M. Need something to distinguish it. */
if (conf->tcxo_gpio != 0 || conn_hw_env.tcxo_support)
return CONNSYS_CLOCK_SCHEMATIC_26M_EXTCXO;
if (!map)
pr_err("%s, failed to get regmap.\n", __func__);
else {
regmap_read(map, DCXO_DIGCLK_ELR, &value);
if (value & 0x1)
return CONNSYS_CLOCK_SCHEMATIC_52M_COTMS;
}
return CONNSYS_CLOCK_SCHEMATIC_26M_COTMS;
}
int consys_clk_get_from_dts_mt6879(struct platform_device *pdev)
{
pm_runtime_enable(&pdev->dev);
dev_pm_syscore_device(&pdev->dev, true);
return 0;
}
int consys_platform_spm_conn_ctrl_mt6879(unsigned int enable)
{
int ret = 0;
struct platform_device *pdev = get_consys_device();
if (!pdev) {
pr_info("get_consys_device fail.\n");
return -1;
}
if (enable) {
ret = pm_runtime_get_sync(&(pdev->dev));
if (ret)
pr_info("pm_runtime_get_sync() fail(%d)\n", ret);
else
pr_info("pm_runtime_get_sync() CONSYS ok\n");
ret = device_init_wakeup(&(pdev->dev), true);
if (ret)
pr_info("device_init_wakeup(true) fail.\n");
else
pr_info("device_init_wakeup(true) CONSYS ok\n");
} else {
ret = device_init_wakeup(&(pdev->dev), false);
if (ret)
pr_info("device_init_wakeup(false) fail.\n");
else
pr_info("device_init_wakeup(false) CONSYS ok\n");
ret = pm_runtime_put_sync(&(pdev->dev));
if (ret)
pr_info("pm_runtime_put_sync() fail.\n");
else
pr_info("pm_runtime_put_sync() CONSYS ok\n");
}
return ret;
}
int consys_clock_buffer_ctrl_mt6879(unsigned int enable)
{
/* This function call didn't work now.
* clock buffer is HW controlled, not SW controlled.
* Keep this function call to update status.
*/
#if (!COMMON_KERNEL_CLK_SUPPORT)
if (enable)
KERNEL_clk_buf_ctrl(CLK_BUF_CONN, true); /*open XO_WCN*/
else
KERNEL_clk_buf_ctrl(CLK_BUF_CONN, false); /*close XO_WCN*/
#endif
return 0;
}
unsigned int consys_soc_chipid_get_mt6879(void)
{
return PLATFORM_SOC_CHIP;
}
void consys_clock_fail_dump_mt6879(void)
{
#if defined(KERNEL_clk_buf_show_status_info)
KERNEL_clk_buf_show_status_info();
#endif
}
int consys_enable_power_dump_mt6879(void)
{
/* Return success because sleep count dump is enable on POS */
return 0;
}
int consys_reset_power_state_mt6879(void)
{
/* Clear data and disable stop */
/* I. Clear
* i. Conn_infra: 0x1806_0384[15]
* ii. Wf: 0x1806_0384[9]
* iii. Bt: 0x1806_0384[10]
* iv. Gps: 0x1806_0384[8]
*/
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_SLP_STOP_HOST_CR_CONN_INFRA_SLEEP_CNT_CLR,
0x1);
udelay(150);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_SLP_STOP_HOST_CR_CONN_INFRA_SLEEP_CNT_CLR,
0x0);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_SLP_STOP_HOST_CR_WF_SLEEP_CNT_CLR,
0x1);
udelay(150);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_SLP_STOP_HOST_CR_WF_SLEEP_CNT_CLR,
0x0);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_SLP_STOP_HOST_CR_BT_SLEEP_CNT_CLR,
0x1);
udelay(150);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_SLP_STOP_HOST_CR_BT_SLEEP_CNT_CLR,
0x0);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_SLP_STOP_HOST_CR_GPS_SLEEP_CNT_CLR,
0x1);
udelay(150);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_SLP_STOP_HOST_CR_GPS_SLEEP_CNT_CLR,
0x0);
/* II. Stop
* i. Conn_infra: 0x1806_0384[7]
* ii. Wf: 0x1806_0384[1]
* iii. Bt: 0x1806_0384[2]
* iv. Gps: 0x1806_0384[0]
*/
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_SLP_STOP_HOST_CR_CONN_INFRA_SLEEP_CNT_STOP,
0x0);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_SLP_STOP_HOST_CR_WF_SLEEP_CNT_STOP,
0x0);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_SLP_STOP_HOST_CR_BT_SLEEP_CNT_STOP,
0x0);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_SLP_STOP_HOST_CR_GPS_SLEEP_CNT_STOP,
0x0);
return 0;
}
static inline void __sleep_count_trigger_read(void)
{
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_CTL_HOST_SLP_COUNTER_RD_TRIGGER, 0x1);
udelay(150);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_CTL_HOST_SLP_COUNTER_RD_TRIGGER, 0x0);
}
static void consys_power_state(void)
{
#if 0
unsigned int i, str_len;
unsigned int buf_len = 0;
unsigned int r;
const char* osc_str[] = {
"fm ", "gps ", "bgf ", "wf ", "ap2conn ", "conn_thm ", "conn_pta ", "conn_infra_bus "};
char buf[256] = {'\0'};
CONSYS_REG_WRITE_HW_ENTRY(CONN_HOST_CSR_TOP_CONN_INFRA_CFG_DBG_SEL_CONN_INFRA_CFG_DBG_SEL,
0x0);
r = CONSYS_REG_READ(CONN_HOST_CSR_TOP_DBG_DUMMY_2_ADDR);
for (i = 0; i < 8; i++) {
str_len = strlen(osc_str[i]);
if ((r & (0x1 << (18 + i))) > 0 && (buf_len + str_len < 256)) {
strncat(buf, osc_str[i], str_len);
buf_len += str_len;
}
}
pr_info("[%s] [0x%x] %s", __func__, r, buf);
#endif
}
int consys_power_state_dump_mt6879(void)
{
static u64 round = 0;
static u64 t_conninfra_sleep_cnt = 0, t_conninfra_sleep_time = 0;
static u64 t_wf_sleep_cnt = 0, t_wf_sleep_time = 0;
static u64 t_bt_sleep_cnt = 0, t_bt_sleep_time = 0;
static u64 t_gps_sleep_cnt = 0, t_gps_sleep_time = 0;
unsigned int conninfra_sleep_cnt, conninfra_sleep_time;
unsigned int wf_sleep_cnt, wf_sleep_time;
unsigned int bt_sleep_cnt, bt_sleep_time;
unsigned int gps_sleep_cnt, gps_sleep_time;
/* Sleep count */
/* 1. Setup read select: 0x1806_0380[3:1]
* 3'h0: conn_infra sleep counter
* 3'h1: wfsys sleep counter
* 3'h2: bgfsys sleep counter
* 3'h3: gpssys sleep counter
* 2. Dump time and count
* a. Timer: 0x1806_0388
* b. Count: 0x1806_038C
*/
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_CTL_HOST_SLP_COUNTER_SEL,
0x0);
__sleep_count_trigger_read();
conninfra_sleep_time = CONSYS_REG_READ(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_TIMER_ADDR);
conninfra_sleep_cnt = CONSYS_REG_READ(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_COUNTER_ADDR);
t_conninfra_sleep_time += conninfra_sleep_time;
t_conninfra_sleep_cnt += conninfra_sleep_cnt;
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_CTL_HOST_SLP_COUNTER_SEL,
0x1);
__sleep_count_trigger_read();
wf_sleep_time = CONSYS_REG_READ(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_TIMER_ADDR);
wf_sleep_cnt = CONSYS_REG_READ(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_COUNTER_ADDR);
t_wf_sleep_time += wf_sleep_time;
t_wf_sleep_cnt += wf_sleep_cnt;
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_CTL_HOST_SLP_COUNTER_SEL,
0x2);
__sleep_count_trigger_read();
bt_sleep_time = CONSYS_REG_READ(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_TIMER_ADDR);
bt_sleep_cnt = CONSYS_REG_READ(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_COUNTER_ADDR);
t_bt_sleep_time += bt_sleep_time;
t_bt_sleep_cnt += bt_sleep_cnt;
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_CTL_HOST_SLP_COUNTER_SEL,
0x3);
__sleep_count_trigger_read();
gps_sleep_time = CONSYS_REG_READ(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_TIMER_ADDR);
gps_sleep_cnt = CONSYS_REG_READ(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_COUNTER_ADDR);
t_gps_sleep_time += gps_sleep_time;
t_gps_sleep_cnt += gps_sleep_cnt;
pr_info("[consys_power_state][round:%llu]conninfra:%u,%u;wf:%u,%u;bt:%u,%u;gps:%u,%u;",
round,
conninfra_sleep_time, conninfra_sleep_cnt,
wf_sleep_time, wf_sleep_cnt,
bt_sleep_time, bt_sleep_cnt,
gps_sleep_time, gps_sleep_cnt);
pr_info("[consys_power_state][total]conninfra:%llu,%llu;wf:%llu,%llu;bt:%llu,%llu;gps:%llu,%llu;",
t_conninfra_sleep_time, t_conninfra_sleep_cnt,
t_wf_sleep_time, t_wf_sleep_cnt,
t_bt_sleep_time, t_bt_sleep_cnt,
t_gps_sleep_time, t_gps_sleep_cnt);
/* Power state */
consys_power_state();
round++;
/* reset after sleep time is accumulated. */
consys_reset_power_state_mt6879();
return 0;
}
unsigned int consys_get_hw_ver_mt6879(void)
{
return CONN_HW_VER;
}
void update_thermal_data_mt6879(struct consys_plat_thermal_data_mt6879* input)
{
memcpy(&g_consys_plat_therm_data, input, sizeof(struct consys_plat_thermal_data_mt6879));
}
static int calculate_thermal_temperature(int y)
{
struct consys_plat_thermal_data_mt6879 *data = &g_consys_plat_therm_data;
int t;
int const_offset = 30;
/* temperature = (y-b)*slope + (offset) */
/* Postpone division to avoid getting wrong slope becasue of integer division */
t = (y - (data->thermal_b == 0 ? 0x38 : data->thermal_b)) *
(data->slop_molecule + 1866) / 1000 + const_offset;
pr_info("y=[%d] b=[%d] constOffset=[%d] [%d] [%d] => t=[%d]\n",
y, data->thermal_b, const_offset, data->slop_molecule, data->offset,
t);
return t;
}
int consys_thermal_query_mt6879(void)
{
#define THERMAL_DUMP_NUM 11
#define LOG_TMP_BUF_SZ 256
#define TEMP_SIZE 13
#define CONN_GPT2_CTRL_BASE 0x18007000
#define CONN_GPT2_CTRL_AP_EN 0x38
void __iomem *addr = NULL;
int cal_val, res = 0;
/* Base: 0x1800_2000, CONN_TOP_THERM_CTL */
const unsigned int thermal_dump_crs[THERMAL_DUMP_NUM] = {
0x00, 0x04, 0x08, 0x0c,
0x10, 0x14, 0x18, 0x1c,
0x20, 0x24, 0x28,
};
char tmp[TEMP_SIZE] = {'\0'};
char tmp_buf[LOG_TMP_BUF_SZ] = {'\0'};
unsigned int i;
unsigned int efuse0, efuse1, efuse2, efuse3;
addr = ioremap(CONN_GPT2_CTRL_BASE, 0x100);
if (addr == NULL) {
pr_err("GPT2_CTRL_BASE remap fail");
return -1;
}
connsys_adie_top_ck_en_ctl_mt6879(true);
/* Hold Semaphore, TODO: may not need this, because
thermal cr seperate for different */
if (consys_sema_acquire_timeout_mt6879(CONN_SEMA_THERMAL_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL) {
pr_err("[THERM QRY] Require semaphore fail\n");
connsys_adie_top_ck_en_ctl_mt6879(false);
iounmap(addr);
return -1;
}
/* therm cal en */
CONSYS_SET_BIT(CONN_THERM_CTL_THERMEN3_ADDR, (0x1 << 19));
/* GPT2 En */
CONSYS_REG_WRITE(addr + CONN_GPT2_CTRL_AP_EN, 0x1);
/* thermal trigger */
CONSYS_SET_BIT(CONN_THERM_CTL_THERMEN3_ADDR, (0x1 << 18));
udelay(500);
/* get thermal value */
cal_val = CONSYS_REG_READ(CONN_THERM_CTL_THERMEN3_ADDR);
cal_val = (cal_val >> 8) & 0x7f;
/* thermal debug dump */
efuse0 = CONSYS_REG_READ(CONN_INFRA_SYSRAM_SW_CR_A_DIE_EFUSE_DATA_0);
efuse1 = CONSYS_REG_READ(CONN_INFRA_SYSRAM_SW_CR_A_DIE_EFUSE_DATA_1);
efuse2 = CONSYS_REG_READ(CONN_INFRA_SYSRAM_SW_CR_A_DIE_EFUSE_DATA_2);
efuse3 = CONSYS_REG_READ(CONN_INFRA_SYSRAM_SW_CR_A_DIE_EFUSE_DATA_3);
for (i = 0; i < THERMAL_DUMP_NUM; i++) {
if (snprintf(
tmp, TEMP_SIZE, "[0x%08x]",
CONSYS_REG_READ(CONN_REG_CONN_THERM_CTL_ADDR + thermal_dump_crs[i])) >= 0)
strncat(tmp_buf, tmp, strlen(tmp));
}
pr_info("[%s] efuse:[0x%08x][0x%08x][0x%08x][0x%08x] thermal dump: %s",
__func__, efuse0, efuse1, efuse2, efuse3, tmp_buf);
res = calculate_thermal_temperature(cal_val);
/* GPT2 disable */
CONSYS_REG_WRITE(addr + CONN_GPT2_CTRL_AP_EN, 0);
/* disable */
CONSYS_CLR_BIT(CONN_THERM_CTL_THERMEN3_ADDR, (0x1 << 19));
consys_sema_release_mt6879(CONN_SEMA_THERMAL_INDEX);
connsys_adie_top_ck_en_ctl_mt6879(false);
iounmap(addr);
return res;
}
static unsigned long long consys_soc_timestamp_get_mt6879(void)
{
#define TICK_PER_MS (13000)
void __iomem *addr = NULL;
u32 tick_h = 0, tick_l = 0, tmp_h = 0;
u64 timestamp = 0;
/* 0x1c01_1000 sys_timer@13M (VLPSYS)
* - 0x0008 CNTCV_L 32 System counter count value low
* - 0x000C CNTCV_H 32 System counter count value high
*/
addr = ioremap(0x1c011000, 0x10);
if (addr) {
do {
tick_h = CONSYS_REG_READ(addr + 0x000c);
tick_l = CONSYS_REG_READ(addr + 0x0008);
tmp_h = CONSYS_REG_READ(addr + 0x000c);
} while (tick_h != tmp_h);
iounmap(addr);
} else {
pr_info("[%s] remap fail", __func__);
return 0;
}
timestamp = ((((u64)tick_h << 32) & 0xFFFFFFFF00000000) | ((u64)tick_l & 0x00000000FFFFFFFF));
do_div(timestamp, TICK_PER_MS);
return timestamp;
}
static unsigned int consys_adie_detection_mt6879(void)
{
return ADIE_6637;
}
unsigned int consys_get_adie_chipid_mt6879(void)
{
return ADIE_6637;
}
static void consys_set_mcu_control_mt6879(int type, bool onoff)
{
pr_info("[%s] Set mcu control type=[%d] onoff=[%d]\n", __func__, type, onoff);
if (onoff) // Turn on
CONSYS_SET_BIT(CONN_INFRA_SYSRAM_SW_CR_MCU_LOG_CONTROL, (0x1 << type));
else // Turn off
CONSYS_CLR_BIT(CONN_INFRA_SYSRAM_SW_CR_MCU_LOG_CONTROL, (0x1 << type));
}

364
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#include <linux/memblock.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "consys_reg_mng.h"
#include "consys_reg_util.h"
#include "mt6879_consys_reg.h"
#include "mt6879_consys_reg_offset.h"
#include "mt6879_pos.h"
#include "mt6879_pos_gen.h"
#include "mt6879_debug_gen.h"
#include "osal.h"
#include "mt6879_pmic.h"
#define LOG_TMP_BUF_SZ 256
static int consys_reg_init(struct platform_device *pdev);
static int consys_reg_deinit(void);
#ifndef CONFIG_FPGA_EARLY_PORTING
static int consys_check_reg_readable(void);
static int consys_check_reg_readable_for_coredump(void);
static int __consys_check_reg_readable(int check_type);
static int consys_is_consys_reg(unsigned int addr);
static int consys_is_bus_hang(void);
#endif
struct consys_base_addr conn_reg_mt6879;
struct consys_reg_mng_ops g_dev_consys_reg_ops_mt6879 = {
.consys_reg_mng_init = consys_reg_init,
.consys_reg_mng_deinit = consys_reg_deinit,
#ifndef CONFIG_FPGA_EARLY_PORTING
.consys_reg_mng_check_reable = consys_check_reg_readable,
.consys_reg_mng_check_reable_for_coredump = consys_check_reg_readable_for_coredump,
.consys_reg_mng_is_bus_hang = consys_is_bus_hang,
.consys_reg_mng_is_consys_reg = consys_is_consys_reg,
#endif
};
static struct conn_debug_info_mt6879 *debug_info;
static const char* consys_base_addr_index_to_str[CONSYS_BASE_ADDR_MAX] = {
"infracfg_ao",
"GPIO",
"IOCFG_RT",
"conn_infra_rgu_on",
"conn_infra_cfg_on",
"conn_wt_slp_ctl_reg",
"conn_infra_bus_cr_on",
"conn_infra_cfg",
"conn_infra_clkgen_top",
"conn_von_bus_bcrm",
"conn_dbg_ctl",
"conn_infra_on_bus_bcrm",
"conn_therm_ctl",
"conn_afe_ctl",
"conn_rf_spi_mst_reg",
"conn_infra_bus_cr",
"conn_infra_off_debug_ctrl_ao",
"conn_infra_off_bus_bcrm",
"conn_infra_sysram_sw_cr",
"conn_host_csr_top",
"conn_semaphore",
"spm",
"top_rgu",
};
int consys_is_consys_reg(unsigned int addr)
{
if (addr >= 0x18000000 && addr < 0x19000000)
return 1;
return 0;
}
#define CONSYS_DUMP_BUF_SIZE 512
static void consys_print_log(const char *title, struct conn_debug_info_mt6879 *info)
{
char buf[CONSYS_DUMP_BUF_SIZE];
char temp[13];
int i;
temp[0] = '\0';
if (snprintf(buf, CONSYS_DUMP_BUF_SIZE, "%s", title) < 0) {
pr_notice("%s snprintf failed\n", __func__);
return;
}
for (i = 0; i < info->length; i++) {
if (snprintf(temp, sizeof(temp), "[0x%08x]", info->rd_data[i]) < 0) {
pr_notice("%s snprintf failed\n", __func__);
return;
}
strncat(buf, temp, strlen(temp) + 1);
}
pr_info("%s\n", buf);
}
static void consys_print_power_debug(int level)
{
pr_info("%s\n", __func__);
if (level >= 0) {
consys_print_power_debug_dbg_level_0_mt6879_debug_gen(level, debug_info);
consys_print_log("[CONN_POWER_A]", debug_info);
}
if (level >= 1) {
consys_print_power_debug_dbg_level_1_mt6879_debug_gen(level, debug_info);
consys_print_log("[CONN_POWER_B]", debug_info);
}
if (level >= 2) {
consys_print_power_debug_dbg_level_2_mt6879_debug_gen(level, debug_info);
consys_print_log("[CONN_POWER_C]", debug_info);
}
}
static void consys_print_bus_debug(int level)
{
pr_info("%s\n", __func__);
consys_print_bus_slpprot_debug_dbg_level_0_mt6879_debug_gen(level, debug_info);
consys_print_log("[slpprot_a]", debug_info);
if (level >= 1) {
consys_print_bus_debug_dbg_level_1_mt6879_debug_gen(level, debug_info);
consys_print_log("[CONN_BUS_B]", debug_info);
}
if (level >= 2) {
consys_print_bus_debug_dbg_level_2_mt6879_debug_gen(level, debug_info);
consys_print_log("[CONN_BUS_C]", debug_info);
consys_print_bus_slpprot_debug_dbg_level_2_mt6879_debug_gen(level, debug_info);
consys_print_log("[slpprot_c]", debug_info);
}
}
int consys_print_debug_mt6879(int level)
{
if (level < 0 || level > 2) {
pr_info("%s level[%d] unexpected value.");
return 0;
}
if (debug_info == NULL) {
pr_notice("%s debug_info is NULL\n", __func__);
return -1;
}
consys_print_power_debug(level);
consys_print_bus_debug(level);
consys_pmic_debug_log_mt6879();
return 0;
}
static inline unsigned int __consys_bus_hang_clock_detect(void)
{
unsigned int r = 0;
unsigned int count = 0;
/* Check conn_infra off bus clock */
/* - write 0x1 to 0x1802_3000[0], reset clock detect */
/* - 0x1802_3000[1]  conn_infra off bus clock (should be 1'b1 if clock exist) */
/* - 0x1802_3000[2]  osc clock (should be 1'b1 if clock exist) */
while (count < 4) {
CONSYS_SET_BIT(CONN_DBG_CTL_CLOCK_DETECT_ADDR, (0x1 << 0));
udelay(20);
r = CONSYS_REG_READ_BIT(CONN_DBG_CTL_CLOCK_DETECT_ADDR, ((0x1 << 2) | (0x1 << 1)));
if (r == 0x6)
break;
udelay(1000);
count ++;
}
if (r != 0x6)
pr_info("%s fail:0x1802_3000 = %x\n", __func__, r);
return r;
}
static int consys_is_bus_hang(void)
{
if (__consys_check_reg_readable(1) > 0)
return 0;
return 1;
}
static int consys_check_conninfra_on_domain(void)
{
unsigned int r1, r2;
/* AP2CONN_INFRA ON */
/* 1. Check ap2conn gals sleep protect status */
/*     - 0x1000_1C9C[0] / 0x1000_1C5C[12]   (rx/tx) */
r1 = CONSYS_REG_READ_BIT(INFRACFG_AO_REG_BASE +
CONSYS_GEN_MCU_CONNSYS_PROTECT_RDY_STA_0_OFFSET_ADDR, (0x1 << 0));
r2 = CONSYS_REG_READ_BIT(INFRACFG_AO_REG_BASE +
CONSYS_GEN_INFRASYS_PROTECT_RDY_STA_1_OFFSET_ADDR, (0x1 << 12));
if (r1 || r2) {
pr_info("%s 0x1000_1C9C[0] = %x, 0x1000_1C5C[12] = %x\n", __func__, r1, r2);
return 0;
}
return 1;
}
static int consys_check_conninfra_off_domain(void)
{
unsigned int r;
r = __consys_bus_hang_clock_detect();
if (r != 0x6)
return 0;
r = CONSYS_REG_READ(CONN_CFG_IP_VERSION_ADDR);
if (r != CONN_HW_VER)
return 0;
return 1;
}
static int __consys_check_reg_readable(int check_type)
{
// check_type includes:
// 0: error
// 1: print if no err
// 2: coredump (can ignore bus timeout irq status)
unsigned int r;
int wakeup_conninfra = 0;
int ret = 1;
if (consys_check_conninfra_on_domain() == 0) {
consys_print_debug_mt6879(0);
return 0;
}
if (consys_check_conninfra_off_domain() == 0) {
pr_info("%s: check conninfra off failed\n", __func__);
consys_print_debug_mt6879(1);
if (check_type == 0 || check_type == 2)
return 0;
/* wake up conninfra to read off register */
wakeup_conninfra = 1;
consys_hw_force_conninfra_wakeup();
ret = 0;
}
/* Check conn_infra off domain bus hang irq status */
/* - 0x1802_3400[2:0], should be 3'b000, or means conn_infra off bus might hang */
r = CONSYS_REG_READ_BIT(CONN_DBG_CTL_CONN_INFRA_BUS_TIMEOUT_IRQ_ADDR,
(0x1 << 0) | (0x1 << 1) | (0x1 << 2));
if (r != 0) {
pr_info("%s bus timeout 0x1802_3400[2:0] = 0x%x\n", __func__, r);
consys_print_debug_mt6879(2);
if (check_type == 2)
return ret;
ret = 0;
} else if (check_type == 1)
consys_print_debug_mt6879(2);
if (wakeup_conninfra)
consys_hw_force_conninfra_sleep();
return ret;
}
static void consys_debug_init_mt6879(void)
{
debug_info = (struct conn_debug_info_mt6879 *)osal_malloc(sizeof(struct conn_debug_info_mt6879));
if (debug_info == NULL) {
pr_notice("%s malloc failed\n", __func__);
return;
}
consys_debug_init_mt6879_debug_gen();
}
static void consys_debug_deinit_mt6879(void)
{
if (debug_info == NULL) {
pr_notice("%s debug_info is NULL\n", __func__);
return;
}
osal_free(debug_info);
debug_info = NULL;
consys_debug_deinit_mt6879_debug_gen();
}
static int consys_check_reg_readable(void)
{
return __consys_check_reg_readable(0);
}
static int consys_check_reg_readable_for_coredump(void)
{
return __consys_check_reg_readable(2);
}
int consys_reg_init(struct platform_device *pdev)
{
int ret = -1;
struct device_node *node = NULL;
struct consys_reg_base_addr *base_addr = NULL;
struct resource res;
int flag, i = 0;
node = pdev->dev.of_node;
pr_info("[%s] node=[%p]\n", __func__, node);
if (node) {
for (i = 0; i < CONSYS_BASE_ADDR_MAX; i++) {
base_addr = &conn_reg_mt6879.reg_base_addr[i];
ret = of_address_to_resource(node, i, &res);
if (ret) {
pr_err("Get Reg Index(%d-%s) failed",
i, consys_base_addr_index_to_str[i]);
continue;
}
base_addr->phy_addr = res.start;
base_addr->vir_addr =
(unsigned long) of_iomap(node, i);
of_get_address(node, i, &(base_addr->size), &flag);
pr_info("Get Index(%d-%s) phy(0x%zx) baseAddr=(0x%zx) size=(0x%zx)",
i, consys_base_addr_index_to_str[i], base_addr->phy_addr,
base_addr->vir_addr, base_addr->size);
}
} else {
pr_err("[%s] can't find CONSYS compatible node\n", __func__);
return ret;
}
consys_debug_init_mt6879();
return 0;
}
static int consys_reg_deinit(void)
{
int i = 0;
for (i = 0; i < CONSYS_BASE_ADDR_MAX; i++) {
if (conn_reg_mt6879.reg_base_addr[i].vir_addr) {
pr_info("[%d] Unmap %s (0x%zx)",
i, consys_base_addr_index_to_str[i],
conn_reg_mt6879.reg_base_addr[i].vir_addr);
iounmap((void __iomem*)conn_reg_mt6879.reg_base_addr[i].vir_addr);
conn_reg_mt6879.reg_base_addr[i].vir_addr = 0;
}
}
consys_debug_deinit_mt6879();
return 0;
}

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drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/mt6879_coredump.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#include <linux/printk.h>
#include <linux/memblock.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "consys_reg_util.h"
#include "connsys_debug_utility.h"
#include "connsys_coredump_hw_config.h"
#include "coredump_mng.h"
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
static char* wifi_task_str[] = {
"Task_WIFI",
"Task_TST_WFSYS",
"Task_Idle_WFSYS",
};
static char* bt_task_str[] = {
"Task_WMT",
"Task_BT",
"Task_TST_BTSYS",
"Task_BT2",
"Task_Idle_BTSYS",
};
static struct coredump_hw_config g_coredump_config[CONN_DEBUG_TYPE_END] = {
/* Wi-Fi config */
{
.name = "WFSYS",
#ifdef CONFIG_FPGA_EARLY_PORTING
.start_offset = 0x8000,
#else
.start_offset = 0x0495400,
#endif
.size = 0x18000,
.seg1_cr = 0x1840012c,
.seg1_value_end = 0x187fffff,
.seg1_start_addr = 0x18400120,
.seg1_phy_addr = 0x18500000,
.task_table_size = sizeof(wifi_task_str)/sizeof(char*),
.task_map_table = wifi_task_str,
.exception_tag_name = "combo_wifi",
},
/* BT config */
{
.name = "BTSYS",
.start_offset = 0x43C00,
.size = 0x18000,
.seg1_cr = 0x18816024,
.seg1_value_end = 0x18bfffff,
.seg1_start_addr = 0x18816014,
.seg1_phy_addr = 0x18900000,
.task_table_size = sizeof(bt_task_str)/sizeof(char*),
.task_map_table = bt_task_str,
.exception_tag_name = "combo_bt",
},
};
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
static struct coredump_hw_config* consys_plt_coredump_get_platform_config(int conn_type);
static unsigned int consys_plt_coredump_get_platform_chipid(void);
static char* consys_plt_coredump_get_task_string(int conn_type, unsigned int task_id);
static char* consys_plt_coredump_get_sys_name(int conn_type);
static bool consys_plt_coredump_is_host_view_cr(unsigned int addr, unsigned int* host_view);
static bool consys_plt_coredump_is_host_csr_readable(void);
static enum cr_category consys_plt_coredump_get_cr_category(unsigned int addr);
struct consys_platform_coredump_ops g_consys_platform_coredump_ops_mt6879 = {
.consys_coredump_get_platform_config = consys_plt_coredump_get_platform_config,
.consys_coredump_get_platform_chipid = consys_plt_coredump_get_platform_chipid,
.consys_coredump_get_task_string = consys_plt_coredump_get_task_string,
.consys_coredump_get_sys_name = consys_plt_coredump_get_sys_name,
.consys_coredump_is_host_view_cr = consys_plt_coredump_is_host_view_cr,
.consys_coredump_is_host_csr_readable = consys_plt_coredump_is_host_csr_readable,
.consys_coredump_get_cr_category = consys_plt_coredump_get_cr_category,
};
static struct coredump_hw_config* consys_plt_coredump_get_platform_config(int conn_type)
{
if (conn_type < 0 || conn_type >= CONN_DEBUG_TYPE_END) {
pr_err("Incorrect type: %d\n", conn_type);
return NULL;
}
return &g_coredump_config[conn_type];
}
static unsigned int consys_plt_coredump_get_platform_chipid(void)
{
return 0x6879;
}
static char* consys_plt_coredump_get_task_string(int conn_type, unsigned int task_id)
{
if (conn_type < 0 || conn_type >= CONN_DEBUG_TYPE_END) {
pr_err("Incorrect type: %d\n", conn_type);
return NULL;
}
if (task_id > g_coredump_config[conn_type].task_table_size) {
pr_err("[%s] Incorrect task: %d\n",
g_coredump_config[conn_type].name, task_id);
return NULL;
}
return g_coredump_config[conn_type].task_map_table[task_id];
}
static char* consys_plt_coredump_get_sys_name(int conn_type)
{
if (conn_type < 0 || conn_type >= CONN_DEBUG_TYPE_END) {
pr_err("Incorrect type: %d\n", conn_type);
return NULL;
}
return g_coredump_config[conn_type].name;
}
static bool consys_plt_coredump_is_host_view_cr(unsigned int addr, unsigned int* host_view)
{
if (addr >= 0x7C000000 && addr <= 0x7Cffffff) {
if (host_view) {
*host_view = ((addr - 0x7c000000) + 0x18000000);
}
return true;
} else if (addr >= 0x18000000 && addr <= 0x18ffffff) {
if (host_view) {
*host_view = addr;
}
return true;
}
return false;
}
static bool consys_plt_coredump_is_host_csr_readable(void)
{
void __iomem *vir_addr = NULL;
bool ret = false;
unsigned int r;
/* AP2CONN_INFRA ON
* 1. Check ap2conn gals sleep protect status
* - 0x1000_1C5C [12] tx
* - 0x1000_1C9C [0] rx
* (sleep protect enable ready)
* both of them should be 1'b0 (CR at ap side)
*/
vir_addr = ioremap(0x10001c5c, 0x44);
if (vir_addr) {
r = CONSYS_REG_READ_BIT(vir_addr, 0x1 << 12) |
CONSYS_REG_READ_BIT(vir_addr + 0x40, 0x1 << 0);
if (r == 0) {
ret = true;
}
iounmap(vir_addr);
} else
pr_info("[%s] remap 0x10001c5c and 0x1000_1c9c fail", __func__);
return ret;
}
static enum cr_category consys_plt_coredump_get_cr_category(unsigned int addr)
{
if (addr >= 0x7c000000 && addr <= 0x7c3fffff) {
if (addr >= 0x7c060000 && addr <= 0x7c06ffff) {
return CONN_HOST_CSR;
}
return CONN_INFRA_CR;
}
return SUBSYS_CR;
}

1285
drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/mt6879_debug_gen.c Normal file
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103
drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/mt6879_emi.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#define pr_fmt(fmt) KBUILD_MODNAME "@(%s:%d) " fmt, __func__, __LINE__
#include "emi_mng.h"
#include "mt6879.h"
#include "mt6879_pos.h"
/* For EMI MPU */
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0))
#include <soc/mediatek/emi.h>
#else
#include <memory/mediatek/emi.h>
#endif
/* For MCIF */
#include <mtk_ccci_common.h>
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
#define REGION_CONN 27
#define DOMAIN_AP 0
#define DOMAIN_CONN 2
#define DOMAIN_SCP 3
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
static int consys_emi_mpu_set_region_protection_mt6879(void);
static void consys_emi_get_md_shared_emi_mt6879(phys_addr_t* base, unsigned int* size);
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
extern unsigned long long gConEmiSize;
extern phys_addr_t gConEmiPhyBase;
struct consys_platform_emi_ops g_consys_platform_emi_ops_mt6879 = {
.consys_ic_emi_mpu_set_region_protection = consys_emi_mpu_set_region_protection_mt6879,
.consys_ic_emi_set_remapping_reg = consys_emi_set_remapping_reg_mt6879,
.consys_ic_emi_get_md_shared_emi = consys_emi_get_md_shared_emi_mt6879,
};
static int consys_emi_mpu_set_region_protection_mt6879(void)
{
pr_info("[%s] is not supported. MPU is set in lk\n", __func__);
return 0;
}
void consys_emi_get_md_shared_emi_mt6879(phys_addr_t* base, unsigned int* size)
{
phys_addr_t mdPhy = 0;
int ret = 0;
#ifndef CONFIG_FPGA_EARLY_PORTING
#if IS_ENABLED(CONFIG_MTK_ECCCI_DRIVER)
mdPhy = get_smem_phy_start_addr(MD_SYS1, SMEM_USER_RAW_MD_CONSYS, &ret);
#else
pr_info("[%s] ECCCI Driver is not supported.\n", __func__);
#endif
#else
pr_info("[%s] not implement on FPGA\n", __func__);
#endif
if (ret && mdPhy) {
pr_info("MCIF base=0x%llx size=0x%x", mdPhy, ret);
if (base)
*base = mdPhy;
if (size)
*size = ret;
} else {
pr_info("MCIF is not supported");
if (base)
*base = 0;
if (size)
*size = 0;
}
}

643
drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/mt6879_pmic.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#define pr_fmt(fmt) KBUILD_MODNAME "@(%s:%d) " fmt, __func__, __LINE__
#include <connectivity_build_in_adapter.h>
#include <asm/atomic.h>
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/timer.h>
#include "osal.h"
#include "consys_hw.h"
#include "consys_reg_util.h"
#include "pmic_mng.h"
#include <linux/regmap.h>
#include "mt6879_pmic.h"
#include "mt6879_consys_reg_offset.h"
#include "mt6879_pos.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
static struct regulator *reg_VCN13;
static struct regulator *reg_VRFIO18; /* MT6363 workaround VCN15 -> VRFIO18 */
static struct regulator *reg_VCN33_1;
static struct regulator *reg_VCN33_2;
static struct regulator *reg_VANT18;
static struct regulator *reg_buckboost;
static struct notifier_block vrfio18_nb;
static struct notifier_block vcn13_nb;
static struct conninfra_dev_cb* g_dev_cb;
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
static int consys_plt_pmic_get_from_dts_mt6879(struct platform_device*, struct conninfra_dev_cb*);
static int consys_plt_pmic_common_power_ctrl_mt6879(unsigned int);
static int consys_plt_pmic_common_power_low_power_mode_mt6879(unsigned int);
static int consys_plt_pmic_wifi_power_ctrl_mt6879(unsigned int);
static int consys_plt_pmic_bt_power_ctrl_mt6879(unsigned int);
static int consys_plt_pmic_gps_power_ctrl_mt6879(unsigned int);
static int consys_plt_pmic_fm_power_ctrl_mt6879(unsigned int);
static int consys_pmic_vcn33_1_power_ctl_mt6879_lg(bool);
static int consys_pmic_vcn33_1_power_ctl_mt6879_rc(bool);
static int consys_pmic_vcn33_2_power_ctl_mt6879_lg(bool);
static int consys_pmic_vcn33_2_power_ctl_mt6879_rc(bool);
static int consys_pmic_vant18_power_ctl_mt6879(bool);
#if 0
static int consys_plt_pmic_raise_voltage_mt6879(unsigned int, bool, bool);
static void consys_plt_pmic_raise_voltage_timer_handler_mt6879(timer_handler_arg);
#endif
static int consys_vcn13_oc_notify(struct notifier_block*, unsigned long, void*);
static int consys_vrfio18_oc_notify(struct notifier_block*, unsigned long, void*);
static int consys_plt_pmic_event_notifier_mt6879(unsigned int, unsigned int);
static void consys_pmic_regmap_set_value(struct regmap *rmap, unsigned int address,
unsigned int mask, unsigned int value);
const struct consys_platform_pmic_ops g_consys_platform_pmic_ops_mt6879 = {
.consys_pmic_get_from_dts = consys_plt_pmic_get_from_dts_mt6879,
.consys_pmic_common_power_ctrl = consys_plt_pmic_common_power_ctrl_mt6879,
.consys_pmic_common_power_low_power_mode = consys_plt_pmic_common_power_low_power_mode_mt6879,
.consys_pmic_wifi_power_ctrl = consys_plt_pmic_wifi_power_ctrl_mt6879,
.consys_pmic_bt_power_ctrl = consys_plt_pmic_bt_power_ctrl_mt6879,
.consys_pmic_gps_power_ctrl = consys_plt_pmic_gps_power_ctrl_mt6879,
.consys_pmic_fm_power_ctrl = consys_plt_pmic_fm_power_ctrl_mt6879,
#if 0
.consys_pmic_raise_voltage = consys_plt_pmic_raise_voltage_mt6879,
#endif
.consys_pmic_event_notifier = consys_plt_pmic_event_notifier_mt6879,
};
int consys_plt_pmic_get_from_dts_mt6879(struct platform_device *pdev, struct conninfra_dev_cb* dev_cb)
{
int ret;
g_dev_cb = dev_cb;
reg_VCN13 = devm_regulator_get_optional(&pdev->dev, "mt6363_vcn13");
if (IS_ERR(reg_VCN13)) {
pr_err("Regulator_get VCN_13 fail\n");
reg_VCN13 = NULL;
}
else {
vcn13_nb.notifier_call = consys_vcn13_oc_notify;
ret = devm_regulator_register_notifier(reg_VCN13, &vcn13_nb);
if (ret)
pr_info("VCN13 regulator notifier request failed\n");
}
reg_VRFIO18 = devm_regulator_get(&pdev->dev, "mt6363_vrfio18");
if (IS_ERR(reg_VRFIO18)) {
pr_err("Regulator_get VRFIO18 fail\n");
reg_VRFIO18 = NULL;
} else {
vrfio18_nb.notifier_call = consys_vrfio18_oc_notify;
ret = devm_regulator_register_notifier(reg_VRFIO18, &vrfio18_nb);
if (ret)
pr_info("VRFIO18 regulator notifier request failed\n");
}
reg_VCN33_1 = devm_regulator_get(&pdev->dev, "mt6368_vcn33_1");
if (IS_ERR(reg_VCN33_1)) {
pr_err("Regulator_get VCN33_1 fail\n");
reg_VCN33_1 = NULL;
}
reg_VCN33_2 = devm_regulator_get(&pdev->dev, "mt6368_vcn33_2");
if (IS_ERR(reg_VCN33_2)) {
pr_err("Regulator_get VCN33_2 fail\n");
reg_VCN33_2 = NULL;
}
reg_VANT18 = devm_regulator_get(&pdev->dev, "mt6368_vant18");
if (IS_ERR(reg_VANT18)) {
pr_err("Regulator_get VANT18 fail\n");
reg_VANT18 = NULL;
}
reg_buckboost = devm_regulator_get_optional(&pdev->dev, "rt6160-buckboost");
if (IS_ERR(reg_buckboost)) {
pr_info("Regulator_get buckboost fail\n");
reg_buckboost = NULL;
}
return 0;
}
int consys_plt_pmic_common_power_ctrl_mt6879(unsigned int enable)
{
#ifdef CONFIG_FPGA_EARLY_PORTING
pr_info("[%s] not support on FPGA", __func__);
#else
int ret;
int sleep_mode;
if (enable) {
/* set PMIC VRFIO18 LDO 1.7V */
regulator_set_voltage(reg_VRFIO18, 1700000, 1700000);
/* set PMIC VRFIO18 LDO SW_OP_EN = 1, SW_EN = 1, SW_LP = 0 (SW ON) */
regulator_set_mode(reg_VRFIO18, REGULATOR_MODE_NORMAL); /* SW_LP = 0 */
ret = regulator_enable(reg_VRFIO18); /* SW_EN = 1 */
if (ret)
pr_err("Enable VRFIO18 fail. ret=%d\n", ret);
/* request VS2 to 1.45V by VS2 VOTER (use bit 4) */
consys_pmic_regmap_set_value(g_regmap_mt6363,
MT6363_BUCK_VS2_VOTER_CON0_SET_ADDR, 1 << 4, 1 << 4);
/* set PMIC VCN13 LDO 1.35V @Normal mode; 0.95V @LPM */
/* no need for LPM because 0.95V is default setting. */
regulator_set_voltage(reg_VCN13, 1350000, 1350000);
regulator_set_mode(reg_VCN13, REGULATOR_MODE_NORMAL); /* SW_LP = 0 */
ret = regulator_enable(reg_VCN13); /* SW_EN = 1 */
if (ret)
pr_err("Enable VCN13 fail. ret=%d\n", ret);
} else {
/* vant18 is enabled in consys_plt_pmic_common_power_low_power_mode_mt6879 */
/* Please refer to POS for more information */
consys_pmic_vant18_power_ctl_mt6879(0);
/* Add 1ms sleep to delay make sure that VCN13/18 would be turned off later then VCN33. */
msleep(1);
/* set PMIC VCN13 LDO SW_EN = 0, SW_LP =0 (sw disable) */
regulator_set_mode(reg_VCN13, REGULATOR_MODE_NORMAL);
regulator_disable(reg_VCN13);
/* clear bit 4 of VS2 VOTER then VS2 can restore to 1.35V */
consys_pmic_regmap_set_value(g_regmap_mt6363,
MT6363_BUCK_VS2_VOTER_CON0_CLR_ADDR, 1 << 4, 1 << 4);
/* set PMIC VRFIO18 LDO SW_EN = 0, SW_LP =0 (sw disable) */
regulator_set_mode(reg_VRFIO18, REGULATOR_MODE_NORMAL);
sleep_mode = consys_get_sleep_mode_mt6879();
if (sleep_mode == 1)
regulator_disable(reg_VRFIO18);
/* Set buckboost to 3.45V (for VCN33_1 & VCN33_2) */
if (reg_buckboost) {
regulator_set_voltage(reg_buckboost, 3450000, 3450000);
pr_info("Set buckboost to 3.45V\n");
}
}
#endif
return 0;
}
static void consys_pmic_regmap_set_value(struct regmap *rmap, unsigned int address,
unsigned int mask, unsigned int value)
{
int old_value = 0;
int new_value = 0;
if (!rmap) {
pr_err("%s regmap is NULL\n", __func__);
return;
}
regmap_read(rmap, address, &old_value);
new_value = (old_value & ~mask) | value;
regmap_write(rmap, address, new_value);
}
int consys_plt_pmic_common_power_low_power_mode_mt6879(unsigned int enable)
{
#ifdef CONFIG_FPGA_EARLY_PORTING
pr_info("[%s] not support on FPGA", __func__);
#else
int sleep_mode;
struct regmap *r = g_regmap_mt6363;
if (!enable)
return 0;
/* Set buckboost to 3.65V (for VCN33_1 & VCN33_2) */
/* Notice that buckboost might not be enabled. */
if (reg_buckboost) {
regulator_set_voltage(reg_buckboost, 3650000, 3650000);
pr_info("Set buckboost to 3.65V\n");
}
if (consys_is_rc_mode_enable_mt6879()) {
/* 1. set PMIC VRFIO18 LDO PMIC HW mode control by PMRC_EN[9][8][7][6] */
/* 1.1. set PMIC VRFIO18 LDO op_mode = 0 */
/* 1.2. set PMIC VRFIO18 LDO HW_OP_EN = 1, HW_OP_CFG = 0 */
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_RC9_OP_MODE_ADDR, 1 << 1, 0 << 1);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_RC9_OP_EN_ADDR, 1 << 1, 1 << 1);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_RC9_OP_CFG_ADDR, 1 << 1, 0 << 1);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_RC8_OP_MODE_ADDR, 1 << 0, 0 << 0);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_RC8_OP_EN_ADDR, 1 << 0, 1 << 0);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_RC8_OP_CFG_ADDR, 1 << 0, 0 << 0);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_RC7_OP_MODE_ADDR, 1 << 7, 0 << 7);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_RC7_OP_EN_ADDR, 1 << 7, 1 << 7);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_RC7_OP_CFG_ADDR, 1 << 7, 0 << 7);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_RC6_OP_MODE_ADDR, 1 << 6, 0 << 6);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_RC6_OP_EN_ADDR, 1 << 6, 1 << 6);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_RC6_OP_CFG_ADDR, 1 << 6, 0 << 6);
sleep_mode = consys_get_sleep_mode_mt6879();
if (sleep_mode == 1) {
/* set PMIC VRFIO18 LDO SW_EN = 1, SW_LP =1 */
regulator_set_mode(reg_VRFIO18, REGULATOR_MODE_IDLE);
} else {
/* set PMIC VRFIO18 LDO SW_EN = 0, SW_LP =0 */
regulator_disable(reg_VRFIO18);
regulator_set_mode(reg_VRFIO18, REGULATOR_MODE_NORMAL); /* SW_LP = 0 */
}
/* 1. set PMIC VCN13 LDO PMIC HW mode control by PMRC_EN[9][8][7][6] */
/* 1.1. set PMIC VCN13 LDO op_mode = 0 */
/* 1.2. set PMIC VCN13 LDO HW_OP_EN = 1, HW_OP_CFG = 0 */
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VCN13_RC9_OP_MODE_ADDR, 1 << 1, 0 << 1);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VCN13_RC9_OP_EN_ADDR, 1 << 1, 1 << 1);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VCN13_RC9_OP_CFG_ADDR, 1 << 1, 0 << 1);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VCN13_RC8_OP_MODE_ADDR, 1 << 0, 0 << 0);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VCN13_RC8_OP_EN_ADDR, 1 << 0, 1 << 0);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VCN13_RC8_OP_CFG_ADDR, 1 << 0, 0 << 0);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VCN13_RC7_OP_MODE_ADDR, 1 << 7, 0 << 7);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VCN13_RC7_OP_EN_ADDR, 1 << 7, 1 << 7);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VCN13_RC7_OP_CFG_ADDR, 1 << 7, 0 << 7);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VCN13_RC6_OP_MODE_ADDR, 1 << 6, 0 << 6);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VCN13_RC6_OP_EN_ADDR, 1 << 6, 1 << 6);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VCN13_RC6_OP_CFG_ADDR, 1 << 6, 0 << 6);
/* 2. set PMIC VCN13 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =1 */
regulator_set_mode(reg_VCN13, REGULATOR_MODE_IDLE);
} else {
/* 1. set PMIC VRFIO18 LDO PMIC HW mode control by SRCCLKENA0 */
/* 1.1. set PMIC VRFIO18 LDO op_mode = 1 */
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_HW0_OP_MODE_ADDR, 1 << 0, 1 << 0);
/* if (A-die sleep mode-2 ){ */
/* 1.2. set PMIC VRFIO18 LDO HW_OP_EN = 1, HW_OP_CFG = 0 */
/* }else{ //A-die sleep mode-1 */
/* 1.2. set PMIC VRFIO18 LDO HW_OP_EN = 1, HW_OP_CFG = 1 */
sleep_mode = consys_get_sleep_mode_mt6879();
if (sleep_mode == 2) {
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_HW0_OP_EN_ADDR, 1 << 0, 1 << 0);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_HW0_OP_CFG_ADDR, 1 << 0, 0 << 0);
} else {
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_HW0_OP_EN_ADDR, 1 << 0, 1 << 0);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_HW0_OP_CFG_ADDR, 1 << 0, 1 << 0);
}
/* 2. set PMIC VRFIO18 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =0 */
regulator_set_mode(reg_VRFIO18, REGULATOR_MODE_NORMAL); /* SW_LP = 0 */
/* 1. set PMIC VCN13 LDO PMIC HW mode control by SRCCLKENA0 */
/* 1.1. set PMIC VCN13 LDO op_mode = 1 */
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VCN13_HW0_OP_MODE_ADDR, 1 << 0, 1 << 0);
/* 1.2. set PMIC VCN13 LDO HW_OP_EN = 1, HW_OP_CFG = 1 */
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_HW0_OP_EN_ADDR, 1 << 0, 1 << 0);
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_HW0_OP_CFG_ADDR, 1 << 0, 1 << 0);
/* 2. set PMIC VCN13 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =0 */
regulator_set_mode(reg_VCN13, REGULATOR_MODE_NORMAL); /* SW_LP = 0 */
}
if (consys_is_rc_mode_enable_mt6879()) {
consys_pmic_vcn33_1_power_ctl_mt6879_rc(enable);
consys_pmic_vcn33_2_power_ctl_mt6879_rc(enable);
}
consys_pmic_vant18_power_ctl_mt6879(enable);
#endif
return 0;
}
int consys_plt_pmic_wifi_power_ctrl_mt6879(unsigned int enable)
{
int ret;
/* necessary in legacy mode only */
if (consys_is_rc_mode_enable_mt6879())
return 0;
ret = consys_pmic_vcn33_1_power_ctl_mt6879_lg(enable);
if (ret)
pr_info("%s VCN33_1 fail\n", (enable? "Enable" : "Disable"));
ret = consys_pmic_vcn33_2_power_ctl_mt6879_lg(enable);
if (ret)
pr_info("%s VCN33_2 fail\n", (enable? "Enable" : "Disable"));
return ret;
}
int consys_plt_pmic_bt_power_ctrl_mt6879(unsigned int enable)
{
/* necessary in legacy mode only */
if (consys_is_rc_mode_enable_mt6879())
return 0;
return consys_pmic_vcn33_1_power_ctl_mt6879_lg(enable);
}
int consys_plt_pmic_gps_power_ctrl_mt6879(unsigned int enable)
{
return 0;
}
int consys_plt_pmic_fm_power_ctrl_mt6879(unsigned int enable)
{
return 0;
}
static int consys_pmic_vcn33_1_power_ctl_mt6879_rc(bool enable)
{
struct regmap *r = g_regmap_mt6368;
if (!enable)
return 0;
/* 1. set PMIC VCN33_1 LDO PMIC HW mode control by PMRC_EN[8][7] */
/* 1.1. set PMIC VCN33_1 LDO op_mode = 0 */
/* 1.2. set PMIC VCN33_1 LDO HW_OP_EN = 1, HW_OP_CFG = 0 */
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_1_RC8_OP_MODE_ADDR, 1 << 0, 0 << 0);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_1_RC8_OP_EN_ADDR, 1 << 0, 1 << 0);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_1_RC8_OP_CFG_ADDR, 1 << 0, 0 << 0);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_1_RC7_OP_MODE_ADDR, 1 << 7, 0 << 7);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_1_RC7_OP_EN_ADDR, 1 << 7, 1 << 7);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_1_RC7_OP_CFG_ADDR, 1 << 7, 0 << 7);
/* 2. set PMIC VCN33_1 LDO SW_EN = 0, SW_LP =0 (sw disable) */
regulator_set_mode(reg_VCN33_1, REGULATOR_MODE_NORMAL);
return 0;
}
static int consys_pmic_vcn33_1_power_ctl_mt6879_lg(bool enable)
{
struct regmap *r = g_regmap_mt6368;
static int enable_count = 0;
/* In legacy mode, VCN33_1 should be turned on either WIFI or BT is on */
/* we use a counter to record the usage. */
if (enable)
enable_count++;
else
enable_count--;
pr_info("%s enable_count %d\n", __func__, enable_count);
if (enable_count < 0 || enable_count > 2) {
pr_info("enable_count %d is unexpected!!!\n", enable_count);
return 0;
}
if (enable_count == 0) {
regulator_disable(reg_VCN33_1);
return 0;
}
/* vcn33_1 is already on in these two cases */
if (enable_count == 2 || (enable_count == 1 && enable == 0))
return 0;
/* !!! Notice that following steps will be executed only when enable_count == 1 !!!*/
/* 1. set PMIC VCN33_1 LDO PMIC HW mode control by SRCCLKENA0 */
/* 1.1. set PMIC VCN33_1 LDO op_mode = 1 */
/* 1.2. set PMIC VCN33_1 LDO HW_OP_EN = 1, HW_OP_CFG = 0 */
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_1_HW0_OP_MODE_ADDR, 1 << 0, 1 << 0);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_1_HW0_OP_EN_ADDR, 1 << 0, 1 << 0);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_1_HW0_OP_CFG_ADDR, 1 << 0, 0 << 0);
/* 2. set PMIC VCN33_1 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =0 */
regulator_set_mode(reg_VCN33_1, REGULATOR_MODE_NORMAL);
regulator_enable(reg_VCN33_1);
return 0;
}
static int consys_pmic_vcn33_2_power_ctl_mt6879_lg(bool enable)
{
struct regmap *r = g_regmap_mt6368;
if (!enable)
regulator_disable(reg_VCN33_2);
else {
/* 1. set PMIC VCN33_2 LDO PMIC HW mode control by SRCCLKENA0 */
/* 1.1. set PMIC VCN33_2 LDO op_mode = 1 */
/* 1.2. set PMIC VCN33_2 LDO HW_OP_EN = 1, HW_OP_CFG = 0 */
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_2_HW0_OP_MODE_ADDR, 1 << 0, 1 << 0);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_2_HW0_OP_EN_ADDR, 1 << 0, 1 << 0);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_2_HW0_OP_CFG_ADDR, 1 << 0, 0 << 0);
/* 2. set PMIC VCN33_2 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =0 */
regulator_set_mode(reg_VCN33_2, REGULATOR_MODE_NORMAL);
regulator_enable(reg_VCN33_2);
}
return 0;
}
static int consys_pmic_vcn33_2_power_ctl_mt6879_rc(bool enable)
{
struct regmap *r = g_regmap_mt6368;
if (!enable)
return 0;
/* 1. set PMIC VCN33_2 LDO PMIC HW mode control by PMRC_EN[8] */
/* 1.1. set PMIC VCN33_2 LDO op_mode = 0 */
/* 1.2. set PMIC VCN33_2 LDO HW_OP_EN = 1, HW_OP_CFG = 0 */
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_2_RC8_OP_MODE_ADDR, 1 << 0, 0 << 0);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_2_RC8_OP_EN_ADDR, 1 << 0, 1 << 0);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VCN33_2_RC8_OP_CFG_ADDR, 1 << 0, 0 << 0);
/* 2. set PMIC VCN33_2 LDO SW_EN = 0, SW_LP =0 (sw disable) */
regulator_set_mode(reg_VCN33_2, REGULATOR_MODE_NORMAL);
return 0;
}
static int consys_pmic_vant18_power_ctl_mt6879(bool enable)
{
struct regmap *r = g_regmap_mt6368;
if (!enable) {
/* 1. VANT18 will be set to SW_EN=1 only in legacy momde. */
/* 2. VANT18 might not be enabled because power on fail before low power control is executed. */
if (consys_is_rc_mode_enable_mt6879() == 0 && regulator_is_enabled(reg_VANT18))
regulator_disable(reg_VANT18);
return 0;
}
if (consys_is_rc_mode_enable_mt6879()) {
/* 1. set PMIC VANT18 LDO PMIC HW mode control by PMRC_EN[10][6] */
/* 1.1. set PMIC VANT18 LDO op_mode = 0 */
/* 1.2. set PMIC VANT18 LDO HW_OP_EN = 1, HW_OP_CFG = 0 */
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VANT18_RC10_OP_MODE_ADDR, 1 << 2, 0 << 2);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VANT18_RC10_OP_EN_ADDR, 1 << 2, 1 << 2);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VANT18_RC10_OP_CFG_ADDR, 1 << 2, 0 << 2);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VANT18_RC6_OP_MODE_ADDR, 1 << 6, 0 << 6);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VANT18_RC6_OP_EN_ADDR, 1 << 6, 1 << 6);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VANT18_RC6_OP_CFG_ADDR, 1 << 6, 0 << 6);
} else {
/* 1. set PMIC VANT18 LDO PMIC HW mode control by SRCCLKENA0 */
/* 1.1. set PMIC VANT18 LDO op_mode = 1 */
/* 1.2. set PMIC VANT18 LDO HW_OP_EN = 1, HW_OP_CFG = 0 */
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VANT18_HW0_OP_MODE_ADDR, 1 << 0, 1 << 0);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VANT18_HW0_OP_EN_ADDR, 1 << 0, 1 << 0);
consys_pmic_regmap_set_value(r, MT6368_RG_LDO_VANT18_HW0_OP_CFG_ADDR, 1 << 0, 0 << 0);
/* 2. set PMIC VANT18 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =0 */
regulator_set_mode(reg_VANT18, REGULATOR_MODE_NORMAL);
regulator_enable(reg_VANT18);
}
return 0;
}
static void dump_adie_cr(enum sys_spi_subsystem subsystem, const unsigned int *adie_cr, int num, char *title)
{
#define LOG_TMP_BUF_SZ 256
unsigned int adie_value;
char tmp[LOG_TMP_BUF_SZ] = {'\0'};
char tmp_buf[LOG_TMP_BUF_SZ] = {'\0'};
int i;
memset(tmp_buf, '\0', LOG_TMP_BUF_SZ);
for (i = 0; i < num; i++) {
consys_spi_read_mt6879(subsystem, adie_cr[i], &adie_value);
if (snprintf(tmp, LOG_TMP_BUF_SZ, "[0x%04x: 0x%08x]", adie_cr[i], adie_value) >= 0)
strncat(tmp_buf, tmp, strlen(tmp));
}
pr_info("%s:%s\n", title, tmp_buf);
}
static int consys_plt_pmic_event_notifier_mt6879(unsigned int id, unsigned int event)
{
#define ATOP_DUMP_NUM 12
#define AWF_DUMP_NUM 3
int ret;
const unsigned int adie_top_cr_list[ATOP_DUMP_NUM] = {
0x03C, 0x090, 0x094, 0x0A0,
0x0C8, 0x0FC, 0xA10, 0xB00,
0xAFC, 0x160, 0xC54, 0xC58,
};
const unsigned int adie_wf_cr_list[AWF_DUMP_NUM] = {
0xFFF, 0x81, 0x80,
};
consys_pmic_debug_log_mt6879();
ret = consys_hw_force_conninfra_wakeup();
if (ret) {
pr_info("[%s] force conninfra wakeup fail\n", __func__);
return -1;
}
/* dump d-die cr */
consys_hw_is_bus_hang();
/* dump a-die cr */
dump_adie_cr(SYS_SPI_TOP, adie_top_cr_list, ATOP_DUMP_NUM, "A-die TOP");
dump_adie_cr(SYS_SPI_WF, adie_wf_cr_list, AWF_DUMP_NUM, "A-die WF0");
dump_adie_cr(SYS_SPI_WF1, adie_wf_cr_list, AWF_DUMP_NUM, "A-die WF1");
consys_hw_force_conninfra_sleep();
return 0;
}
static int consys_vcn13_oc_notify(struct notifier_block *nb, unsigned long event, void *unused)
{
static int oc_counter = 0;
static int oc_dump = 0;
if (event != REGULATOR_EVENT_OVER_CURRENT)
return NOTIFY_OK;
oc_counter++;
pr_info("[%s] VCN13 OC times: %d\n", __func__, oc_counter);
if (oc_counter <= 30)
oc_dump = 1;
else if (oc_counter == (oc_dump * 100))
oc_dump++;
else
return NOTIFY_OK;
if (g_dev_cb != NULL && g_dev_cb->conninfra_pmic_event_notifier != NULL)
g_dev_cb->conninfra_pmic_event_notifier(0, 0);
return NOTIFY_OK;
}
static int consys_vrfio18_oc_notify(struct notifier_block *nb, unsigned long event, void *unused)
{
static int oc_counter = 0;
static int oc_dump = 0;
if (event != REGULATOR_EVENT_OVER_CURRENT)
return NOTIFY_OK;
oc_counter++;
pr_info("[%s] VRFIO18 OC times: %d\n", __func__, oc_counter);
if (oc_counter <= 30)
oc_dump = 1;
else if (oc_counter == (oc_dump * 100))
oc_dump++;
else
return NOTIFY_OK;
if (g_dev_cb != NULL && g_dev_cb->conninfra_pmic_event_notifier != NULL)
g_dev_cb->conninfra_pmic_event_notifier(0, 0);
return NOTIFY_OK;
}
void consys_pmic_debug_log_mt6879(void)
{
struct regmap *r = g_regmap_mt6363;
struct regmap *r2 = g_regmap_mt6368;
int vcn13, vrfio18, vcn33_1, vcn33_2, vant18;
if (!r || !r2) {
pr_notice("%s regmap is NULL\n", __func__);
return;
}
regmap_read(r, MT6363_RG_LDO_VCN13_MON_ADDR, &vcn13);
regmap_read(r, MT6363_RG_LDO_VRFIO18_MON_ADDR, &vrfio18);
regmap_read(r2, MT6368_RG_LDO_VCN33_1_MON_ADDR, &vcn33_1);
regmap_read(r2, MT6368_RG_LDO_VCN33_2_MON_ADDR, &vcn33_2);
regmap_read(r2, MT6368_RG_LDO_VANT18_MON_ADDR, &vant18);
pr_info("%s vcn13:0x%08x,vrfio18:0x%08x,vcn33_1:0x%08x,vcn33_2:0x%08x,vant18:0x%08x\n",
__func__, vcn13, vrfio18, vcn33_1, vcn33_2, vant18);
}

770
drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/mt6879_pos.c Normal file
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@ -0,0 +1,770 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#include <linux/pinctrl/consumer.h>
#include <linux/irqflags.h>
#include <connectivity_build_in_adapter.h>
#include <linux/pm_runtime.h>
#include "consys_hw.h" /* for semaphore index */
/* platform dependent */
#include "plat_def.h"
/* macro for read/write cr */
#include "consys_reg_util.h"
#include "plat_def.h"
/* cr base address */
#include "mt6879_consys_reg.h"
/* cr offset */
#include "mt6879_consys_reg_offset.h"
/* For function declaration */
#include "mt6879.h"
#include "mt6879_pos.h"
#include "mt6879_pos_gen.h"
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
#define CONSYS_SLEEP_MODE_1 (0x1 << 0)
#define CONSYS_SLEEP_MODE_2 (0x1 << 1)
#define MT6637E1 0x66378A00
#define MT6637E2 0x66378A01
#define SEMA_HOLD_TIME_THRESHOLD 10 //10 ms
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
struct a_die_reg_config {
unsigned int reg;
unsigned int mask;
unsigned int config;
};
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
static u64 sema_get_time[CONN_SEMA_NUM_MAX];
#ifndef CONFIG_FPGA_EARLY_PORTING
static const char* get_spi_sys_name(enum sys_spi_subsystem subsystem);
#endif
static int connsys_adie_clock_buffer_setting(unsigned int curr_status, unsigned int next_status);
unsigned int consys_emi_set_remapping_reg_mt6879(
phys_addr_t con_emi_base_addr,
phys_addr_t md_shared_emi_base_addr)
{
return consys_emi_set_remapping_reg_mt6879_gen(con_emi_base_addr, md_shared_emi_base_addr, 16);
}
int consys_conninfra_on_power_ctrl_mt6879(unsigned int enable)
{
int ret = 0;
#if MTK_CONNINFRA_CLOCK_BUFFER_API_AVAILABLE
ret = consys_platform_spm_conn_ctrl_mt6879(enable);
#else
ret = consys_conninfra_on_power_ctrl_mt6879_gen(enable);
#endif /* MTK_CONNINFRA_CLOCK_BUFFER_API_AVAILABLE */
consys_update_ap2conn_hclk_mt6879_gen();
return ret;
}
int consys_conninfra_wakeup_mt6879(void)
{
return consys_conninfra_wakeup_mt6879_gen();
}
int consys_conninfra_sleep_mt6879(void)
{
return consys_conninfra_sleep_mt6879_gen();
}
void consys_set_if_pinmux_mt6879(unsigned int enable)
{
#ifndef CFG_CONNINFRA_ON_CTP
struct pinctrl_state *tcxo_pinctrl_set;
struct pinctrl_state *tcxo_pinctrl_clr;
int ret = -1;
#endif
if (enable) {
consys_set_if_pinmux_mt6879_gen(1);
/* if(TCXO mode)
* Set GPIO135 pinmux for TCXO mode (Aux3)(CONN_TCXOENA_REQ)
*/
if (consys_co_clock_type_mt6879() == CONNSYS_CLOCK_SCHEMATIC_26M_EXTCXO) {
#if defined(CFG_CONNINFRA_ON_CTP)
consys_set_gpio_tcxo_mode_mt6879_gen(1, 1);
#else
if (!IS_ERR(g_conninfra_pinctrl_ptr)) {
tcxo_pinctrl_set = pinctrl_lookup_state(g_conninfra_pinctrl_ptr, "conninfra_tcxo_set");
if (!IS_ERR(tcxo_pinctrl_set)) {
ret = pinctrl_select_state(g_conninfra_pinctrl_ptr, tcxo_pinctrl_set);
if (ret)
pr_err("[%s] set TCXO mode error: %d\n", __func__, ret);
}
}
#endif /* defined(CFG_CONNINFRA_ON_CTP) */
}
} else {
consys_set_if_pinmux_mt6879_gen(0);
if (consys_co_clock_type_mt6879() == CONNSYS_CLOCK_SCHEMATIC_26M_EXTCXO) {
#if defined(CFG_CONNINFRA_ON_CTP)
consys_set_gpio_tcxo_mode_mt6879_gen(1, 0);
#else
if (!IS_ERR(g_conninfra_pinctrl_ptr)) {
tcxo_pinctrl_clr = pinctrl_lookup_state(g_conninfra_pinctrl_ptr, "conninfra_tcxo_clr");
if (!IS_ERR(tcxo_pinctrl_clr)) {
ret = pinctrl_select_state(g_conninfra_pinctrl_ptr, tcxo_pinctrl_clr);
if (ret)
pr_err("[%s] clear TCXO mode error: %d\n", __func__, ret);
}
}
#endif /* defined(CFG_CONNINFRA_ON_CTP) */
}
}
}
int consys_polling_chipid_mt6879(void)
{
return consys_polling_chipid_mt6879_gen(NULL);
}
int connsys_d_die_cfg_mt6879(void)
{
unsigned int d_die_efuse = 0;
/* Reset conninfra sysram */
consys_init_conninfra_sysram_mt6879_gen();
/* Read D-die Efuse
* AP2CONN_EFUSE_DATA 0x1801_1020
* Write to conninfra sysram: CONN_INFRA_SYSRAM_SW_CR_D_DIE_EFUSE(0x1805_3820)
*/
connsys_get_d_die_efuse_mt6879_gen(&d_die_efuse);
CONSYS_REG_WRITE(
CONN_INFRA_SYSRAM_SW_CR_D_DIE_EFUSE, d_die_efuse);
connsys_d_die_cfg_mt6879_gen();
#if defined(CONNINFRA_PLAT_BUILD_MODE)
CONSYS_REG_WRITE(CONN_INFRA_SYSRAM_SW_CR_BUILD_MODE, CONNINFRA_PLAT_BUILD_MODE);
pr_info("[%s] Write CONN_INFRA_SYSRAM_SW_CR_BUILD_MODE to 0x%08x\n",
__func__, CONSYS_REG_READ(CONN_INFRA_SYSRAM_SW_CR_BUILD_MODE));
#endif
return 0;
}
static int connsys_adie_clock_buffer_setting(unsigned int curr_status, unsigned int next_status)
{
#ifndef CONFIG_FPGA_EARLY_PORTING
unsigned int hw_version;
int ret = 0;
hw_version = CONSYS_REG_READ(CONN_INFRA_SYSRAM_SW_CR_A_DIE_CHIP_ID);
ret = connsys_adie_clock_buffer_setting_mt6879_gen(
curr_status, next_status, hw_version, CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT);
if (ret)
return -1;
#endif
return 0;
}
int connsys_spi_master_cfg_mt6879(unsigned int next_status)
{
connsys_wt_slp_top_ctrl_adie6637_mt6879_gen();
return 0;
}
int consys_get_sleep_mode_mt6879(void)
{
int platform_config;
platform_config = consys_hw_get_platform_config();
if (platform_config & CONSYS_SLEEP_MODE_1)
return 1;
else if (platform_config & CONSYS_SLEEP_MODE_2)
return 2;
if (conn_hw_env.adie_hw_version == MT6637E1)
return 1;
/* This is a temp solution for WIFI RX fail when sleep mode = 2 */
return 1;
}
int connsys_a_die_cfg_mt6879(void)
{
#ifdef CONFIG_FPGA_EARLY_PORTING
pr_info("[%s] not support on FPGA", __func__);
#else /* CONFIG_FPGA_EARLY_PORTING */
unsigned int adie_id = 0;
unsigned int hw_ver_id = 0;
int check = 0;
struct consys_plat_thermal_data_mt6879 input;
void __iomem *sysram_efuse_list[16] = { 0 };
unsigned int sleep_mode = 0;
unsigned int clock_type = 0;
unsigned int sysram_clock_type = 0;
clock_type = consys_co_clock_type_mt6879();
if (clock_type == CONNSYS_CLOCK_SCHEMATIC_52M_COTMS) {
pr_info("A-die co-clock 52M\n");
sysram_clock_type = 2;
} else if (clock_type == CONNSYS_CLOCK_SCHEMATIC_26M_COTMS) {
pr_info("A-die co-clock 26M\n");
sysram_clock_type = 1;
} else {
pr_info("A-die tcxo 26M\n");
sysram_clock_type = 3;
}
// Write clock type to conninfra sysram
// 0: default
// 1: co-clock 26M
// 2: co_clock 52M
// 3: tcxo 26M
CONSYS_REG_WRITE(CONN_INFRA_SYSRAM_SW_CR_CLOCK_TYPE, sysram_clock_type);
memset(&input, 0, sizeof(struct consys_plat_thermal_data_mt6879));
connsys_a_die_switch_to_gpio_mode_mt6879_gen();
connsys_adie_top_ck_en_ctl_mt6879_gen(1);
connsys_a_die_cfg_deassert_adie_reset_mt6879_gen();
if (consys_sema_acquire_timeout_mt6879(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL) {
connsys_adie_top_ck_en_ctl_mt6879_gen(0);
pr_err("[SPI READ] Require semaphore fail\n");
return CONNINFRA_SPI_OP_FAIL;
}
check = connsys_a_die_cfg_read_adie_id_mt6879_gen(&adie_id, &hw_ver_id);
if (check) {
consys_sema_release_mt6879(CONN_SEMA_RFSPI_INDEX);
return -1;
}
pr_info("[%s] A-die chip id: 0x%08x\n", __func__, adie_id);
conn_hw_env.adie_hw_version = adie_id;
/* Write to conninfra sysram */
CONSYS_REG_WRITE(CONN_INFRA_SYSRAM_SW_CR_A_DIE_CHIP_ID, adie_id);
sysram_efuse_list[0] = (void __iomem *)CONN_INFRA_SYSRAM_SW_CR_A_DIE_EFUSE_DATA_0;
sysram_efuse_list[1] = (void __iomem *)CONN_INFRA_SYSRAM_SW_CR_A_DIE_EFUSE_DATA_1;
sysram_efuse_list[2] = (void __iomem *)CONN_INFRA_SYSRAM_SW_CR_A_DIE_EFUSE_DATA_2;
sysram_efuse_list[3] = (void __iomem *)CONN_INFRA_SYSRAM_SW_CR_A_DIE_EFUSE_DATA_3;
connsys_a_die_efuse_read_get_efuse_info_mt6879_gen(sysram_efuse_list,
&(input.slop_molecule), &(input.thermal_b), &(input.offset));
pr_info("slop_molecule=[%d], thermal_b =[%d], offset=[%d]", input.slop_molecule, input.thermal_b, input.offset);
update_thermal_data_mt6879(&input);
connsys_a_die_cfg_PART2_mt6879_gen(hw_ver_id);
consys_sema_release_mt6879(CONN_SEMA_RFSPI_INDEX);
connsys_a_die_switch_to_conn_mode_mt6879_gen();
conn_hw_env.is_rc_mode = consys_is_rc_mode_enable_mt6879();
pr_info("[%s] Check rc mode=[%d]\n", __func__, conn_hw_env.is_rc_mode);
#endif /* CONFIG_FPGA_EARLY_PORTING */
sleep_mode = consys_get_sleep_mode_mt6879();
pr_info("sleep_mode = %d\n", sleep_mode);
connsys_wt_slp_top_power_saving_ctrl_adie6637_mt6879_gen(adie_id, sleep_mode);
return 0;
}
int connsys_afe_wbg_cal_mt6879(void)
{
return connsys_afe_wbg_cal_mt6879_gen(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT);
}
int connsys_subsys_pll_initial_mt6879(void)
{
return connsys_subsys_pll_initial_xtal_26000k_mt6879_gen();
}
int connsys_low_power_setting_mt6879(unsigned int curr_status, unsigned int next_status)
{
connsys_adie_clock_buffer_setting(curr_status, next_status);
if (curr_status == 0) {
connsys_low_power_setting_mt6879_gen();
} else {
/* Not first on */
}
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
/* !!!!!!!!!!!!!!!!!!!!!! CANNOT add code after HERE!!!!!!!!!!!!!!!!!!!!!!!!!! */
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
return 0;
}
static int consys_sema_acquire(unsigned int index)
{
if (index >= CONN_SEMA_NUM_MAX)
return CONN_SEMA_GET_FAIL;
if (CONSYS_REG_READ_BIT(
(CONN_SEMAPHORE_CONN_SEMA00_M2_OWN_STA_ADDR + index*4), 0x1) == 0x1) {
return CONN_SEMA_GET_SUCCESS;
} else {
return CONN_SEMA_GET_FAIL;
}
}
int consys_sema_acquire_timeout_mt6879(unsigned int index, unsigned int usec)
{
int i;
unsigned long flags = 0;
if (index >= CONN_SEMA_NUM_MAX)
return CONN_SEMA_GET_FAIL;
for (i = 0; i < usec; i++) {
if (consys_sema_acquire(index) == CONN_SEMA_GET_SUCCESS) {
sema_get_time[index] = jiffies;
if (index == CONN_SEMA_RFSPI_INDEX)
local_irq_save(flags);
return CONN_SEMA_GET_SUCCESS;
}
udelay(1);
}
pr_err("Get semaphore 0x%x timeout, dump status:\n", index);
pr_err("M0:[0x%x] M1:[0x%x] M2:[0x%x] M3:[0x%x]\n",
CONSYS_REG_READ(CONN_SEMAPHORE_CONN_SEMA_OWN_BY_M0_STA_REP_1_ADDR),
CONSYS_REG_READ(CONN_SEMAPHORE_CONN_SEMA_OWN_BY_M1_STA_REP_1_ADDR),
CONSYS_REG_READ(CONN_SEMAPHORE_CONN_SEMA_OWN_BY_M2_STA_REP_1_ADDR),
CONSYS_REG_READ(CONN_SEMAPHORE_CONN_SEMA_OWN_BY_M3_STA_REP_1_ADDR));
/* Debug feature in Android, remove it in CTP */
#if 0
consys_reg_mng_dump_cpupcr(CONN_DUMP_CPUPCR_TYPE_ALL, 10, 200);
#endif
return CONN_SEMA_GET_FAIL;
}
void consys_sema_release_mt6879(unsigned int index)
{
u64 duration;
unsigned long flags = 0;
if (index >= CONN_SEMA_NUM_MAX)
return;
CONSYS_REG_WRITE(
(CONN_SEMAPHORE_CONN_SEMA00_M2_OWN_REL_ADDR + index*4), 0x1);
duration = jiffies_to_msecs(jiffies - sema_get_time[index]);
if (index == CONN_SEMA_RFSPI_INDEX)
local_irq_restore(flags);
if (duration > SEMA_HOLD_TIME_THRESHOLD)
pr_notice("%s hold semaphore (%d) for %llu ms\n", __func__, index, duration);
}
struct spi_op {
unsigned int busy_cr;
unsigned int polling_bit;
unsigned int addr_cr;
unsigned int read_addr_format;
unsigned int write_addr_format;
unsigned int write_data_cr;
unsigned int read_data_cr;
unsigned int read_data_mask;
};
static const struct spi_op spi_op_array[SYS_SPI_MAX] = {
/* SYS_SPI_WF1 */
{
CONN_RF_SPI_MST_REG_SPI_STA_OFFSET, 1,
CONN_RF_SPI_MST_REG_SPI_WF_ADDR_OFFSET, 0x00001000, 0x00000000,
CONN_RF_SPI_MST_REG_SPI_WF_WDAT_OFFSET,
CONN_RF_SPI_MST_REG_SPI_WF_RDAT_OFFSET, 0xffffffff
},
/* SYS_SPI_WF0 */
{
CONN_RF_SPI_MST_REG_SPI_STA_OFFSET, 1,
CONN_RF_SPI_MST_REG_SPI_WF_ADDR_OFFSET, 0x00003000, 0x00002000,
CONN_RF_SPI_MST_REG_SPI_WF_WDAT_OFFSET,
CONN_RF_SPI_MST_REG_SPI_WF_RDAT_OFFSET, 0xffffffff
},
/* SYS_SPI_BT */
{
CONN_RF_SPI_MST_REG_SPI_STA_OFFSET, 2,
CONN_RF_SPI_MST_REG_SPI_BT_ADDR_OFFSET, 0x00005000, 0x00004000,
CONN_RF_SPI_MST_REG_SPI_BT_WDAT_OFFSET,
CONN_RF_SPI_MST_REG_SPI_BT_RDAT_OFFSET, 0x000000ff
},
/* SYS_SPI_FM */
{
CONN_RF_SPI_MST_REG_SPI_STA_OFFSET, 3,
CONN_RF_SPI_MST_REG_SPI_FM_ADDR_OFFSET, 0x00007000, 0x00006000,
CONN_RF_SPI_MST_REG_SPI_FM_WDAT_OFFSET,
CONN_RF_SPI_MST_REG_SPI_FM_RDAT_OFFSET, 0x0000ffff
},
/* SYS_SPI_GPS */
{
CONN_RF_SPI_MST_REG_SPI_STA_OFFSET, 4,
CONN_RF_SPI_MST_REG_SPI_GPS_GPS_ADDR_OFFSET, 0x00009000, 0x00008000,
CONN_RF_SPI_MST_REG_SPI_GPS_GPS_WDAT_OFFSET,
CONN_RF_SPI_MST_REG_SPI_GPS_GPS_RDAT_OFFSET, 0x0000ffff
},
/* SYS_SPI_TOP */
{
CONN_RF_SPI_MST_REG_SPI_STA_OFFSET, 5,
CONN_RF_SPI_MST_REG_SPI_TOP_ADDR_OFFSET, 0x0000b000, 0x0000a000,
CONN_RF_SPI_MST_REG_SPI_TOP_WDAT_OFFSET,
CONN_RF_SPI_MST_REG_SPI_TOP_RDAT_OFFSET, 0xffffffff
},
/* SYS_SPI_WF2 */
{
CONN_RF_SPI_MST_REG_SPI_STA_OFFSET, 1,
CONN_RF_SPI_MST_REG_SPI_WF_ADDR_OFFSET, 0x0000d000, 0x0000c000,
CONN_RF_SPI_MST_REG_SPI_WF_WDAT_OFFSET,
CONN_RF_SPI_MST_REG_SPI_WF_RDAT_OFFSET, 0xffffffff
},
/* SYS_SPI_WF3 */
{
CONN_RF_SPI_MST_REG_SPI_STA_OFFSET, 1,
CONN_RF_SPI_MST_REG_SPI_WF_ADDR_OFFSET, 0x0000f000, 0x0000e000,
CONN_RF_SPI_MST_REG_SPI_WF_WDAT_OFFSET,
CONN_RF_SPI_MST_REG_SPI_WF_RDAT_OFFSET, 0xffffffff
},
};
int consys_spi_read_nolock_mt6879(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data)
{
/* Read action:
* 1. Polling busy_cr[polling_bit] should be 0
* 2. Write addr_cr with data being {read_addr_format | addr[11:0]}
* 3. Trigger SPI by writing write_data_cr as 0
* 4. Polling busy_cr[polling_bit] as 0
* 5. Read data_cr[data_mask]
*/
int check = 0;
const struct spi_op* op = &spi_op_array[subsystem];
if (!data) {
pr_err("[%s] invalid data ptr\n", __func__);
return CONNINFRA_SPI_OP_FAIL;
}
#ifndef CONFIG_FPGA_EARLY_PORTING
CONSYS_REG_BIT_POLLING(
CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->busy_cr, op->polling_bit, 0, 100, 50, check);
if (check != 0) {
pr_err("[%s][%s][STEP1] polling 0x%08x bit %d fail. Value=0x%08x\n",
__func__, get_spi_sys_name(subsystem), CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->busy_cr,
op->polling_bit,
CONSYS_REG_READ(CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->busy_cr));
return CONNINFRA_SPI_OP_FAIL;
}
#endif
CONSYS_REG_WRITE(CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->addr_cr, (op->read_addr_format | addr));
CONSYS_REG_WRITE(CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->write_data_cr, 0);
#ifndef CONFIG_FPGA_EARLY_PORTING
udelay(1);
check = 0;
CONSYS_REG_BIT_POLLING(
CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->busy_cr, op->polling_bit, 0, 100, 50, check);
if (check != 0) {
pr_err("[%s][%d][STEP4] polling 0x%08x bit %d fail. Value=0x%08x\n",
__func__, subsystem, CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->busy_cr,
op->polling_bit,
CONSYS_REG_READ(CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->busy_cr));
return CONNINFRA_SPI_OP_FAIL;
}
#endif
check = CONSYS_REG_READ_BIT(
CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->read_data_cr, op->read_data_mask);
*data = check;
return 0;
}
int consys_spi_read_mt6879(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data)
{
int ret = 0;
/* Get semaphore before read */
if (consys_sema_acquire_timeout_mt6879(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL) {
pr_err("[SPI READ] Require semaphore fail\n");
return CONNINFRA_SPI_OP_FAIL;
}
ret = consys_spi_read_nolock_mt6879(subsystem, addr, data);
consys_sema_release_mt6879(CONN_SEMA_RFSPI_INDEX);
return ret;
}
int consys_spi_write_nolock_mt6879(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data)
{
#ifndef CONFIG_FPGA_EARLY_PORTING
int check = 0;
#endif
const struct spi_op* op = &spi_op_array[subsystem];
/* Write action:
* 1. Wait busy_cr[polling_bit] as 0
* 2. Write addr_cr with data being {write_addr_format | addr[11:0]
* 3. Write write_data_cr ad data
* 4. Wait busy_cr[polling_bit] as 0
*/
#ifndef CONFIG_FPGA_EARLY_PORTING
CONSYS_REG_BIT_POLLING(
CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->busy_cr,
op->polling_bit, 0, 100, 50, check);
if (check != 0) {
pr_err("[%s][%s][STEP1] polling 0x%08x bit %d fail. Value=0x%08x\n",
__func__, get_spi_sys_name(subsystem), CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->busy_cr,
op->polling_bit,
CONSYS_REG_READ(CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->busy_cr));
return CONNINFRA_SPI_OP_FAIL;
}
#endif
CONSYS_REG_WRITE(CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->addr_cr, (op->write_addr_format | addr));
CONSYS_REG_WRITE(CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->write_data_cr, data);
#ifndef CONFIG_FPGA_EARLY_PORTING
udelay(1);
check = 0;
CONSYS_REG_BIT_POLLING(CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->busy_cr, op->polling_bit, 0, 100, 50, check);
if (check != 0) {
pr_err("[%s][%s][STEP4] polling 0x%08x bit %d fail. Value=0x%08x\n",
__func__, get_spi_sys_name(subsystem), CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->busy_cr,
op->polling_bit,
CONSYS_REG_READ(CONN_REG_CONN_RF_SPI_MST_REG_ADDR + op->busy_cr));
return CONNINFRA_SPI_OP_FAIL;
}
#endif
return 0;
}
int consys_spi_write_mt6879(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data)
{
int ret = 0;
/* Get semaphore before read */
if (consys_sema_acquire_timeout_mt6879(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL) {
pr_err("[SPI WRITE] Require semaphore fail\n");
return CONNINFRA_SPI_OP_FAIL;
}
ret = consys_spi_write_nolock_mt6879(subsystem, addr, data);
consys_sema_release_mt6879(CONN_SEMA_RFSPI_INDEX);
return ret;
}
int consys_spi_update_bits_mt6879(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data, unsigned int mask)
{
int ret = 0;
unsigned int curr_val = 0;
unsigned int new_val = 0;
bool change = false;
/* Get semaphore before updating bits */
if (consys_sema_acquire_timeout_mt6879(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL) {
pr_err("[SPI WRITE] Require semaphore fail\n");
return CONNINFRA_SPI_OP_FAIL;
}
ret = consys_spi_read_nolock_mt6879(subsystem, addr, &curr_val);
if (ret) {
consys_sema_release_mt6879(CONN_SEMA_RFSPI_INDEX);
#ifndef CONFIG_FPGA_EARLY_PORTING
pr_err("[%s][%s] Get 0x%08x error, ret=%d",
__func__, get_spi_sys_name(subsystem), addr, ret);
#endif
return CONNINFRA_SPI_OP_FAIL;
}
new_val = (curr_val & (~mask)) | (data & mask);
change = (curr_val != new_val);
if (change) {
ret = consys_spi_write_nolock_mt6879(subsystem, addr, new_val);
}
consys_sema_release_mt6879(CONN_SEMA_RFSPI_INDEX);
return ret;
}
int consys_spi_clock_switch_mt6879(enum connsys_spi_speed_type type)
{
int check;
int ret = 0;
/* Get semaphore before read */
if (consys_sema_acquire_timeout_mt6879(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL) {
pr_err("[SPI CLOCK SWITCH] Require semaphore fail\n");
return -1;
}
if (type == CONNSYS_SPI_SPEED_26M) {
/* SPI clock from HS to osc (source:BPLL) (FM) */
/* 0x18042110 WR [4]:1'b1 => Disable hs clock of FM */
/* 0x18042110 WR [5]:1'b1 => Disable hs clock mux to FM */
/* 0x18012088 WR [4]:1'b1 => Disable SPI BPLL from FM */
CONSYS_REG_WRITE_HW_ENTRY(
CONN_RF_SPI_MST_REG_SPI_HSCK_CTL_CLR_FM_HS_EN, 1);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_RF_SPI_MST_REG_SPI_HSCK_CTL_CLR_FM_SPI_CK_CTL, 1);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_CLKGEN_TOP_CKGEN_RFSPI_PLL_REQ_CLR_CONN_RFSPI_BPLL_REQ_M4, 1);
} else if (type == CONNSYS_SPI_SPEED_64M) {
/* SPI clock from osc_ck to HS (source:BPLL) (FM) */
/* 0x18012084 WR [4]:1'b1 => 1'b1: Enable SPI BPLL from FM */
/* 0x18011030 POLLING [1] == 1'b1 */
/* 0x1804210C WR [5]:1'b1 => Select hs clock mux to FM */
/* 0x1804210C WR [4]:1'b1 => Select hs clock of FM */
CONSYS_REG_WRITE_HW_ENTRY(
CONN_CLKGEN_TOP_CKGEN_RFSPI_PLL_REQ_SET_CONN_RFSPI_BPLL_REQ_M4, 1);
check = 0;
CONSYS_REG_BIT_POLLING(CONN_CFG_PLL_STATUS_ADDR, 1, 1, 100, 50, check);
if (check == 0) {
CONSYS_REG_WRITE_HW_ENTRY(CONN_RF_SPI_MST_REG_SPI_HSCK_CTL_SET_FM_SPI_CK_CTL, 1);
CONSYS_REG_WRITE_HW_ENTRY(CONN_RF_SPI_MST_REG_SPI_HSCK_CTL_SET_FM_HS_EN, 1);
} else {
ret = -1;
pr_info("[%s] BPLL enable fail: 0x%08x",
__func__, CONSYS_REG_READ(CONN_CFG_PLL_STATUS_ADDR));
}
} else {
pr_err("[%s] wrong parameter %d\n", __func__, type);
}
consys_sema_release_mt6879(CONN_SEMA_RFSPI_INDEX);
return ret;
}
int consys_subsys_status_update_mt6879(bool on, int radio)
{
if (radio < CONNDRV_TYPE_BT || radio > CONNDRV_TYPE_WIFI) {
pr_err("[%s] wrong parameter: %d\n", __func__, radio);
return -1;
}
if (consys_sema_acquire_timeout_mt6879(CONN_SEMA_CONN_INFRA_COMMON_SYSRAM_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL) {
pr_err("[%s] acquire semaphore (%d) timeout\n",
__func__, CONN_SEMA_CONN_INFRA_COMMON_SYSRAM_INDEX);
return -1;
}
/* When FM power on, give priority of selecting spi clock */
if (radio == CONNDRV_TYPE_FM) {
if (consys_sema_acquire_timeout_mt6879(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_SUCCESS) {
CONSYS_REG_WRITE_HW_ENTRY(CONN_RF_SPI_MST_REG_SPI_HSCK_CTL_FM_SPI_CK_CTL, on);
consys_sema_release_mt6879(CONN_SEMA_RFSPI_INDEX);
}
}
if (on) {
CONSYS_SET_BIT(CONN_INFRA_SYSRAM_SW_CR_RADIO_STATUS, (0x1 << radio));
} else {
CONSYS_CLR_BIT(CONN_INFRA_SYSRAM_SW_CR_RADIO_STATUS, (0x1 << radio));
}
consys_sema_release_mt6879(CONN_SEMA_CONN_INFRA_COMMON_SYSRAM_INDEX);
return 0;
}
bool consys_is_rc_mode_enable_mt6879(void)
{
#ifdef CONFIG_FPGA_EARLY_PORTING
return false;
#else /* CONFIG_FPGA_EARLY_PORTING */
#ifdef CFG_CONNINFRA_ON_CTP
bool ret = (bool)CONSYS_REG_READ_BIT(RC_CENTRAL_CFG1, 0x1);
return ret;
#else /* CFG_CONNINFRA_ON_CTP */
static bool ever_read = false;
void __iomem *addr = NULL;
static bool ret = false;
/* Base: SRCLEN_RC (0x1C00_D000)
* Offset: 0x004 CENTRAL_CFG1
* [0] srclken_rc_en
*/
if (!ever_read) {
addr = ioremap(RC_CENTRAL_CFG1, 0x4);
if (addr != NULL) {
ret = (bool)CONSYS_REG_READ_BIT(addr, 0x1);
iounmap(addr);
ever_read = true;
} else
pr_err("[%s] remap 0x%08x fail\n", __func__, RC_CENTRAL_CFG1);
}
return ret;
#endif /* CFG_CONNINFRA_ON_CTP */
#endif /* CONFIG_FPGA_EARLY_PORTING */
}
#ifndef CONFIG_FPGA_EARLY_PORTING
void consys_spi_write_offset_range_nolock_mt6879(
enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int value,
unsigned int reg_offset, unsigned int value_offset, unsigned int size)
{
unsigned int data = 0, data2;
unsigned int reg_mask;
int ret;
value = (value >> value_offset);
value = GET_BIT_RANGE(value, size, 0);
value = (value << reg_offset);
ret = consys_spi_read_nolock_mt6879(subsystem, addr, &data);
if (ret) {
pr_err("[%s][%s] Get 0x%08x error, ret=%d",
__func__, get_spi_sys_name(subsystem), addr, ret);
return;
}
reg_mask = GENMASK(reg_offset + size - 1, reg_offset);
data2 = data & (~reg_mask);
data2 = (data2 | value);
consys_spi_write_nolock_mt6879(subsystem, addr, data2);
}
const char* get_spi_sys_name(enum sys_spi_subsystem subsystem)
{
const static char* spi_system_name[SYS_SPI_MAX] = {
"SYS_SPI_WF1",
"SYS_SPI_WF",
"SYS_SPI_BT",
"SYS_SPI_FM",
"SYS_SPI_GPS",
"SYS_SPI_TOP",
"SYS_SPI_WF2",
"SYS_SPI_WF3",
};
if (subsystem >= SYS_SPI_WF1 && subsystem < SYS_SPI_MAX)
return spi_system_name[subsystem];
return "UNKNOWN";
}
#endif
int connsys_adie_top_ck_en_ctl_mt6879(bool onoff)
{
return connsys_adie_top_ck_en_ctl_mt6879_gen(onoff);
}

2157
drivers/misc/mediatek/connectivity/conninfra/platform/mt6879/mt6879_pos_gen.c Normal file
View file

File diff suppressed because it is too large Load diff

2
drivers/misc/mediatek/connectivity/conninfra/platform/mt6885/include/mt6885_pos.h
View file

@ -20,7 +20,7 @@
#define _PLATFORM_MT6885_POS_H_
unsigned int consys_emi_set_remapping_reg_mt6885(phys_addr_t, phys_addr_t, phys_addr_t);
unsigned int consys_emi_set_remapping_reg_mt6885(phys_addr_t, phys_addr_t);
int consys_conninfra_on_power_ctrl_mt6885(unsigned int enable);
int consys_conninfra_wakeup_mt6885(void);

48
drivers/misc/mediatek/connectivity/conninfra/platform/mt6885/mt6885.c
View file

@ -85,7 +85,7 @@ static unsigned int consys_soc_chipid_get(void);
static unsigned int consys_get_hw_ver(void);
static void consys_clock_fail_dump(void);
static int consys_thermal_query(void);
static int consys_power_state(char *buf, unsigned int size);
static int consys_power_state(void);
static int consys_bus_clock_ctrl(enum consys_drv_type, unsigned int, int);
static unsigned long long consys_soc_timestamp_get(void);
static unsigned int consys_adie_detection_mt6885(void);
@ -377,23 +377,23 @@ int consys_thermal_query(void)
}
int consys_power_state(char *buf, unsigned int size)
int consys_power_state(void)
{
const char* osc_str[] = {
"fm ", "gps ", "bgf ", "wf ", "ap2conn ", "conn_thm ", "conn_pta ", "conn_infra_bus "
};
char temp_buf[256] = {'\0'};
char buf[256] = {'\0'};
unsigned int r = CONSYS_REG_READ(CON_REG_HOST_CSR_ADDR + CONN_HOST_CSR_DBG_DUMMY_2);
unsigned int i, buf_len = 0, str_len;
for (i = 0; i < 8; i++) {
str_len = strlen(osc_str[i]);
if ((r & (0x1 << (18 + i))) > 0 && (buf_len + str_len < 256)) {
strncat(temp_buf, osc_str[i], str_len);
strncat(buf, osc_str[i], str_len);
buf_len += str_len;
}
}
pr_info("[%s] [0x%x] %s", __func__, r, temp_buf);
pr_info("[%s] [0x%x] %s", __func__, r, buf);
return 0;
}
@ -412,6 +412,8 @@ int consys_bus_clock_ctrl(enum consys_drv_type drv_type, unsigned int bus_clock,
if (bus_clock & CONNINFRA_BUS_CLOCK_BPLL) {
if (conninfra_bus_clock_bpll_state == 0) {
CONSYS_SET_BIT(CONN_AFE_CTL_BASE_ADDR + CONN_AFE_CTL_RG_DIG_EN_03, (0x1 << 21));
udelay(30);
bpll_switch = true;
}
conninfra_bus_clock_bpll_state |= (0x1 << drv_type);
@ -419,27 +421,12 @@ int consys_bus_clock_ctrl(enum consys_drv_type drv_type, unsigned int bus_clock,
/* Enable WPLL */
if (bus_clock & CONNINFRA_BUS_CLOCK_WPLL) {
if (conninfra_bus_clock_wpll_state == 0) {
CONSYS_SET_BIT(CONN_AFE_CTL_BASE_ADDR + CONN_AFE_CTL_RG_DIG_EN_03, (0x1 << 20));
udelay(50);
wpll_switch = true;
}
conninfra_bus_clock_wpll_state |= (0x1 << drv_type);
}
if (bpll_switch || wpll_switch) {
while (consys_sema_acquire_timeout_mt6885(CONN_SEMA_BUS_CONTROL, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL);
if (bpll_switch) {
CONSYS_SET_BIT(CONN_AFE_CTL_BASE_ADDR + CONN_AFE_CTL_RG_DIG_EN_03, (0x1 << 21));
udelay(30);
}
if (wpll_switch) {
CONSYS_SET_BIT(CONN_AFE_CTL_BASE_ADDR + CONN_AFE_CTL_RG_DIG_EN_03, (0x1 << 20));
udelay(50);
}
consys_sema_release_mt6885(CONN_SEMA_BUS_CONTROL);
}
pr_info("drv=[%d] conninfra_bus_clock_wpll=[%u]->[%u] %s conninfra_bus_clock_bpll=[%u]->[%u] %s",
drv_type,
wpll_state, conninfra_bus_clock_wpll_state, (wpll_switch ? "enable" : ""),
@ -450,6 +437,7 @@ int consys_bus_clock_ctrl(enum consys_drv_type drv_type, unsigned int bus_clock,
if (bus_clock & CONNINFRA_BUS_CLOCK_WPLL) {
conninfra_bus_clock_wpll_state &= ~(0x1<<drv_type);
if (conninfra_bus_clock_wpll_state == 0) {
CONSYS_CLR_BIT(CONN_AFE_CTL_BASE_ADDR + CONN_AFE_CTL_RG_DIG_EN_03, (0x1 << 20));
wpll_switch = true;
}
}
@ -457,24 +445,10 @@ int consys_bus_clock_ctrl(enum consys_drv_type drv_type, unsigned int bus_clock,
if (bus_clock & CONNINFRA_BUS_CLOCK_BPLL) {
conninfra_bus_clock_bpll_state &= ~(0x1<<drv_type);
if (conninfra_bus_clock_bpll_state == 0) {
CONSYS_CLR_BIT(CONN_AFE_CTL_BASE_ADDR + CONN_AFE_CTL_RG_DIG_EN_03, (0x1 << 21));
bpll_switch = true;
}
}
if (bpll_switch || wpll_switch) {
while (consys_sema_acquire_timeout_mt6885(CONN_SEMA_BUS_CONTROL, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL);
if (wpll_switch) {
CONSYS_CLR_BIT(CONN_AFE_CTL_BASE_ADDR + CONN_AFE_CTL_RG_DIG_EN_03, (0x1 << 20));
}
if (bpll_switch) {
CONSYS_CLR_BIT(CONN_AFE_CTL_BASE_ADDR + CONN_AFE_CTL_RG_DIG_EN_03, (0x1 << 21));
}
consys_sema_release_mt6885(CONN_SEMA_BUS_CONTROL);
}
pr_info("drv=[%d] conninfra_bus_clock_wpll=[%u]->[%u] %s conninfra_bus_clock_bpll=[%u]->[%u] %s",
drv_type,
wpll_state, conninfra_bus_clock_wpll_state, (wpll_switch ? "disable" : ""),

3
drivers/misc/mediatek/connectivity/conninfra/platform/mt6885/mt6885_pos.c
View file

@ -120,8 +120,7 @@ const char* get_spi_sys_name(enum sys_spi_subsystem subsystem)
unsigned int consys_emi_set_remapping_reg_mt6885(
phys_addr_t con_emi_base_addr,
phys_addr_t md_shared_emi_base_addr,
phys_addr_t gps_emi_base_addr)
phys_addr_t md_shared_emi_base_addr)
{
/* EMI Registers remapping */
CONSYS_REG_WRITE_OFFSET_RANGE(CON_REG_HOST_CSR_ADDR + CONN2AP_REMAP_MCU_EMI_BASE_ADDR_OFFSET,

2
drivers/misc/mediatek/connectivity/conninfra/platform/mt6893/include/mt6893_pos.h
View file

@ -7,7 +7,7 @@
#define _PLATFORM_MT6893_POS_H_
unsigned int consys_emi_set_remapping_reg_mt6893(phys_addr_t, phys_addr_t, phys_addr_t);
unsigned int consys_emi_set_remapping_reg_mt6893(phys_addr_t, phys_addr_t);
int consys_conninfra_on_power_ctrl_mt6893(unsigned int enable);
int consys_conninfra_wakeup_mt6893(void);

10
drivers/misc/mediatek/connectivity/conninfra/platform/mt6893/mt6893.c
View file

@ -80,7 +80,7 @@ static unsigned int consys_soc_chipid_get(void);
static unsigned int consys_get_hw_ver(void);
static void consys_clock_fail_dump(void);
static int consys_thermal_query(void);
static int consys_power_state(char *buf, unsigned int size);
static int consys_power_state(void);
static int consys_bus_clock_ctrl(enum consys_drv_type, unsigned int, int);
static unsigned long long consys_soc_timestamp_get(void);
static unsigned int consys_adie_detection_mt6893(void);
@ -427,20 +427,20 @@ int consys_thermal_query(void)
}
int consys_power_state(char *buf, unsigned int size)
int consys_power_state(void)
{
const char* osc_str[] = {
"fm ", "gps ", "bgf ", "wf ", "ap2conn ", "conn_thm ", "conn_pta ", "conn_infra_bus "
};
char temp_buf[256] = {'\0'};
char buf[256] = {'\0'};
int r = CONSYS_REG_READ(CON_REG_HOST_CSR_ADDR + CONN_HOST_CSR_DBG_DUMMY_2);
int i;
for (i = 0; i < 8; i++) {
if ((r & (0x1 << (18 + i))) > 0)
strncat(temp_buf, osc_str[i], strlen(osc_str[i]));
strncat(buf, osc_str[i], strlen(osc_str[i]));
}
pr_info("[%s] [0x%x] %s", __func__, r, temp_buf);
pr_info("[%s] [0x%x] %s", __func__, r, buf);
return 0;
}

2
drivers/misc/mediatek/connectivity/conninfra/platform/mt6893/mt6893_consys_reg.c
View file

@ -641,7 +641,7 @@ unsigned long consys_reg_validate_idx_n_offset(unsigned int idx, unsigned long o
{
unsigned long res;
if (idx >= CONSYS_BASE_ADDR_MAX) {
if (idx < 0 || idx >= CONSYS_BASE_ADDR_MAX) {
pr_warn("ConsysReg failed: No support the base %d\n", idx);
return 0;
}

3
drivers/misc/mediatek/connectivity/conninfra/platform/mt6893/mt6893_emi.c
View file

@ -8,6 +8,9 @@
#include <linux/version.h>
#include <linux/memblock.h>
#include <linux/platform_device.h>
#ifdef CONFIG_MTK_EMI
#include <mt_emi_api.h>
#endif
#include <linux/of_reserved_mem.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0))

9
drivers/misc/mediatek/connectivity/conninfra/platform/mt6893/mt6893_pos.c
View file

@ -100,8 +100,7 @@ static int connsys_a_die_thermal_cal(int efuse_valid, unsigned int efuse);
unsigned int consys_emi_set_remapping_reg_mt6893(
phys_addr_t con_emi_base_addr,
phys_addr_t md_shared_emi_base_addr,
phys_addr_t gps_emi_base_addr)
phys_addr_t md_shared_emi_base_addr)
{
/* EMI Registers remapping */
CONSYS_REG_WRITE_OFFSET_RANGE(CON_REG_HOST_CSR_ADDR + CONN2AP_REMAP_MCU_EMI_BASE_ADDR_OFFSET,
@ -2132,7 +2131,7 @@ static void consys_spi_write_offset_range_nolock(
unsigned int reg_mask;
int ret;
if (subsystem >= SYS_SPI_MAX) {
if (subsystem < 0 || subsystem >= SYS_SPI_MAX) {
pr_notice("%s subsystem %d is invalid\n", __func__, subsystem);
return;
}
@ -2219,7 +2218,7 @@ int consys_adie_top_ck_en_on_mt6893(enum consys_adie_ctl_type type)
unsigned int status;
int ret;
if (type < CONNSYS_ADIE_CTL_HOST_BT) {
if (type >= CONNSYS_ADIE_CTL_MAX || type < CONNSYS_ADIE_CTL_HOST_BT) {
pr_err("[%s] invalid parameter(%d)\n", __func__, type);
return -1;
}
@ -2247,7 +2246,7 @@ int consys_adie_top_ck_en_off_mt6893(enum consys_adie_ctl_type type)
unsigned int status;
int ret = 0;
if (type >= CONNSYS_ADIE_CTL_MAX) {
if (type >= CONNSYS_ADIE_CTL_MAX || type < CONNSYS_ADIE_CTL_HOST_BT) {
pr_err("[%s] invalid parameter(%d)\n", __func__, type);
return -1;
}

1
drivers/misc/mediatek/connectivity/conninfra/platform/mt6895/include/mt6895.h
View file

@ -48,6 +48,5 @@ int consys_platform_spm_conn_ctrl_mt6895(unsigned int enable);
int consys_co_clock_type_mt6895(void);
void update_thermal_data_mt6895(struct consys_plat_thermal_data_mt6895* input);
unsigned int consys_get_adie_chipid_mt6895(void);
int consys_pre_cal_restore_mt6895(void);
#endif /* _PLATFORM_MT6895_H_ */

2
drivers/misc/mediatek/connectivity/conninfra/platform/mt6895/include/mt6895_consys_reg.h
View file

@ -68,7 +68,5 @@ extern struct consys_base_addr conn_reg_mt6895;
#define CONN_REG_SPM_ADDR conn_reg_mt6895.reg_base_addr[SPM_BASE_INDEX].vir_addr
#define CONN_REG_TOP_RGU_ADDR conn_reg_mt6895.reg_base_addr[TOP_RGU_BASE_INDEX].vir_addr
int consys_check_conninfra_on_domain_mt6895(void);
#endif /* _PLATFORM_MT6895_CONSYS_REG_H_ */

49
drivers/misc/mediatek/connectivity/conninfra/platform/mt6895/include/mt6895_debug_gen.h
View file

@ -11,7 +11,7 @@
* It should not be modified by hand.
*
* Reference debug file,
* - [Lxxxn]connsys_power_debug.xlsx (Modified date: 2021-12-28)
* - [Lxxxn]connsys_power_debug.xlsx (Modified date: 2021-08-18)
* - [Lxxxn]conn_infra_bus_debug_ctrl.xlsx (Modified date: 2021-10-14)
*/
@ -80,27 +80,11 @@ void consys_print_bus_slpprot_debug_dbg_level_0_mt6895_debug_gen(
/* Base: CONSYS_DBG_GEN_SRCLKENRC_BASE_ADDR (0x1C00_D000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_SRCLKENRC_BASE_ADDR 0x1C00D000
#define CONSYS_DBG_GEN_FSM_STA_0_OFFSET_ADDR 0x100
#define CONSYS_DBG_GEN_CMD_STA_0_OFFSET_ADDR 0x104
#define CONSYS_DBG_GEN_CMD_STA_1_OFFSET_ADDR 0x108
#define CONSYS_DBG_GEN_SPI_STA_0_OFFSET_ADDR 0x10C
#define CONSYS_DBG_GEN_PI_PO_STA_0_OFFSET_ADDR 0x110
#define CONSYS_DBG_GEN_M00_REQ_STA_0_OFFSET_ADDR 0x114
#define CONSYS_DBG_GEN_M01_REQ_STA_0_OFFSET_ADDR 0x118
#define CONSYS_DBG_GEN_M02_REQ_STA_0_OFFSET_ADDR 0x11C
#define CONSYS_DBG_GEN_M03_REQ_STA_0_OFFSET_ADDR 0x120
#define CONSYS_DBG_GEN_M04_REQ_STA_0_OFFSET_ADDR 0x124
#define CONSYS_DBG_GEN_M05_REQ_STA_0_OFFSET_ADDR 0x128
#define CONSYS_DBG_GEN_M06_REQ_STA_0_OFFSET_ADDR 0x12C
#define CONSYS_DBG_GEN_M07_REQ_STA_0_OFFSET_ADDR 0x130
#define CONSYS_DBG_GEN_M08_REQ_STA_0_OFFSET_ADDR 0x134
#define CONSYS_DBG_GEN_M09_REQ_STA_0_OFFSET_ADDR 0x138
#define CONSYS_DBG_GEN_M10_REQ_STA_0_OFFSET_ADDR 0x13C
#define CONSYS_DBG_GEN_M11_REQ_STA_0_OFFSET_ADDR 0x140
#define CONSYS_DBG_GEN_M12_REQ_STA_0_OFFSET_ADDR 0x144
#define CONSYS_DBG_GEN_M13_REQ_STA_0_OFFSET_ADDR 0x148
#define CONSYS_DBG_GEN_DEBUG_STA_0_OFFSET_ADDR 0x14C
#define CONSYS_DBG_GEN_SPMI_P_STA_0_OFFSET_ADDR 0x150
#define CONSYS_DBG_GEN_DEBUG_TRACE_0_LSB_OFFSET_ADDR 0x700
#define CONSYS_DBG_GEN_DEBUG_TRACE_0_MSB_OFFSET_ADDR 0x704
#define CONSYS_DBG_GEN_DEBUG_TRACE_1_LSB_OFFSET_ADDR 0x708
@ -146,20 +130,6 @@ void consys_print_bus_slpprot_debug_dbg_level_0_mt6895_debug_gen(
#define CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR 0xa04
#define CONSYS_DBG_GEN_CONNSYS_PWR_STATES_OFFSET_ADDR 0xA10
/*************************************************************************************/
/* Base: CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR (0x1802_3000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR 0x18023000
#define CONSYS_DBG_GEN_CONN_INFRA_MONFLAG_OUT_OFFSET_ADDR 0x200
#define CONSYS_DBG_GEN_CONN_INFRA_BUS_TIMEOUT_IRQ_OFFSET_ADDR 0x400
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_BUS_DBG_OUT_OFFSET_ADDR 0x404
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_BUS_DBG_SEL_OFFSET_ADDR 0x408
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUGSYS_CTRL_OFFSET_ADDR 0x40c
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_INFO_OFFSET_ADDR 0x410
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_ADDR_OFFSET_ADDR 0x414
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_WDATA_OFFSET_ADDR 0x418
#define CONSYS_DBG_GEN_CONN_INFRA_VON_BUS_DEBUG_INFO_OFFSET_ADDR 0x41c
/*************************************************************************************/
/* Base: CONN_CFG_BASE (0x1801_1000) */
/*************************************************************************************/
@ -208,14 +178,17 @@ void consys_print_bus_slpprot_debug_dbg_level_0_mt6895_debug_gen(
#define CONSYS_DBG_GEN_CONN_INFRA_SYSRAM_BASE_OFFSET_ADDR 0x18050000
/*************************************************************************************/
/* Base: CONN_RF_SPI_MST_REG_BASE (0x1804_2000) */
/* Base: CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR (0x1802_3000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_SPI_STA_OFFSET_ADDR 0x0
#define CONSYS_DBG_GEN_SPI_CRTL_OFFSET_ADDR 0x4
#define CONSYS_DBG_GEN_SPI_TOP_ADDR_OFFSET_ADDR 0x50
#define CONSYS_DBG_GEN_SPI_TOP_WDAT_OFFSET_ADDR 0x54
#define CONSYS_DBG_GEN_SPI_TOP_RDAT_OFFSET_ADDR 0x58
#define CONSYS_DBG_GEN_SPI_HSCK_CTL_OFFSET_ADDR 0x108
#define CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR 0x18023000
#define CONSYS_DBG_GEN_CONN_INFRA_BUS_TIMEOUT_IRQ_OFFSET_ADDR 0x400
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_BUS_DBG_OUT_OFFSET_ADDR 0x404
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_BUS_DBG_SEL_OFFSET_ADDR 0x408
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUGSYS_CTRL_OFFSET_ADDR 0x40c
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_INFO_OFFSET_ADDR 0x410
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_ADDR_OFFSET_ADDR 0x414
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_WDATA_OFFSET_ADDR 0x418
#define CONSYS_DBG_GEN_CONN_INFRA_VON_BUS_DEBUG_INFO_OFFSET_ADDR 0x41c
/*************************************************************************************/
/* Base: CONN_BUS_CR_ON_BASE (0x1800_e000) */

1
drivers/misc/mediatek/connectivity/conninfra/platform/mt6895/include/mt6895_pmic.h
View file

@ -27,7 +27,6 @@
#define MT6363_RG_LDO_VRFIO18_HW0_OP_MODE_ADDR 0x1bda
#define MT6363_RG_LDO_VCN13_MON_ADDR 0x1d0b
#define MT6363_RG_LDO_VCN13_VOSEL_SLEEP_ADDR 0x1d0d
#define MT6363_RG_LDO_VCN13_RC6_OP_EN_ADDR 0x1d14
#define MT6363_RG_LDO_VCN13_RC6_OP_CFG_ADDR 0x1d17
#define MT6363_RG_LDO_VCN13_RC6_OP_MODE_ADDR 0x1d1a

2
drivers/misc/mediatek/connectivity/conninfra/platform/mt6895/include/mt6895_pos.h
View file

@ -8,7 +8,7 @@
#include <linux/types.h>
unsigned int consys_emi_set_remapping_reg_mt6895(phys_addr_t, phys_addr_t, phys_addr_t);
unsigned int consys_emi_set_remapping_reg_mt6895(phys_addr_t, phys_addr_t);
int consys_conninfra_on_power_ctrl_mt6895(unsigned int enable);
int consys_conninfra_wakeup_mt6895(void);

10
drivers/misc/mediatek/connectivity/conninfra/platform/mt6895/include/mt6895_pos_gen.h
View file

@ -11,9 +11,9 @@
* It should not be modified by hand.
*
* Reference POS file,
* - Pxxxxn_power_on_sequence_20211124.xlsx
* - Pxxxxn_conn_infra_sub_task_211117.xlsx
* - conn_infra_cmdbt_instr_autogen_20220216.txt
* - Pxxxxn_power_on_sequence_20210913.xlsx
* - Pxxxxn_conn_infra_sub_task_210811.xlsx
* - conn_infra_cmdbt_instr_autogen_20210902.txt
*/
@ -28,7 +28,6 @@ int consys_polling_chipid_mt6895_gen(unsigned int *pconsys_ver_id);
unsigned int consys_emi_set_remapping_reg_mt6895_gen(
phys_addr_t con_emi_base_addr,
phys_addr_t md_shared_emi_base_addr,
phys_addr_t gps_emi_base_addr,
unsigned int emi_base_addr_offset);
void consys_init_conninfra_sysram_mt6895_gen(void);
void connsys_get_d_die_efuse_mt6895_gen(unsigned int *p_d_die_efuse);
@ -74,7 +73,6 @@ int connsys_a_die_cfg_PART2_mt6895_gen(unsigned int hw_ver_id);
int connsys_a_die_switch_to_conn_mode_mt6895_gen(void);
void connsys_wt_slp_top_power_saving_ctrl_adie6637_sleep_mode_1_mt6895_gen(void);
void connsys_wt_slp_top_power_saving_ctrl_adie6637_sleep_mode_2_mt6895_gen(void);
void connsys_wt_slp_top_power_saving_ctrl_adie6637_sleep_mode_3_mt6895_gen(void);
void connsys_wt_slp_top_power_saving_ctrl_adie6637_mt6895_gen(
unsigned int hw_version,
unsigned int sleep_mode);
@ -168,7 +166,6 @@ int consys_conninfra_sleep_mt6895_gen(void);
#define CONSYS_GEN_CONN_INFRA_CONN2AP_EMI_PATH_ADDR_END_OFFSET_ADDR 0x74
#define CONSYS_GEN_CONN2AP_REMAP_MCU_EMI_BASE_ADDR_OFFSET_ADDR 0x354
#define CONSYS_GEN_CONN2AP_REMAP_MD_SHARE_EMI_BASE_ADDR_OFFSET_ADDR 0x35C
#define CONSYS_GEN_CONN2AP_REMAP_GPS_EMI_BASE_ADDR_OFFSET_ADDR 0x360
#define CONSYS_GEN_CONN2AP_REMAP_WF_PERI_BASE_ADDR_OFFSET_ADDR 0x364
#define CONSYS_GEN_CONN2AP_REMAP_BT_PERI_BASE_ADDR_OFFSET_ADDR 0x368
#define CONSYS_GEN_CONN2AP_REMAP_GPS_PERI_BASE_ADDR_OFFSET_ADDR 0x36C
@ -320,7 +317,6 @@ int consys_conninfra_sleep_mt6895_gen(void);
/****************************************************************************************************/
/* Base: CONN_BUS_CR_ON_BASE (0x1800_E000) */
/****************************************************************************************************/
#define CONSYS_GEN_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_OFFSET_ADDR 0x24
#define CONSYS_GEN_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_OFFSET_ADDR 0x38
#define CONSYS_GEN_CONN_VON_BUS_DCM_CTL_1_OFFSET_ADDR 0x104
#define CONSYS_GEN_CONN_OFF_BUS_DCM_CTL_1_OFFSET_ADDR 0x110

356
drivers/misc/mediatek/connectivity/conninfra/platform/mt6895/mt6895.c
View file

@ -15,13 +15,6 @@
#include <connectivity_build_in_adapter.h>
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
#include <oplus_conn_event.h>
#include <linux/string.h>
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
#include "osal.h"
#include "conninfra.h"
#include "conninfra_conf.h"
@ -47,7 +40,6 @@
********************************************************************************
*/
#define PLATFORM_SOC_CHIP 0x6895
#define PRINT_THERMAL_LOG_THRESHOLD 60
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
@ -63,18 +55,7 @@
* D A T A T Y P E S
********************************************************************************
*/
struct rf_cr_backup_data {
unsigned int addr;
unsigned int value1;
unsigned int value2;
};
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
static char mUevent[256] = {'\0'};
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
@ -88,16 +69,12 @@ static int consys_thermal_query_mt6895(void);
/* Power state relative */
static int consys_enable_power_dump_mt6895(void);
static int consys_reset_power_state_mt6895(void);
static int consys_reset_power_state(void);
static int consys_power_state_dump_mt6895(char *buf, unsigned int size);
static int consys_power_state_dump_mt6895(void);
static unsigned long long consys_soc_timestamp_get_mt6895(void);
static unsigned int consys_adie_detection_mt6895(void);
static void consys_set_mcu_control_mt6895(int type, bool onoff);
static int consys_pre_cal_backup_mt6895(unsigned int offset, unsigned int size);
static int consys_pre_cal_clean_data_mt6895(void);
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
@ -141,14 +118,11 @@ struct consys_hw_ops_struct g_consys_hw_ops_mt6895 = {
.consys_plt_thermal_query = consys_thermal_query_mt6895,
.consys_plt_enable_power_dump = consys_enable_power_dump_mt6895,
.consys_plt_reset_power_state = consys_reset_power_state_mt6895,
.consys_plt_reset_power_state = consys_power_state_dump_mt6895,
.consys_plt_power_state = consys_power_state_dump_mt6895,
.consys_plt_soc_timestamp_get = consys_soc_timestamp_get_mt6895,
.consys_plt_adie_detection = consys_adie_detection_mt6895,
.consys_plt_set_mcu_control = consys_set_mcu_control_mt6895,
.consys_plt_pre_cal_backup = consys_pre_cal_backup_mt6895,
.consys_plt_pre_cal_clean_data = consys_pre_cal_clean_data_mt6895,
};
extern struct consys_hw_ops_struct g_consys_hw_ops_mt6895;
@ -169,12 +143,6 @@ const struct conninfra_plat_data mt6895_plat_data = {
};
static struct consys_plat_thermal_data_mt6895 g_consys_plat_therm_data;
/* For calibration backup/restore */
static struct rf_cr_backup_data *mt6637_backup_data = NULL;
static unsigned int mt6637_backup_cr_number = 0;
extern phys_addr_t gConEmiPhyBase;
static void __iomem *ccif_wf2ap_sw_irq_b_addr;
static void __iomem *ccif_bgf2ap_sw_irq_b_addr;
int consys_co_clock_type_mt6895(void)
{
@ -190,6 +158,8 @@ int consys_co_clock_type_mt6895(void)
pr_notice("[%s] Get conf fail", __func__);
return -1;
}
pr_info("[%s] conf->tcxo_gpio=%d conn_hw_env.tcxo_support=%d",
__func__, conf->tcxo_gpio, conn_hw_env.tcxo_support);
if (conf->tcxo_gpio != 0 || conn_hw_env.tcxo_support) {
if (conf->co_clock_flag == 3)
@ -205,8 +175,7 @@ int consys_co_clock_type_mt6895(void)
clock_type = CONNSYS_CLOCK_SCHEMATIC_52M_COTMS;
}
}
pr_info("[%s] conf->tcxo_gpio=%d conn_hw_env.tcxo_support=%d, %s",
__func__, conf->tcxo_gpio, conn_hw_env.tcxo_support, clock_name[clock_type]);
pr_info("%s: %s\n", __func__, clock_name[clock_type]);
return clock_type;
}
@ -216,13 +185,6 @@ int consys_clk_get_from_dts_mt6895(struct platform_device *pdev)
pm_runtime_enable(&pdev->dev);
dev_pm_syscore_device(&pdev->dev, true);
/* remap these two CR for print irq status */
if (!ccif_wf2ap_sw_irq_b_addr)
ccif_wf2ap_sw_irq_b_addr = ioremap(0x1803C008, 0x4);
if (!ccif_bgf2ap_sw_irq_b_addr)
ccif_bgf2ap_sw_irq_b_addr = ioremap(0x1803E008, 0x4);
return 0;
}
@ -240,18 +202,26 @@ int consys_platform_spm_conn_ctrl_mt6895(unsigned int enable)
ret = pm_runtime_get_sync(&(pdev->dev));
if (ret)
pr_info("pm_runtime_get_sync() fail(%d)\n", ret);
else
pr_info("pm_runtime_get_sync() CONSYS ok\n");
ret = device_init_wakeup(&(pdev->dev), true);
if (ret)
pr_info("device_init_wakeup(true) fail.\n");
else
pr_info("device_init_wakeup(true) CONSYS ok\n");
} else {
ret = device_init_wakeup(&(pdev->dev), false);
if (ret)
pr_info("device_init_wakeup(false) fail.\n");
else
pr_info("device_init_wakeup(false) CONSYS ok\n");
ret = pm_runtime_put_sync(&(pdev->dev));
if (ret)
pr_info("pm_runtime_put_sync() fail.\n");
else
pr_info("pm_runtime_put_sync() CONSYS ok\n");
}
return ret;
}
@ -289,7 +259,7 @@ int consys_enable_power_dump_mt6895(void)
return 0;
}
int consys_reset_power_state(void)
int consys_reset_power_state_mt6895(void)
{
/* Clear data and disable stop */
/* I. Clear
@ -361,43 +331,6 @@ static inline void __sleep_count_trigger_read(void)
}
static void consys_print_irq_status(void)
{
unsigned int val_1, val_2, val_3, val_4;
val_1 = CONSYS_REG_READ(CONN_REG_CONN_HOST_CSR_TOP_ADDR + 0x38) & 0x1;
val_2 = CONSYS_REG_READ(CONN_REG_CONN_HOST_CSR_TOP_ADDR + 0x34) & 0x1;
val_3 = CONSYS_REG_READ(CONN_REG_CONN_HOST_CSR_TOP_ADDR + 0x3C) & 0x2;
val_4 = CONSYS_REG_READ(CONN_REG_CONN_HOST_CSR_TOP_ADDR + 0x44) & 0x1;
// conn_bgf_hif_on_host_int_b
// (~(0x1806_0038[0] & 0x1806_0034[0])) & (~(0x1806_0038[1] & 0x1806_003C[0]))
if ((val_1 && val_2) || (val_1 && val_3))
pr_info("conn_bgf_hif_on_host_int_b %x %x %x", val_1, val_2, val_3);
// conn_gps_hif_on_host_int_b
// ~ (0x1806_0038[0] & 0x1806_0044[0])
if (val_1 && val_4)
pr_info("conn_gps_hif_on_host_int_b %x %x", val_1, val_4);
if (consys_check_conninfra_on_domain_mt6895() == 0)
return;
// ccif_wf2ap_sw_irq_b 0x1803_C008[7:0]
// ccif_bgf2ap_sw_irq_b 0x1803_E008[7:0]
if (ccif_wf2ap_sw_irq_b_addr) {
val_1 = CONSYS_REG_READ(ccif_wf2ap_sw_irq_b_addr) & 0xFF;
if (val_1 > 0)
pr_info("ccif_wf2ap_sw_irq_b %x", val_1);
}
if (ccif_bgf2ap_sw_irq_b_addr) {
val_1 = CONSYS_REG_READ(ccif_bgf2ap_sw_irq_b_addr) & 0xFF;
if (val_1 > 0)
pr_info("ccif_bgf2ap_sw_irq_b %x", val_1);
}
}
static void consys_power_state(void)
{
unsigned int i, str_len;
@ -415,28 +348,17 @@ static void consys_power_state(void)
for (i = 0; i < 15; i++) {
str_len = strlen(osc_str[i]);
if ((r & (0x1 << (1 + i))) > 0 && (buf_len + str_len < 256)) {
strncat(buf, osc_str[i], str_len);
buf_len += str_len;
}
}
if (r & 0xFFFF) {
pr_info("[%s] [0x%x] %s", __func__, r, buf);
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
snprintf(mUevent, sizeof(mUevent), "consys=power_state:%s;", buf);
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
}
consys_print_irq_status();
pr_info("[%s] [0x%x] %s", __func__, r, buf);
}
static int consys_power_state_dump(char *buf, unsigned int size, int print_log)
int consys_power_state_dump_mt6895(void)
{
#define POWER_STATE_BUF_SIZE 256
#define CONN_32K_TICKS_PER_SEC (32768)
#define CONN_TICK_TO_SEC(TICK) (TICK / CONN_32K_TICKS_PER_SEC)
static u64 round = 0;
static u64 t_conninfra_sleep_cnt = 0, t_conninfra_sleep_time = 0;
static u64 t_wf_sleep_cnt = 0, t_wf_sleep_time = 0;
@ -446,9 +368,6 @@ static int consys_power_state_dump(char *buf, unsigned int size, int print_log)
unsigned int wf_sleep_cnt, wf_sleep_time;
unsigned int bt_sleep_cnt, bt_sleep_time;
unsigned int gps_sleep_cnt, gps_sleep_time;
char temp_buf[POWER_STATE_BUF_SIZE];
char *buf_p = temp_buf;
int buf_sz = POWER_STATE_BUF_SIZE;
/* Sleep count */
/* 1. Setup read select: 0x1806_0380[3:1]
@ -470,10 +389,6 @@ static int consys_power_state_dump(char *buf, unsigned int size, int print_log)
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_COUNTER_ADDR);
t_conninfra_sleep_time += conninfra_sleep_time;
t_conninfra_sleep_cnt += conninfra_sleep_cnt;
/* Wait 60 us to make sure the duration to next write to SLP_COUNTER_RD_TRIGGER is
* long enough.
*/
udelay(60);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_CTL_HOST_SLP_COUNTER_SEL,
@ -485,7 +400,6 @@ static int consys_power_state_dump(char *buf, unsigned int size, int print_log)
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_COUNTER_ADDR);
t_wf_sleep_time += wf_sleep_time;
t_wf_sleep_cnt += wf_sleep_cnt;
udelay(60);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_CTL_HOST_SLP_COUNTER_SEL,
@ -497,7 +411,6 @@ static int consys_power_state_dump(char *buf, unsigned int size, int print_log)
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_COUNTER_ADDR);
t_bt_sleep_time += bt_sleep_time;
t_bt_sleep_cnt += bt_sleep_cnt;
udelay(60);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_CTL_HOST_SLP_COUNTER_SEL,
@ -510,106 +423,28 @@ static int consys_power_state_dump(char *buf, unsigned int size, int print_log)
t_gps_sleep_time += gps_sleep_time;
t_gps_sleep_cnt += gps_sleep_cnt;
if (print_log > 0 && buf != NULL && size > 0) {
buf_p = buf;
buf_sz = size;
}
if (print_log > 0 && snprintf(buf_p, buf_sz,"[consys_power_state][round:%llu]"
"conninfra:%u.%03u,%u;wf:%u.%03u,%u;bt:%u.%03u,%u;gps:%u.%03u,%u;"
"[total]conninfra:%llu.%03llu,%llu;wf:%llu.%03llu,%llu;"
"bt:%llu.%03llu,%llu;gps:%llu.%03llu,%llu;",
pr_info("[consys_power_state][round:%llu]conninfra:%u,%u;wf:%u,%u;bt:%u,%u;gps:%u,%u;",
round,
CONN_TICK_TO_SEC(conninfra_sleep_time),
CONN_TICK_TO_SEC((conninfra_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
conninfra_sleep_cnt,
CONN_TICK_TO_SEC(wf_sleep_time),
CONN_TICK_TO_SEC((wf_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
wf_sleep_cnt,
CONN_TICK_TO_SEC(bt_sleep_time),
CONN_TICK_TO_SEC((bt_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
bt_sleep_cnt,
CONN_TICK_TO_SEC(gps_sleep_time),
CONN_TICK_TO_SEC((gps_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
gps_sleep_cnt,
CONN_TICK_TO_SEC(t_conninfra_sleep_time),
CONN_TICK_TO_SEC((t_conninfra_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_conninfra_sleep_cnt,
CONN_TICK_TO_SEC(t_wf_sleep_time),
CONN_TICK_TO_SEC((t_wf_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_wf_sleep_cnt,
CONN_TICK_TO_SEC(t_bt_sleep_time),
CONN_TICK_TO_SEC((t_bt_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_bt_sleep_cnt,
CONN_TICK_TO_SEC(t_gps_sleep_time),
CONN_TICK_TO_SEC((t_gps_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_gps_sleep_cnt) > 0) {
pr_info("%s", buf_p);
}
conninfra_sleep_time, conninfra_sleep_cnt,
wf_sleep_time, wf_sleep_cnt,
bt_sleep_time, bt_sleep_cnt,
gps_sleep_time, gps_sleep_cnt);
pr_info("[consys_power_state][total]conninfra:%llu,%llu;wf:%llu,%llu;bt:%llu,%llu;gps:%llu,%llu;",
t_conninfra_sleep_time, t_conninfra_sleep_cnt,
t_wf_sleep_time, t_wf_sleep_cnt,
t_bt_sleep_time, t_bt_sleep_cnt,
t_gps_sleep_time, t_gps_sleep_cnt);
/* Power state */
if (print_log > 0) {
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
memset(mUevent, '\0', sizeof(mUevent));
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
consys_power_state();
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
if (strlen(mUevent) > 0) {
snprintf(&(mUevent[strlen(mUevent)]), sizeof(mUevent)-strlen(mUevent),
"conninfra:%u.%03u,%u;wf:%u.%03u,%u;bt:%u.%03u,%u;gps:%u.%03u,%u;"
"[total]conninfra:%llu.%03llu,%llu;wf:%llu.%03llu,%llu;"
"bt:%llu.%03llu,%llu;gps:%llu.%03llu,%llu;",
CONN_TICK_TO_SEC(conninfra_sleep_time),
CONN_TICK_TO_SEC((conninfra_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
conninfra_sleep_cnt,
CONN_TICK_TO_SEC(wf_sleep_time),
CONN_TICK_TO_SEC((wf_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
wf_sleep_cnt,
CONN_TICK_TO_SEC(bt_sleep_time),
CONN_TICK_TO_SEC((bt_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
bt_sleep_cnt,
CONN_TICK_TO_SEC(gps_sleep_time),
CONN_TICK_TO_SEC((gps_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
gps_sleep_cnt,
CONN_TICK_TO_SEC(t_conninfra_sleep_time),
CONN_TICK_TO_SEC((t_conninfra_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_conninfra_sleep_cnt,
CONN_TICK_TO_SEC(t_wf_sleep_time),
CONN_TICK_TO_SEC((t_wf_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_wf_sleep_cnt,
CONN_TICK_TO_SEC(t_bt_sleep_time),
CONN_TICK_TO_SEC((t_bt_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_bt_sleep_cnt,
CONN_TICK_TO_SEC(t_gps_sleep_time),
CONN_TICK_TO_SEC((t_gps_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_gps_sleep_cnt);
oplusConnSendUevent(mUevent);
}
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
}
consys_power_state();
round++;
/* reset after sleep time is accumulated. */
consys_reset_power_state();
consys_reset_power_state_mt6895();
return 0;
}
int consys_reset_power_state_mt6895(void)
{
return consys_power_state_dump(NULL, 0, 0);
}
int consys_power_state_dump_mt6895(char *buf, unsigned int size)
{
return consys_power_state_dump(buf, size, 1);
}
unsigned int consys_get_hw_ver_mt6895(void)
{
return CONN_HW_VER;
@ -631,9 +466,10 @@ static int calculate_thermal_temperature(int y)
t = (y - (data->thermal_b == 0 ? 0x38 : data->thermal_b)) *
(data->slop_molecule + 1866) / 1000 + const_offset;
if (t > PRINT_THERMAL_LOG_THRESHOLD)
pr_info("y=[%d] b=[%d] constOffset=[%d] [%d] [%d] => t=[%d]\n",
y, data->thermal_b, const_offset, data->slop_molecule, data->offset, t);
pr_info("y=[%d] b=[%d] constOffset=[%d] [%d] [%d] => t=[%d]\n",
y, data->thermal_b, const_offset, data->slop_molecule, data->offset,
t);
return t;
}
@ -698,10 +534,10 @@ int consys_thermal_query_mt6895(void)
CONSYS_REG_READ(CONN_REG_CONN_THERM_CTL_ADDR + thermal_dump_crs[i])) >= 0)
strncat(tmp_buf, tmp, strlen(tmp));
}
pr_info("[%s] efuse:[0x%08x][0x%08x][0x%08x][0x%08x] thermal dump: %s",
__func__, efuse0, efuse1, efuse2, efuse3, tmp_buf);
res = calculate_thermal_temperature(cal_val);
if (res > PRINT_THERMAL_LOG_THRESHOLD)
pr_info("[%s] efuse:[0x%08x][0x%08x][0x%08x][0x%08x] thermal dump: %s",
__func__, efuse0, efuse1, efuse2, efuse3, tmp_buf);
/* GPT2 disable */
CONSYS_REG_WRITE(addr + CONN_GPT2_CTRL_AP_EN, 0);
@ -767,123 +603,3 @@ static void consys_set_mcu_control_mt6895(int type, bool onoff)
CONSYS_CLR_BIT(CONN_INFRA_SYSRAM_SW_CR_MCU_LOG_CONTROL, (0x1 << type));
}
}
static int consys_pre_cal_backup_mt6895(unsigned int offset, unsigned int size)
{
void __iomem* vir_addr = 0;
unsigned int expected_size = 0;
pr_info("[%s] emi base=0x%x offset=0x%x size=%d", __func__, gConEmiPhyBase, offset, size);
if ((size == 0) || ((offset & 0x3) != 0x0))
return 1;
if (mt6637_backup_data != NULL) {
kfree(mt6637_backup_data);
mt6637_backup_data = NULL;
}
/* Read CR number from EMI */
vir_addr = ioremap(gConEmiPhyBase + offset, 4);
if (vir_addr == NULL) {
pr_err("[%s] ioremap CR number fail", __func__);
return -ENOMEM;
}
mt6637_backup_cr_number = readl(vir_addr);
iounmap(vir_addr);
expected_size = sizeof(struct rf_cr_backup_data)*mt6637_backup_cr_number + 4;
if (size < expected_size) {
pr_err("[%s] cr number=%d, expected_size=0x%x size=0x%x", __func__, mt6637_backup_cr_number, expected_size, size);
mt6637_backup_cr_number = 0;
return 1;
}
mt6637_backup_data =
kmalloc(
sizeof(struct rf_cr_backup_data)*mt6637_backup_cr_number,
GFP_KERNEL);
if (mt6637_backup_data == NULL) {
pr_err("[%s] allocate fail");
return -ENOMEM;
}
vir_addr = ioremap(gConEmiPhyBase + offset + 4,
sizeof(struct rf_cr_backup_data)*mt6637_backup_cr_number);
if (vir_addr == NULL) {
pr_err("[%s] ioremap data fail", __func__);
return -ENOMEM;
}
memcpy_fromio(mt6637_backup_data, vir_addr,
sizeof(struct rf_cr_backup_data)*mt6637_backup_cr_number);
iounmap(vir_addr);
return 0;
}
int consys_pre_cal_restore_mt6895(void)
{
int i;
if (mt6637_backup_cr_number == 0 || mt6637_backup_data == NULL) {
pr_info("[%s] mt6637_backup_cr_number=%d mt6637_backup_data=%x",
__func__, mt6637_backup_cr_number, mt6637_backup_data);
return 1;
}
pr_info("[%s] mt6637_backup_cr_number=%d mt6637_backup_data=%x",
__func__, mt6637_backup_cr_number, mt6637_backup_data);
/* Acquire semaphore */
if (consys_sema_acquire_timeout_mt6895(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL) {
pr_err("[%s] Require semaphore fail\n", __func__);
return CONNINFRA_SPI_OP_FAIL;
}
/* Enable a-die top_ck en */
connsys_adie_top_ck_en_ctl_mt6895(true);
/* Enable WF clock
* ATOP 0xb04 0xfe000000
* ATOP 0xb08 0xe0000000
* ATOP 0xa04 0xffffffff
* ATOP 0xaf4 0xffffffff
*/
consys_spi_write_nolock_mt6895(SYS_SPI_TOP, 0xb04, 0xfe000000);
consys_spi_write_nolock_mt6895(SYS_SPI_TOP, 0xb08, 0xe0000000);
consys_spi_write_nolock_mt6895(SYS_SPI_TOP, 0xa04, 0xffffffff);
consys_spi_write_nolock_mt6895(SYS_SPI_TOP, 0xaf4, 0xffffffff);
/* Write CR back, SYS_SPI_WF & SYS_SPI_WF1 */
for (i = 0; i < mt6637_backup_cr_number; i++) {
consys_spi_write_nolock_mt6895(
SYS_SPI_WF,
mt6637_backup_data[i].addr,
mt6637_backup_data[i].value1);
}
for (i = 0; i < mt6637_backup_cr_number; i++) {
consys_spi_write_nolock_mt6895(
SYS_SPI_WF1,
mt6637_backup_data[i].addr,
mt6637_backup_data[i].value2);
}
/* Disable WF clock
* ATOP 0xb04 0x88000000
* ATOP 0xb08 0x00000000
* ATOP 0xa04 0x00000000
* ATOP 0xaf4 0x00000000
*/
consys_spi_write_nolock_mt6895(SYS_SPI_TOP, 0xb04, 0x88000000);
consys_spi_write_nolock_mt6895(SYS_SPI_TOP, 0xb08, 0x00000000);
consys_spi_write_nolock_mt6895(SYS_SPI_TOP, 0xa04, 0x00000000);
consys_spi_write_nolock_mt6895(SYS_SPI_TOP, 0xaf4, 0x00000000);
/* Release semaphore */
consys_sema_release_mt6895(CONN_SEMA_RFSPI_INDEX);
/* Disable a-die top ck en */
connsys_adie_top_ck_en_ctl_mt6895(false);
return 0;
}
static int consys_pre_cal_clean_data_mt6895(void)
{
if (mt6637_backup_data != NULL) {
kfree(mt6637_backup_data);
mt6637_backup_data = NULL;
}
mt6637_backup_cr_number = 0;
return 0;
}

46
drivers/misc/mediatek/connectivity/conninfra/platform/mt6895/mt6895_consys_reg.c
View file

@ -18,7 +18,7 @@
#include "osal.h"
#include "mt6895_pmic.h"
#define CONSYS_DUMP_BUF_SIZE 800
#define LOG_TMP_BUF_SZ 256
static int consys_reg_init(struct platform_device *pdev);
static int consys_reg_deinit(void);
@ -40,7 +40,6 @@ struct consys_reg_mng_ops g_dev_consys_reg_ops_mt6895 = {
};
static struct conn_debug_info_mt6895 *debug_info;
static char *debug_buf;
static const char* consys_base_addr_index_to_str[CONSYS_BASE_ADDR_MAX] = {
"infracfg_ao",
@ -76,16 +75,15 @@ int consys_is_consys_reg(unsigned int addr)
return 0;
}
#define CONSYS_DUMP_BUF_SIZE 512
static void consys_print_log(const char *title, struct conn_debug_info_mt6895 *info)
{
char buf[CONSYS_DUMP_BUF_SIZE];
char temp[13];
int i;
if (debug_buf == NULL)
return;
temp[0] = '\0';
if (snprintf(debug_buf, CONSYS_DUMP_BUF_SIZE, "%s", title) < 0) {
if (snprintf(buf, CONSYS_DUMP_BUF_SIZE, "%s", title) < 0) {
pr_notice("%s snprintf failed\n", __func__);
return;
}
@ -95,12 +93,9 @@ static void consys_print_log(const char *title, struct conn_debug_info_mt6895 *i
pr_notice("%s snprintf failed\n", __func__);
return;
}
if (strlen(debug_buf) + strlen(temp) < CONSYS_DUMP_BUF_SIZE)
strncat(debug_buf, temp, strlen(temp) + 1);
else
pr_notice("%s debug_buf len is not enough\n", __func__);
strncat(buf, temp, strlen(temp) + 1);
}
pr_info("%s\n",debug_buf);
pr_info("%s\n", buf);
}
static void consys_print_power_debug(int level)
@ -209,11 +204,6 @@ static int consys_check_conninfra_on_domain(void)
return 1;
}
int consys_check_conninfra_on_domain_mt6895(void)
{
return consys_check_conninfra_on_domain();
}
static int consys_check_conninfra_off_domain(void)
{
unsigned int r;
@ -251,10 +241,8 @@ static int __consys_check_reg_readable(int check_type)
return 0;
/* wake up conninfra to read off register */
if (consys_hw_force_conninfra_wakeup() != 0)
return 0;
wakeup_conninfra = 1;
consys_hw_force_conninfra_wakeup();
ret = 0;
}
@ -282,13 +270,7 @@ static void consys_debug_init_mt6895(void)
{
debug_info = (struct conn_debug_info_mt6895 *)osal_malloc(sizeof(struct conn_debug_info_mt6895));
if (debug_info == NULL) {
pr_notice("%s debug_info malloc failed\n", __func__);
return;
}
debug_buf = osal_malloc(CONSYS_DUMP_BUF_SIZE);
if (debug_buf == NULL) {
pr_notice("%s debug_buf malloc failed\n", __func__);
pr_notice("%s malloc failed\n", __func__);
return;
}
@ -297,15 +279,13 @@ static void consys_debug_init_mt6895(void)
static void consys_debug_deinit_mt6895(void)
{
if (debug_info != NULL) {
osal_free(debug_info);
debug_info = NULL;
if (debug_info == NULL) {
pr_notice("%s debug_info is NULL\n", __func__);
return;
}
if (debug_buf != NULL) {
osal_free(debug_buf);
debug_buf = NULL;
}
osal_free(debug_info);
debug_info = NULL;
consys_debug_deinit_mt6895_debug_gen();
}

383
drivers/misc/mediatek/connectivity/conninfra/platform/mt6895/mt6895_debug_gen.c
View file

@ -11,7 +11,7 @@
* It should not be modified by hand.
*
* Reference debug file,
* - [Lxxxn]connsys_power_debug.xlsx (Modified date: 2021-12-28)
* - [Lxxxn]connsys_power_debug.xlsx (Modified date: 2021-08-18)
* - [Lxxxn]conn_infra_bus_debug_ctrl.xlsx (Modified date: 2021-10-14)
*/
@ -30,16 +30,16 @@
void __iomem *vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 = NULL;
void __iomem *vir_addr_consys_dbg_gen_topckgen_base_mt6895 = NULL;
void __iomem *vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6895 = NULL;
void __iomem *vir_addr_consys_dbg_gen_conn_infra_sysram_base_offset_mt6895 = NULL;
void __iomem *vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6895 = NULL;
void __iomem *vir_addr_0x1804c000_mt6895 = NULL;
void consys_debug_init_mt6895_debug_gen(void)
{
vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 = ioremap(CONSYS_DBG_GEN_SRCLKENRC_BASE_ADDR, 0x77C);
vir_addr_consys_dbg_gen_topckgen_base_mt6895 = ioremap(CONSYS_DBG_GEN_TOPCKGEN_BASE_ADDR, 0x180);
vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6895 = ioremap(CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR, 0x41c);
vir_addr_consys_dbg_gen_conn_infra_sysram_base_offset_mt6895 = ioremap(CONSYS_DBG_GEN_CONN_INFRA_SYSRAM_BASE_OFFSET_ADDR, 0xBA4);
vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6895 = ioremap(CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR, 0x41c);
vir_addr_0x1804c000_mt6895 = ioremap(0x1804c000, 0xc);
}
@ -51,12 +51,12 @@ void consys_debug_deinit_mt6895_debug_gen(void)
if (vir_addr_consys_dbg_gen_topckgen_base_mt6895)
iounmap(vir_addr_consys_dbg_gen_topckgen_base_mt6895);
if (vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6895)
iounmap(vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6895);
if (vir_addr_consys_dbg_gen_conn_infra_sysram_base_offset_mt6895)
iounmap(vir_addr_consys_dbg_gen_conn_infra_sysram_base_offset_mt6895);
if (vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6895)
iounmap(vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6895);
if (vir_addr_0x1804c000_mt6895)
iounmap(vir_addr_0x1804c000_mt6895);
}
@ -159,336 +159,234 @@ void consys_print_power_debug_dbg_level_0_mt6895_debug_gen(
/* A2 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A2", 0x1C00D000 + CONSYS_DBG_GEN_FSM_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_FSM_STA_0_OFFSET_ADDR));
/* A3 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A3", 0x1C00D000 + CONSYS_DBG_GEN_CMD_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_CMD_STA_0_OFFSET_ADDR));
/* A4 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A4", 0x1C00D000 + CONSYS_DBG_GEN_CMD_STA_1_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_CMD_STA_1_OFFSET_ADDR));
/* A5 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A5", 0x1C00D000 + CONSYS_DBG_GEN_SPI_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SPI_STA_0_OFFSET_ADDR));
/* A6 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A6", 0x1C00D000 + CONSYS_DBG_GEN_PI_PO_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_PI_PO_STA_0_OFFSET_ADDR));
/* A7 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A7", 0x1C00D000 + CONSYS_DBG_GEN_M00_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M00_REQ_STA_0_OFFSET_ADDR));
/* A8 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A8", 0x1C00D000 + CONSYS_DBG_GEN_M01_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M01_REQ_STA_0_OFFSET_ADDR));
/* A9 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A9", 0x1C00D000 + CONSYS_DBG_GEN_M02_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M02_REQ_STA_0_OFFSET_ADDR));
/* A10 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A10", 0x1C00D000 + CONSYS_DBG_GEN_M03_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M03_REQ_STA_0_OFFSET_ADDR));
/* A11 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A11", 0x1C00D000 + CONSYS_DBG_GEN_M04_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M04_REQ_STA_0_OFFSET_ADDR));
/* A12 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A12", 0x1C00D000 + CONSYS_DBG_GEN_M05_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M05_REQ_STA_0_OFFSET_ADDR));
/* A13 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A13", 0x1C00D000 + CONSYS_DBG_GEN_M06_REQ_STA_0_OFFSET_ADDR,
"A2", 0x1C00D000 + CONSYS_DBG_GEN_M06_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M06_REQ_STA_0_OFFSET_ADDR));
/* A14 */
/* A3 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A14", 0x1C00D000 + CONSYS_DBG_GEN_M07_REQ_STA_0_OFFSET_ADDR,
"A3", 0x1C00D000 + CONSYS_DBG_GEN_M07_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M07_REQ_STA_0_OFFSET_ADDR));
/* A15 */
/* A4 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A15", 0x1C00D000 + CONSYS_DBG_GEN_M08_REQ_STA_0_OFFSET_ADDR,
"A4", 0x1C00D000 + CONSYS_DBG_GEN_M08_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M08_REQ_STA_0_OFFSET_ADDR));
/* A16 */
/* A5 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A16", 0x1C00D000 + CONSYS_DBG_GEN_M09_REQ_STA_0_OFFSET_ADDR,
"A5", 0x1C00D000 + CONSYS_DBG_GEN_M09_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M09_REQ_STA_0_OFFSET_ADDR));
/* A17 */
/* A6 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A17", 0x1C00D000 + CONSYS_DBG_GEN_M10_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M10_REQ_STA_0_OFFSET_ADDR));
/* A18 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A18", 0x1C00D000 + CONSYS_DBG_GEN_M11_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M11_REQ_STA_0_OFFSET_ADDR));
/* A19 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A19", 0x1C00D000 + CONSYS_DBG_GEN_M12_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M12_REQ_STA_0_OFFSET_ADDR));
/* A20 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A20", 0x1C00D000 + CONSYS_DBG_GEN_M13_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_M13_REQ_STA_0_OFFSET_ADDR));
/* A21 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A21", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_STA_0_OFFSET_ADDR));
/* A21 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A21", 0x1C00D000 + CONSYS_DBG_GEN_SPMI_P_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SPMI_P_STA_0_OFFSET_ADDR));
/* A22 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A22", 0x1C001000 + CONSYS_DBG_GEN_CONN_PWR_CON_OFFSET_ADDR,
"A6", 0x1C001000 + CONSYS_DBG_GEN_CONN_PWR_CON_OFFSET_ADDR,
CONSYS_REG_READ(SPM_REG_BASE +
CONSYS_DBG_GEN_CONN_PWR_CON_OFFSET_ADDR));
/* A23 */
/* A7 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A23", 0x10000000 + 0x180,
"A7", 0x10000000 + 0x180,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_topckgen_base_mt6895 + 0x180));
/* A24 */
/* A8 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A24", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_0_LSB_OFFSET_ADDR,
"A8", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_0_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_0_LSB_OFFSET_ADDR));
/* A25 */
/* A9 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A25", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_0_MSB_OFFSET_ADDR,
"A9", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_0_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_0_MSB_OFFSET_ADDR));
/* A26 */
/* A10 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A26", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_1_LSB_OFFSET_ADDR,
"A10", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_1_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_1_LSB_OFFSET_ADDR));
/* A27 */
/* A11 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A27", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_1_MSB_OFFSET_ADDR,
"A11", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_1_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_1_MSB_OFFSET_ADDR));
/* A28 */
/* A12 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A28", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_2_LSB_OFFSET_ADDR,
"A12", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_2_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_2_LSB_OFFSET_ADDR));
/* A29 */
/* A13 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A29", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_2_MSB_OFFSET_ADDR,
"A13", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_2_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_2_MSB_OFFSET_ADDR));
/* A30 */
/* A14 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A30", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_3_LSB_OFFSET_ADDR,
"A14", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_3_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_3_LSB_OFFSET_ADDR));
/* A31 */
/* A15 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A31", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_3_MSB_OFFSET_ADDR,
"A15", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_3_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_3_MSB_OFFSET_ADDR));
/* A32 */
/* A16 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A32", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_4_LSB_OFFSET_ADDR,
"A16", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_4_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_4_LSB_OFFSET_ADDR));
/* A33 */
/* A17 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A33", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_4_MSB_OFFSET_ADDR,
"A17", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_4_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_4_MSB_OFFSET_ADDR));
/* A34 */
/* A18 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A34", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_5_LSB_OFFSET_ADDR,
"A18", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_5_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_5_LSB_OFFSET_ADDR));
/* A35 */
/* A19 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A35", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_5_MSB_OFFSET_ADDR,
"A19", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_5_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_5_MSB_OFFSET_ADDR));
/* A36 */
/* A20 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A36", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_6_LSB_OFFSET_ADDR,
"A20", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_6_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_6_LSB_OFFSET_ADDR));
/* A37 */
/* A21 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A37", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_6_MSB_OFFSET_ADDR,
"A21", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_6_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_6_MSB_OFFSET_ADDR));
/* A38 */
/* A22 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A38", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_7_LSB_OFFSET_ADDR,
"A22", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_7_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_7_LSB_OFFSET_ADDR));
/* A39 */
/* A23 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A39", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_7_MSB_OFFSET_ADDR,
"A23", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_7_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_DEBUG_TRACE_7_MSB_OFFSET_ADDR));
/* A40 */
/* A24 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A40", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_LSB_OFFSET_ADDR,
"A24", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_LSB_OFFSET_ADDR));
/* A41 */
/* A25 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A41", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_MSB_OFFSET_ADDR,
"A25", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_MSB_OFFSET_ADDR));
/* A42 */
/* A26 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A42", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_LSB_OFFSET_ADDR,
"A26", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_LSB_OFFSET_ADDR));
/* A43 */
/* A27 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A43", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_MSB_OFFSET_ADDR,
"A27", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_MSB_OFFSET_ADDR));
/* A44 */
/* A28 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A44", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_LSB_OFFSET_ADDR,
"A28", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_LSB_OFFSET_ADDR));
/* A45 */
/* A29 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A45", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_MSB_OFFSET_ADDR,
"A29", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_MSB_OFFSET_ADDR));
/* A46 */
/* A30 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A46", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_LSB_OFFSET_ADDR,
"A30", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_LSB_OFFSET_ADDR));
/* A47 */
/* A31 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A47", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_MSB_OFFSET_ADDR,
"A31", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_MSB_OFFSET_ADDR));
/* A48 */
/* A32 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A48", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_LSB_OFFSET_ADDR,
"A32", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_LSB_OFFSET_ADDR));
/* A49 */
/* A33 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A49", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_MSB_OFFSET_ADDR,
"A33", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_MSB_OFFSET_ADDR));
/* A50 */
/* A34 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A50", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_LSB_OFFSET_ADDR,
"A34", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_LSB_OFFSET_ADDR));
/* A51 */
/* A35 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A51", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_MSB_OFFSET_ADDR,
"A35", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_MSB_OFFSET_ADDR));
/* A52 */
/* A36 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A52", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_LSB_OFFSET_ADDR,
"A36", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_LSB_OFFSET_ADDR));
/* A53 */
/* A37 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A53", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_MSB_OFFSET_ADDR,
"A37", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_MSB_OFFSET_ADDR));
/* A54 */
/* A38 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A54", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_LSB_OFFSET_ADDR,
"A38", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_LSB_OFFSET_ADDR));
/* A55 */
/* A39 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A55", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_MSB_OFFSET_ADDR,
"A39", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_MSB_OFFSET_ADDR));
/* A56 */
/* A40 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_0_info,
"A56", 0x1C00D000 + CONSYS_DBG_GEN_CMD_STA_0_OFFSET_ADDR,
"A40", 0x1C00D000 + CONSYS_DBG_GEN_CMD_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6895 +
CONSYS_DBG_GEN_CMD_STA_0_OFFSET_ADDR));
}
@ -505,12 +403,6 @@ void consys_print_power_debug_dbg_level_1_mt6895_debug_gen(
if (level < 1)
return;
if (!vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6895) {
pr_notice("vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6895(%x) ioremap fail\n",
CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR);
return;
}
if (CONN_HOST_CSR_TOP_BASE == 0) {
pr_notice("CONN_HOST_CSR_TOP_BASE is not defined\n");
return;
@ -553,74 +445,8 @@ void consys_print_power_debug_dbg_level_1_mt6895_debug_gen(
CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR));
/* B3 */
CONSYS_REG_WRITE_MASK(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR, 0x1, 0x7);
update_debug_write_info_mt6895_debug_gen(pdbg_level_1_info,
"B3", 0x18060000 + CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR,
0, 2, 0x1);
update_debug_read_info_mt6895_debug_gen(pdbg_level_1_info,
NULL, 0x18060000 + CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR,
CONSYS_REG_READ(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR));
/* B4 */
CONSYS_REG_WRITE_MASK(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR, 0x2, 0x7);
update_debug_write_info_mt6895_debug_gen(pdbg_level_1_info,
"B4", 0x18060000 + CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR,
0, 2, 0x2);
update_debug_read_info_mt6895_debug_gen(pdbg_level_1_info,
NULL, 0x18060000 + CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR,
CONSYS_REG_READ(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR));
/* B5 */
CONSYS_REG_WRITE_MASK(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR, 0x3, 0x7);
update_debug_write_info_mt6895_debug_gen(pdbg_level_1_info,
"B5", 0x18060000 + CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR,
0, 2, 0x3);
update_debug_read_info_mt6895_debug_gen(pdbg_level_1_info,
NULL, 0x18060000 + CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR,
CONSYS_REG_READ(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR));
/* B6 */
CONSYS_REG_WRITE_MASK(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR, 0x6, 0x7);
update_debug_write_info_mt6895_debug_gen(pdbg_level_1_info,
"B6", 0x18060000 + CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR,
0, 2, 0x6);
update_debug_read_info_mt6895_debug_gen(pdbg_level_1_info,
NULL, 0x18060000 + CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR,
CONSYS_REG_READ(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR));
/* B7 */
CONSYS_REG_WRITE_MASK(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR, 0x7, 0x7);
update_debug_write_info_mt6895_debug_gen(pdbg_level_1_info,
"B7", 0x18060000 + CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR,
0, 2, 0x7);
update_debug_read_info_mt6895_debug_gen(pdbg_level_1_info,
NULL, 0x18060000 + CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR,
CONSYS_REG_READ(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR));
/* B8 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_1_info,
"B8", 0x18023000 + CONSYS_DBG_GEN_CONN_INFRA_MONFLAG_OUT_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6895 +
CONSYS_DBG_GEN_CONN_INFRA_MONFLAG_OUT_OFFSET_ADDR));
/* B9 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_1_info,
"B9", 0x18060000 + CONSYS_DBG_GEN_CONNSYS_PWR_STATES_OFFSET_ADDR,
"B3", 0x18060000 + CONSYS_DBG_GEN_CONNSYS_PWR_STATES_OFFSET_ADDR,
CONSYS_REG_READ(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CONNSYS_PWR_STATES_OFFSET_ADDR));
}
@ -668,11 +494,6 @@ void consys_print_power_debug_dbg_level_2_mt6895_debug_gen(
return;
}
if (CONN_RF_SPI_MST_REG_BASE == 0) {
pr_notice("CONN_RF_SPI_MST_REG_BASE is not defined\n");
return;
}
/* C0 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_2_info,
"C0", 0x18011000 + CONSYS_DBG_GEN_PLL_STATUS_OFFSET_ADDR,
@ -827,42 +648,6 @@ void consys_print_power_debug_dbg_level_2_mt6895_debug_gen(
update_debug_read_info_mt6895_debug_gen(pdbg_level_2_info,
"C22", 0x18050000 + 0xBA4,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_conn_infra_sysram_base_offset_mt6895 + 0xBA4));
/* C23 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_2_info,
"C23", 0x18042000 + CONSYS_DBG_GEN_SPI_STA_OFFSET_ADDR,
CONSYS_REG_READ(CONN_RF_SPI_MST_REG_BASE +
CONSYS_DBG_GEN_SPI_STA_OFFSET_ADDR));
/* C24 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_2_info,
"C24", 0x18042000 + CONSYS_DBG_GEN_SPI_TOP_ADDR_OFFSET_ADDR,
CONSYS_REG_READ(CONN_RF_SPI_MST_REG_BASE +
CONSYS_DBG_GEN_SPI_TOP_ADDR_OFFSET_ADDR));
/* C25 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_2_info,
"C25", 0x18042000 + CONSYS_DBG_GEN_SPI_TOP_WDAT_OFFSET_ADDR,
CONSYS_REG_READ(CONN_RF_SPI_MST_REG_BASE +
CONSYS_DBG_GEN_SPI_TOP_WDAT_OFFSET_ADDR));
/* C26 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_2_info,
"C26", 0x18042000 + CONSYS_DBG_GEN_SPI_TOP_RDAT_OFFSET_ADDR,
CONSYS_REG_READ(CONN_RF_SPI_MST_REG_BASE +
CONSYS_DBG_GEN_SPI_TOP_RDAT_OFFSET_ADDR));
/* C27 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_2_info,
"C27", 0x18042000 + CONSYS_DBG_GEN_SPI_HSCK_CTL_OFFSET_ADDR,
CONSYS_REG_READ(CONN_RF_SPI_MST_REG_BASE +
CONSYS_DBG_GEN_SPI_HSCK_CTL_OFFSET_ADDR));
/* C28 */
update_debug_read_info_mt6895_debug_gen(pdbg_level_2_info,
"C28", 0x18042000 + CONSYS_DBG_GEN_SPI_CRTL_OFFSET_ADDR,
CONSYS_REG_READ(CONN_RF_SPI_MST_REG_BASE +
CONSYS_DBG_GEN_SPI_CRTL_OFFSET_ADDR));
}
void consys_print_bus_debug_dbg_level_1_mt6895_debug_gen(

128
drivers/misc/mediatek/connectivity/conninfra/platform/mt6895/mt6895_pmic.c
View file

@ -154,11 +154,11 @@ int consys_plt_pmic_get_from_dts_mt6895(struct platform_device *pdev, struct con
int consys_plt_pmic_common_power_ctrl_mt6895(unsigned int enable)
{
int ret = 0;
#ifdef CONFIG_FPGA_EARLY_PORTING
pr_info("[%s] not support on FPGA", __func__);
#else
int sleep_mode = consys_get_sleep_mode_mt6895();
int ret;
int sleep_mode;
if (enable) {
/* set PMIC VRFIO18 LDO 1.7V */
@ -169,25 +169,18 @@ int consys_plt_pmic_common_power_ctrl_mt6895(unsigned int enable)
if (ret)
pr_notice("Enable VRFIO18 fail. ret=%d\n", ret);
/* request VS2 to 1.45V by VS2 VOTER (use bit 4) */
consys_pmic_regmap_set_value(g_regmap_mt6363,
MT6363_BUCK_VS2_VOTER_CON0_SET_ADDR, 1 << 4, 1 << 4);
/* set PMIC VCN13 LDO 1.35V @Normal mode; 0.95V @LPM */
/* no need for LPM because 0.95V is default setting. */
regulator_set_voltage(reg_VCN13, 1350000, 1350000);
regulator_set_mode(reg_VCN13, REGULATOR_MODE_NORMAL); /* SW_LP = 0 */
/* 1.05V @LPM */
if (sleep_mode == 3)
consys_pmic_regmap_set_value(g_regmap_mt6363,
MT6363_RG_LDO_VCN13_VOSEL_SLEEP_ADDR, 0x7F, 0x1);
ret = regulator_enable(reg_VCN13); /* SW_EN = 1 */
if (ret)
pr_notice("Enable VCN13 fail. ret=%d\n", ret);
} else {
if (consys_is_rc_mode_enable_mt6895()) {
consys_pmic_vcn33_1_power_ctl_mt6895_rc(0);
consys_pmic_vcn33_2_power_ctl_mt6895_rc(0);
}
/* vant18 is enabled in consys_plt_pmic_common_power_low_power_mode_mt6895 */
/* Please refer to POS for more information */
consys_pmic_vant18_power_ctl_mt6895(0);
@ -196,18 +189,17 @@ int consys_plt_pmic_common_power_ctrl_mt6895(unsigned int enable)
msleep(1);
/* set PMIC VCN13 LDO SW_EN = 0, SW_LP =0 (sw disable) */
regulator_set_mode(reg_VCN13, REGULATOR_MODE_NORMAL);
ret = regulator_disable(reg_VCN13);
if (ret)
pr_notice("%s regulator_disable err: %d", __func__, ret);
regulator_disable(reg_VCN13);
/* clear bit 4 of VS2 VOTER then VS2 can restore to 1.35V */
consys_pmic_regmap_set_value(g_regmap_mt6363,
MT6363_BUCK_VS2_VOTER_CON0_CLR_ADDR, 1 << 4, 1 << 4);
/* set PMIC VRFIO18 LDO SW_EN = 0, SW_LP =0 (sw disable) */
regulator_set_mode(reg_VRFIO18, REGULATOR_MODE_NORMAL);
sleep_mode = consys_get_sleep_mode_mt6895();
if (sleep_mode == 1 || sleep_mode == 3) {
ret = regulator_disable(reg_VRFIO18);
if (ret)
pr_notice("%s regulator_disable err:%d", __func__, ret);
}
if (sleep_mode == 1)
regulator_disable(reg_VRFIO18);
/* Set buckboost to 3.45V (for VCN33_1 & VCN33_2) */
if (reg_buckboost) {
@ -216,7 +208,7 @@ int consys_plt_pmic_common_power_ctrl_mt6895(unsigned int enable)
}
}
#endif
return ret;
return 0;
}
static void consys_pmic_regmap_set_value(struct regmap *rmap, unsigned int address,
@ -237,7 +229,6 @@ static void consys_pmic_regmap_set_value(struct regmap *rmap, unsigned int addre
int consys_plt_pmic_common_power_low_power_mode_mt6895(unsigned int enable)
{
int ret = 0;
#ifdef CONFIG_FPGA_EARLY_PORTING
pr_info("[%s] not support on FPGA", __func__);
#else
@ -272,14 +263,12 @@ int consys_plt_pmic_common_power_low_power_mode_mt6895(unsigned int enable)
consys_pmic_regmap_set_value(r, MT6363_RG_LDO_VRFIO18_RC6_OP_CFG_ADDR, 1 << 6, 0 << 6);
sleep_mode = consys_get_sleep_mode_mt6895();
if (sleep_mode == 1 || sleep_mode == 3) {
if (sleep_mode == 1) {
/* set PMIC VRFIO18 LDO SW_EN = 1, SW_LP =1 */
regulator_set_mode(reg_VRFIO18, REGULATOR_MODE_IDLE);
} else {
/* set PMIC VRFIO18 LDO SW_EN = 0, SW_LP =0 */
ret = regulator_disable(reg_VRFIO18);
if (ret)
pr_notice("%s regulator_disable err: %d", __func__, ret);
regulator_disable(reg_VRFIO18);
regulator_set_mode(reg_VRFIO18, REGULATOR_MODE_NORMAL); /* SW_LP = 0 */
}
@ -340,7 +329,7 @@ int consys_plt_pmic_common_power_low_power_mode_mt6895(unsigned int enable)
consys_pmic_vcn33_2_power_ctl_mt6895_rc(enable);
}
consys_pmic_vant18_power_ctl_mt6895(enable);
return ret;
return 0;
}
int consys_plt_pmic_wifi_power_ctrl_mt6895(unsigned int enable)
@ -383,19 +372,10 @@ int consys_plt_pmic_fm_power_ctrl_mt6895(unsigned int enable)
static int consys_pmic_vcn33_1_power_ctl_mt6895_rc(bool enable)
{
#ifndef CONFIG_FPGA_EARLY_PORTING
int ret = 0;
struct regmap *r = g_regmap_mt6368;
int sleep_mode = consys_get_sleep_mode_mt6895();
if (!enable) {
if (sleep_mode == 3) {
ret = regulator_disable(reg_VCN33_1);
if (ret)
pr_notice("[%s] Disable VCN33_1 fail, ret=%d\n", __func__, ret);
}
if (!enable)
return 0;
}
/* 1. set PMIC VCN33_1 LDO PMIC HW mode control by PMRC_EN[8][7] */
/* 1.1. set PMIC VCN33_1 LDO op_mode = 0 */
@ -409,14 +389,6 @@ static int consys_pmic_vcn33_1_power_ctl_mt6895_rc(bool enable)
/* 2. set PMIC VCN33_1 LDO SW_EN = 0, SW_LP =0 (sw disable) */
regulator_set_mode(reg_VCN33_1, REGULATOR_MODE_NORMAL);
if (sleep_mode == 3) {
ret = regulator_enable(reg_VCN33_1);
if (ret)
pr_notice("[%s] Enable VCN33_1 fail, ret=%d\n", __func__, ret);
udelay(210);
/* set PMIC VCN33_1 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =1 (sw lp) */
regulator_set_mode(reg_VCN33_1, REGULATOR_MODE_IDLE);
}
#endif
return 0;
}
@ -425,7 +397,6 @@ static int consys_pmic_vcn33_1_power_ctl_mt6895_lg(bool enable)
{
struct regmap *r = g_regmap_mt6368;
static int enable_count = 0;
int ret = 0;
/* In legacy mode, VCN33_1 should be turned on either WIFI or BT is on */
@ -442,10 +413,8 @@ static int consys_pmic_vcn33_1_power_ctl_mt6895_lg(bool enable)
}
if (enable_count == 0) {
ret = regulator_disable(reg_VCN33_1);
if (ret)
pr_notice("%s regulator_disable err:%d", __func__, ret);
return ret;
regulator_disable(reg_VCN33_1);
return 0;
}
/* vcn33_1 is already on in these two cases */
@ -462,24 +431,19 @@ static int consys_pmic_vcn33_1_power_ctl_mt6895_lg(bool enable)
/* 2. set PMIC VCN33_1 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =0 */
regulator_set_mode(reg_VCN33_1, REGULATOR_MODE_NORMAL);
ret = regulator_enable(reg_VCN33_1);
if (ret)
pr_notice("%s regulator_enable err:%d", __func__, ret);
regulator_enable(reg_VCN33_1);
return ret;
return 0;
}
static int consys_pmic_vcn33_2_power_ctl_mt6895_lg(bool enable)
{
struct regmap *r = g_regmap_mt6368;
int ret = 0;
if (!enable) {
ret = regulator_disable(reg_VCN33_2);
if (ret)
pr_notice("%s regulator_disable err:%d", __func__, ret);
} else {
if (!enable)
regulator_disable(reg_VCN33_2);
else {
/* 1. set PMIC VCN33_2 LDO PMIC HW mode control by SRCCLKENA0 */
/* 1.1. set PMIC VCN33_2 LDO op_mode = 1 */
/* 1.2. set PMIC VCN33_2 LDO HW_OP_EN = 1, HW_OP_CFG = 0 */
@ -489,30 +453,18 @@ static int consys_pmic_vcn33_2_power_ctl_mt6895_lg(bool enable)
/* 2. set PMIC VCN33_2 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =0 */
regulator_set_mode(reg_VCN33_2, REGULATOR_MODE_NORMAL);
ret = regulator_enable(reg_VCN33_2);
if (ret)
pr_notice("%s regulator_enable err:%d", __func__, ret);
regulator_enable(reg_VCN33_2);
}
return ret;
return 0;
}
static int consys_pmic_vcn33_2_power_ctl_mt6895_rc(bool enable)
{
#ifndef CONFIG_FPGA_EARLY_PORTING
int ret = 0;
struct regmap *r = g_regmap_mt6368;
int sleep_mode = consys_get_sleep_mode_mt6895();
if (!enable) {
if (sleep_mode == 3) {
ret = regulator_disable(reg_VCN33_2);
if (ret)
pr_notice("[%s] Disable VCN33_2 fail, ret=%d\n", __func__, ret);
}
if (!enable)
return 0;
}
/* 1. set PMIC VCN33_2 LDO PMIC HW mode control by PMRC_EN[8] */
/* 1.1. set PMIC VCN33_2 LDO op_mode = 0 */
@ -523,32 +475,20 @@ static int consys_pmic_vcn33_2_power_ctl_mt6895_rc(bool enable)
/* 2. set PMIC VCN33_2 LDO SW_EN = 0, SW_LP =0 (sw disable) */
regulator_set_mode(reg_VCN33_2, REGULATOR_MODE_NORMAL);
if (sleep_mode == 3) {
ret = regulator_enable(reg_VCN33_2);
if (ret)
pr_notice("[%s] Enable VCN33_2 fail, ret=%d\n", __func__, ret);
udelay(210);
/* set PMIC VCN33_2 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =1 (sw lp) */
regulator_set_mode(reg_VCN33_2, REGULATOR_MODE_IDLE);
}
#endif
return 0;
}
static int consys_pmic_vant18_power_ctl_mt6895(bool enable)
{
int ret = 0;
#ifndef CONFIG_FPGA_EARLY_PORTING
struct regmap *r = g_regmap_mt6368;
if (!enable) {
/* 1. VANT18 will be set to SW_EN=1 only in legacy momde. */
/* 2. VANT18 might not be enabled because power on fail before low power control is executed. */
if (consys_is_rc_mode_enable_mt6895() == 0 && regulator_is_enabled(reg_VANT18)) {
ret = regulator_disable(reg_VANT18);
if (ret)
pr_notice("%s regulator_disable err:%d", __func__, ret);
}
if (consys_is_rc_mode_enable_mt6895() == 0 && regulator_is_enabled(reg_VANT18))
regulator_disable(reg_VANT18);
return 0;
}
@ -572,12 +512,10 @@ static int consys_pmic_vant18_power_ctl_mt6895(bool enable)
/* 2. set PMIC VANT18 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =0 */
regulator_set_mode(reg_VANT18, REGULATOR_MODE_NORMAL);
ret = regulator_enable(reg_VANT18);
if (ret)
pr_notice("%s regulator_disable err:%d", __func__, ret);
regulator_enable(reg_VANT18);
}
#endif
return ret;
return 0;
}
static int consys_plt_pmic_event_notifier_mt6895(unsigned int id, unsigned int event)
@ -671,7 +609,7 @@ void consys_pmic_debug_log_mt6895(void)
{
struct regmap *r = g_regmap_mt6363;
struct regmap *r2 = g_regmap_mt6368;
int vcn13 = 0, vrfio18 = 0, vcn33_1 = 0, vcn33_2 = 0, vant18 = 0;
int vcn13, vrfio18, vcn33_1, vcn33_2, vant18;
if (!r || !r2) {
pr_notice("%s regmap is NULL\n", __func__);

128
drivers/misc/mediatek/connectivity/conninfra/platform/mt6895/mt6895_pos.c
View file

@ -33,7 +33,7 @@
#define MT6637E1 0x66378A00
#define MT6637E2 0x66378A01
#define SEMA_HOLD_TIME_THRESHOLD 5 //5 ms
#define SEMA_HOLD_TIME_THRESHOLD 10 //10 ms
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
@ -54,42 +54,17 @@ struct a_die_reg_config {
********************************************************************************
*/
static u64 sema_get_time[CONN_SEMA_NUM_MAX];
static u64 log_sema_time[10];
static unsigned int sema_count = 0;
static unsigned long g_sema_irq_flags = 0;
#ifndef CONFIG_FPGA_EARLY_PORTING
static const char* get_spi_sys_name(enum sys_spi_subsystem subsystem);
#endif
static int connsys_adie_clock_buffer_setting(unsigned int curr_status, unsigned int next_status);
/*
#ifdef OPLUS_BUG_STABILITY
liumin@NETWORK.WIFI.ALPS06544156, 2022/05/16
Add for lisa , It is a badboard and sound "dada" when wifi open/close scence
*/
extern char prj_name[];
static bool isBadBoardPrj() {
unsigned long dev_prj = simple_strtoul(prj_name,NULL,16);
pr_info("[consys]project No.:%d\n", dev_prj);
if (dev_prj == 0x21641 || dev_prj == 0x21642 || dev_prj == 0x21649
|| dev_prj == 0x216BE || dev_prj == 0x216BF || dev_prj == 0x216E5
|| dev_prj == 0x216E6) {
return true;
}
return false;
}
/* End */
unsigned int consys_emi_set_remapping_reg_mt6895(
phys_addr_t con_emi_base_addr,
phys_addr_t md_shared_emi_base_addr,
phys_addr_t gps_emi_base_addr)
phys_addr_t md_shared_emi_base_addr)
{
return consys_emi_set_remapping_reg_mt6895_gen(con_emi_base_addr, md_shared_emi_base_addr,
gps_emi_base_addr, 16);
return consys_emi_set_remapping_reg_mt6895_gen(con_emi_base_addr, md_shared_emi_base_addr, 16);
}
int consys_conninfra_on_power_ctrl_mt6895(unsigned int enable)
@ -117,22 +92,6 @@ int consys_conninfra_sleep_mt6895(void)
return consys_conninfra_sleep_mt6895_gen();
}
static void print_pmif_reg(void)
{
void __iomem *addr = NULL;
unsigned int v;
/* DEBUGTOP_MON 0x0d0a0088 */
addr = ioremap(0x0d0a0088, 0x4);
if (!addr) {
pr_notice("%s clk cg ioremap failed\n", __func__);
return;
}
v = CONSYS_REG_READ(addr);
iounmap(addr);
pr_info("[consys]DEBUGTOP_MON:%x\n", v);
}
void consys_set_if_pinmux_mt6895(unsigned int enable)
{
#ifndef CFG_CONNINFRA_ON_CTP
@ -140,10 +99,8 @@ void consys_set_if_pinmux_mt6895(unsigned int enable)
struct pinctrl_state *tcxo_pinctrl_clr;
int ret = -1;
#endif
int clock_type;
int clock_type = consys_co_clock_type_mt6895();
print_pmif_reg();
clock_type = consys_co_clock_type_mt6895();
if (enable) {
consys_set_if_pinmux_mt6895_gen(1);
/* if(TCXO mode)
@ -253,14 +210,6 @@ int consys_get_sleep_mode_mt6895(void)
if (conn_hw_env.adie_hw_version == MT6637E1)
return 1;
//#ifdef OPLUS_BUG_STABILITY
//CONNECTIVITY.WIFI, 2022/05/16
//Add for lisa, for resolved 'da da'
if (isBadBoardPrj()) {
return 3;
}
//#endif /* OPLUS_BUG_STABILITY */
return 1;
}
@ -314,6 +263,7 @@ int connsys_a_die_cfg_mt6895(void)
consys_sema_release_mt6895(CONN_SEMA_RFSPI_INDEX);
return -1;
}
pr_info("[%s] A-die chip id: 0x%08x\n", __func__, adie_id);
conn_hw_env.adie_hw_version = adie_id;
/* Write to conninfra sysram */
@ -337,8 +287,7 @@ int connsys_a_die_cfg_mt6895(void)
conn_hw_env.is_rc_mode = consys_is_rc_mode_enable_mt6895();
sleep_mode = consys_get_sleep_mode_mt6895();
pr_info("[%s] sleep_mode=[%d]\n", __func__, sleep_mode);
pr_info("sleep_mode = %d\n", sleep_mode);
connsys_wt_slp_top_power_saving_ctrl_adie6637_mt6895_gen(adie_id, sleep_mode);
#endif /* CONFIG_FPGA_EARLY_PORTING */
return 0;
@ -351,13 +300,6 @@ void connsys_afe_sw_patch_mt6895(void)
int connsys_afe_wbg_cal_mt6895(void)
{
static int first_cal = 1;
/* DAC cal should be executed only once. */
/* The result will be stored in always-on domain. */
if (first_cal == 0)
return 0;
first_cal = 0;
return connsys_afe_wbg_cal_mt6895_gen(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT);
}
@ -398,6 +340,7 @@ static int consys_sema_acquire(unsigned int index)
int consys_sema_acquire_timeout_mt6895(unsigned int index, unsigned int usec)
{
int i;
unsigned long flags = 0;
if (index >= CONN_SEMA_NUM_MAX)
return CONN_SEMA_GET_FAIL;
@ -405,7 +348,7 @@ int consys_sema_acquire_timeout_mt6895(unsigned int index, unsigned int usec)
if (consys_sema_acquire(index) == CONN_SEMA_GET_SUCCESS) {
sema_get_time[index] = jiffies;
if (index == CONN_SEMA_RFSPI_INDEX)
local_irq_save(g_sema_irq_flags);
local_irq_save(flags);
return CONN_SEMA_GET_SUCCESS;
}
udelay(1);
@ -427,6 +370,7 @@ int consys_sema_acquire_timeout_mt6895(unsigned int index, unsigned int usec)
void consys_sema_release_mt6895(unsigned int index)
{
u64 duration;
unsigned long flags = 0;
if (index >= CONN_SEMA_NUM_MAX)
return;
@ -434,25 +378,10 @@ void consys_sema_release_mt6895(unsigned int index)
(CONN_SEMAPHORE_CONN_SEMA00_M2_OWN_REL_ADDR + index*4), 0x1);
duration = jiffies_to_msecs(jiffies - sema_get_time[index]);
if (index == CONN_SEMA_RFSPI_INDEX) {
local_irq_restore(g_sema_irq_flags);
if (sema_count == 10)
sema_count = 0;
log_sema_time[sema_count] = duration;
sema_count++;
/* delay for firmware to take semaphore */
udelay(2);
}
if (duration > SEMA_HOLD_TIME_THRESHOLD) {
if (index == CONN_SEMA_RFSPI_INDEX)
local_irq_restore(flags);
if (duration > SEMA_HOLD_TIME_THRESHOLD)
pr_notice("%s hold semaphore (%d) for %llu ms\n", __func__, index, duration);
pr_notice("[%s] log_sema_time: [%llu][%llu][%llu][%llu][%llu][%llu][%llu][%llu][%llu][%llu]\n",
__func__, log_sema_time[0], log_sema_time[1], log_sema_time[2], log_sema_time[3],
log_sema_time[4], log_sema_time[5], log_sema_time[6],
log_sema_time[7], log_sema_time[8], log_sema_time[9]);
}
}
struct spi_op {
@ -580,10 +509,6 @@ int consys_spi_read_nolock_mt6895(enum sys_spi_subsystem subsystem, unsigned int
int consys_spi_read_mt6895(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data)
{
int ret = 0;
if (subsystem == SYS_SPI_FM || subsystem == SYS_SPI_GPS)
return consys_spi_read_nolock_mt6895(subsystem, addr, data);
/* Get semaphore before read */
if (consys_sema_acquire_timeout_mt6895(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL) {
pr_notice("[SPI READ] Require semaphore fail\n");
@ -643,10 +568,6 @@ int consys_spi_write_nolock_mt6895(enum sys_spi_subsystem subsystem, unsigned in
int consys_spi_write_mt6895(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data)
{
int ret = 0;
if (subsystem == SYS_SPI_FM || subsystem == SYS_SPI_GPS)
return consys_spi_write_nolock_mt6895(subsystem, addr, data);
/* Get semaphore before read */
if (consys_sema_acquire_timeout_mt6895(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL) {
pr_notice("[SPI WRITE] Require semaphore fail\n");
@ -666,19 +587,16 @@ int consys_spi_update_bits_mt6895(enum sys_spi_subsystem subsystem, unsigned int
unsigned int new_val = 0;
bool change = false;
if (subsystem != SYS_SPI_FM && subsystem != SYS_SPI_GPS) {
/* Get semaphore before updating bits */
if (consys_sema_acquire_timeout_mt6895(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL) {
pr_notice("[SPI WRITE] Require semaphore fail\n");
return CONNINFRA_SPI_OP_FAIL;
}
/* Get semaphore before updating bits */
if (consys_sema_acquire_timeout_mt6895(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL) {
pr_notice("[SPI WRITE] Require semaphore fail\n");
return CONNINFRA_SPI_OP_FAIL;
}
ret = consys_spi_read_nolock_mt6895(subsystem, addr, &curr_val);
if (ret) {
if (subsystem != SYS_SPI_FM && subsystem != SYS_SPI_GPS)
consys_sema_release_mt6895(CONN_SEMA_RFSPI_INDEX);
consys_sema_release_mt6895(CONN_SEMA_RFSPI_INDEX);
#ifndef CONFIG_FPGA_EARLY_PORTING
pr_notice("[%s][%s] Get 0x%08x error, ret=%d",
__func__, get_spi_sys_name(subsystem), addr, ret);
@ -693,8 +611,7 @@ int consys_spi_update_bits_mt6895(enum sys_spi_subsystem subsystem, unsigned int
ret = consys_spi_write_nolock_mt6895(subsystem, addr, new_val);
}
if (subsystem != SYS_SPI_FM && subsystem != SYS_SPI_GPS)
consys_sema_release_mt6895(CONN_SEMA_RFSPI_INDEX);
consys_sema_release_mt6895(CONN_SEMA_RFSPI_INDEX);
return ret;
}
@ -777,13 +694,6 @@ int consys_subsys_status_update_mt6895(bool on, int radio)
}
consys_sema_release_mt6895(CONN_SEMA_CONN_INFRA_COMMON_SYSRAM_INDEX);
/* BT is on but wifi is not on */
if (on && (radio == CONNDRV_TYPE_BT) &&
(CONSYS_REG_READ_BIT(CONN_INFRA_SYSRAM_SW_CR_RADIO_STATUS, (0x1 << CONNDRV_TYPE_WIFI)) == 0x0))
consys_pre_cal_restore_mt6895();
return 0;
}
@ -855,7 +765,7 @@ const char* get_spi_sys_name(enum sys_spi_subsystem subsystem)
"SYS_SPI_WF2",
"SYS_SPI_WF3",
};
if (subsystem < SYS_SPI_MAX)
if (subsystem >= SYS_SPI_WF1 && subsystem < SYS_SPI_MAX)
return spi_system_name[subsystem];
return "UNKNOWN";
}

133
drivers/misc/mediatek/connectivity/conninfra/platform/mt6895/mt6895_pos_gen.c
View file

@ -11,9 +11,9 @@
* It should not be modified by hand.
*
* Reference POS file,
* - Pxxxxn_power_on_sequence_20211124.xlsx
* - Pxxxxn_conn_infra_sub_task_211117.xlsx
* - conn_infra_cmdbt_instr_autogen_20220216.txt
* - Pxxxxn_power_on_sequence_20210913.xlsx
* - Pxxxxn_conn_infra_sub_task_210811.xlsx
* - conn_infra_cmdbt_instr_autogen_20210902.txt
*/
@ -33,29 +33,28 @@
const unsigned int g_cmdbt_dwn_value_ary_mt6895[1024] = {
0x16001040, 0x16011801, 0x16100001, 0x16110000, 0x31000100, 0x16000400, 0x16011805, 0x16100A00,
0x16111805, 0x1620006F, 0x16210000, 0xCCCCCCCC, 0x16001044, 0x16011801, 0x1610FFFE, 0x1611FFFF,
0x31000100, 0x16002060, 0x16011801, 0x1610FFFF, 0x1611FFFF, 0x31000100, 0x16002070, 0x16011801,
0x1610FFFF, 0x16110000, 0x31000100, 0x1600C000, 0x16011801, 0x16100000, 0x16110000, 0x31000100,
0x1600C008, 0x16011801, 0x16100000, 0x16110000, 0x31000100, 0x1600D00C, 0x16011801, 0x161000BF,
0x16110000, 0x31000100, 0x16000740, 0x16011805, 0x16100D40, 0x16111805, 0x1620002D, 0x16210000,
0xCCCCCCCC, 0x16001040, 0x16011801, 0x32100000, 0x16200002, 0x16210000, 0x19300102, 0x31000300,
0x1600071C, 0x16011805, 0x16100D1C, 0x16111805, 0x16200009, 0x16210000, 0xCCCCCCCC, 0x16001044,
0x16011801, 0x32100000, 0x1620FFFD, 0x1621FFFF, 0x17300102, 0x31000300, 0x160005C4, 0x16011805,
0x16000400, 0x16011805, 0x16100A00, 0x16111805, 0x1620006F, 0x16210000, 0xCCCCCCCC, 0x16002060,
0x16011801, 0x1610FFFF, 0x1611FFFF, 0x31000100, 0x16002070, 0x16011801, 0x1610FFFF, 0x16110000,
0x31000100, 0x1600C000, 0x16011801, 0x16100000, 0x16110000, 0x31000100, 0x1600C008, 0x16011801,
0x16100000, 0x16110000, 0x31000100, 0x1600D00C, 0x16011801, 0x161000BF, 0x16110000, 0x31000100,
0x16000730, 0x16011805, 0x16100D30, 0x16111805, 0x1620002D, 0x16210000, 0xCCCCCCCC, 0x1600070C,
0x16011805, 0x16100D0C, 0x16111805, 0x16200009, 0x16210000, 0xCCCCCCCC, 0x160005C4, 0x16011805,
0x16100BC4, 0x16111805, 0x1620001B, 0x16210000, 0xCCCCCCCC, 0x1600C0D0, 0x16011801, 0x16100001,
0x16110000, 0x31000100, 0x16000630, 0x16011805, 0x16100C30, 0x16111805, 0x1620003B, 0x16210000,
0x16110000, 0x31000100, 0x16000630, 0x16011805, 0x16100C30, 0x16111805, 0x16200037, 0x16210000,
0xCCCCCCCC, 0x160005BC, 0x16011805, 0x16100BBC, 0x16111805, 0x16200002, 0x16210000, 0xCCCCCCCC,
0x1600D000, 0x16011804, 0x16100200, 0x16110000, 0x31000100, 0x1600D000, 0x16011804, 0x16100200,
0x161107F4, 0x31000100, 0x1600D000, 0x16011804, 0x16100204, 0x161107F4, 0x31000100, 0x1600D000,
0x16011804, 0x1610020C, 0x161107F4, 0x31000100, 0x1600D000, 0x16011804, 0x1610001C, 0x161107F4,
0x31000100, 0x6000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x16000400, 0x16011805, 0x16100A00, 0x16111805, 0x16200071, 0x16210000, 0xBBBBBBBB, 0x16002060,
0x16011801, 0x1610FFFF, 0x1611FFFF, 0x31000100, 0x16002070, 0x16011801, 0x1610FFFF, 0x16110000,
0x31000100, 0x160005C4, 0x16011805, 0x16100BC4, 0x16111805, 0x16200056, 0x16210000, 0xBBBBBBBB,
0x31000100, 0x160005C4, 0x16011805, 0x16100BC4, 0x16111805, 0x16200052, 0x16210000, 0xBBBBBBBB,
0x1600C000, 0x16011801, 0x16100000, 0x16110000, 0x31000100, 0x1600C008, 0x16011801, 0x16100000,
0x16110000, 0x31000100, 0x1600071C, 0x16011805, 0x16100D1C, 0x16111805, 0x16200009, 0x16210000,
0xBBBBBBBB, 0x1600D00C, 0x16011801, 0x161000BF, 0x16110000, 0x31000100, 0x16000740, 0x16011805,
0x16100D40, 0x16111805, 0x1620002D, 0x16210000, 0xBBBBBBBB, 0x6000000, 0x0, 0x0,
0x16110000, 0x31000100, 0x1600070C, 0x16011805, 0x16100D0C, 0x16111805, 0x16200009, 0x16210000,
0xBBBBBBBB, 0x1600D00C, 0x16011801, 0x161000BF, 0x16110000, 0x31000100, 0x16000730, 0x16011805,
0x16100D30, 0x16111805, 0x1620002D, 0x16210000, 0xBBBBBBBB, 0x6000000, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
@ -85,14 +84,14 @@ const unsigned int g_cmdbt_dwn_value_ary_mt6895[1024] = {
0x1801C598, 0x1801C59C, 0x1801C5A0, 0x1801C5A4, 0x1801C5A8, 0x1801C5AC, 0x1801C5B0, 0x1801C5B4,
0x1801C5B8, 0x1801C5BC, 0x1801C5C0, 0x1801C5C4, 0x1801C5C8, 0x1801C5CC, 0x1801C5D0, 0x1801C5D4,
0x1801C5D8, 0x1801C5E0, 0x1801C5E4, 0x1801C654, 0x1801C754, 0x1801C7B0, 0x1801C7B4, 0x1801C7C0,
0x1801C7E0, 0x1801C800, 0x1801C830, 0x1801C254, 0x1801C258, 0x1801C294, 0x1801C298, 0x1801D00C,
0x1801D008, 0x1801D024, 0x1801D028, 0x1801D02C, 0x1801D03C, 0x1801D04C, 0x1801D054, 0x1801D058,
0x1801D000, 0x1801D004, 0x1801B04C, 0x1801B0BC, 0x1801B070, 0x1801B074, 0x1801B500, 0x1801A000,
0x1801A004, 0x1801A008, 0x1801A00C, 0x1801A018, 0x1801A024, 0x1801A028, 0x1801A02C, 0x1801A110,
0x1801A200, 0x1801A204, 0x1801A208, 0x1801A20C, 0x1801A210, 0x1801A214, 0x1801A218, 0x1801A21C,
0x1801A228, 0x1801A22C, 0x1801A230, 0x1801A234, 0x1801A238, 0x1801A23C, 0x1801A240, 0x1801A244,
0x1801A248, 0x1801A304, 0x1801A30C, 0x1801A310, 0x1801A314, 0x1801A604, 0x1801A608, 0x1801A610,
0x1801A620, 0x1801A630, 0x1801A640, 0x1801A650, 0x1801A660, 0x0, 0x0, 0x0,
0x1801C7E0, 0x1801C800, 0x1801C830, 0x1801D00C, 0x1801D008, 0x1801D024, 0x1801D028, 0x1801D02C,
0x1801D03C, 0x1801D04C, 0x1801D054, 0x1801D058, 0x1801D000, 0x1801D004, 0x1801B04C, 0x1801B0BC,
0x1801B070, 0x1801B074, 0x1801B500, 0x1801A000, 0x1801A004, 0x1801A008, 0x1801A00C, 0x1801A018,
0x1801A024, 0x1801A028, 0x1801A02C, 0x1801A110, 0x1801A200, 0x1801A204, 0x1801A208, 0x1801A20C,
0x1801A210, 0x1801A214, 0x1801A218, 0x1801A21C, 0x1801A228, 0x1801A22C, 0x1801A230, 0x1801A234,
0x1801A238, 0x1801A23C, 0x1801A240, 0x1801A244, 0x1801A248, 0x1801A304, 0x1801A30C, 0x1801A310,
0x1801A314, 0x1801A604, 0x1801A608, 0x1801A610, 0x1801A620, 0x1801A630, 0x1801A640, 0x1801A650,
0x1801A660, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
@ -171,9 +170,9 @@ void consys_set_if_pinmux_mt6895_gen(unsigned int enable)
CONSYS_REG_WRITE_MASK(IOCFG_RTT_REG_BASE +
CONSYS_GEN_DRV_CFG0_OFFSET_ADDR, 0x8, 0x38);
CONSYS_REG_WRITE_MASK(vir_addr_consys_gen_iocfg_tr_base +
CONSYS_GEN_DRV_CFG1_OFFSET_ADDR, 0x200, 0xE00);
CONSYS_GEN_DRV_CFG1_OFFSET_ADDR, 0xE00, 0xE00);
CONSYS_REG_WRITE_MASK(vir_addr_consys_gen_iocfg_tr_base +
CONSYS_GEN_IOCFG_TR_DRV_CFG0_OFFSET_ADDR, 0x9240, 0x3FFC0);
CONSYS_GEN_IOCFG_TR_DRV_CFG0_OFFSET_ADDR, 0x3FFC0, 0x3FFC0);
#endif
/* set pinmux PUPD setting */
@ -544,7 +543,6 @@ int consys_polling_chipid_mt6895_gen(unsigned int *pconsys_ver_id)
unsigned int consys_emi_set_remapping_reg_mt6895_gen(
phys_addr_t con_emi_base_addr,
phys_addr_t md_shared_emi_base_addr,
phys_addr_t gps_emi_base_addr,
unsigned int emi_base_addr_offset)
{
if (CONN_BUS_CR_BASE == 0) {
@ -575,17 +573,6 @@ unsigned int consys_emi_set_remapping_reg_mt6895_gen(
CONSYS_REG_READ(CONN_BUS_CR_BASE +
CONSYS_GEN_CONN2AP_REMAP_MD_SHARE_EMI_BASE_ADDR_OFFSET_ADDR));
if (gps_emi_base_addr) {
CONSYS_REG_WRITE_OFFSET_RANGE(CONN_BUS_CR_BASE +
CONSYS_GEN_CONN2AP_REMAP_GPS_EMI_BASE_ADDR_OFFSET_ADDR,
gps_emi_base_addr, 0, emi_base_addr_offset, 20);
}
pr_info("gps_emi_base=[0x%llx] remap cr: gps=[0x%08x]\n",
gps_emi_base_addr,
CONSYS_REG_READ(CONN_BUS_CR_BASE +
CONSYS_GEN_CONN2AP_REMAP_GPS_EMI_BASE_ADDR_OFFSET_ADDR));
CONSYS_REG_WRITE_MASK(CONN_BUS_CR_BASE +
CONSYS_GEN_CONN2AP_REMAP_WF_PERI_BASE_ADDR_OFFSET_ADDR, 0x1000, 0xFFFFF);
CONSYS_REG_WRITE_MASK(CONN_BUS_CR_BASE +
@ -1445,54 +1432,6 @@ void connsys_wt_slp_top_power_saving_ctrl_adie6637_sleep_mode_2_mt6895_gen(void)
CONSYS_GEN_WB_BG_OFF6_OFFSET_ADDR, 0x1);
}
void connsys_wt_slp_top_power_saving_ctrl_adie6637_sleep_mode_3_mt6895_gen(void)
{
if (CONN_WT_SLP_CTL_REG_BASE == 0) {
pr_notice("CONN_WT_SLP_CTL_REG_BASE is not defined\n");
return;
}
/* set wt_slp CR for A-die power saving (ref. A-die power control) */
CONSYS_REG_WRITE_MASK(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_SLP_CTL_OFFSET_ADDR, 0x6, 0x1F);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_ADDR1_OFFSET_ADDR, 0xA03C);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_ADDR2_OFFSET_ADDR, 0xA03C);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_ADDR3_OFFSET_ADDR, 0xAB00);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_ADDR4_OFFSET_ADDR, 0xAB00);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_ADDR5_OFFSET_ADDR, 0xAB00);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_ADDR6_OFFSET_ADDR, 0xA0C8);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_ON1_OFFSET_ADDR, 0x0);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_ON2_OFFSET_ADDR, 0x0);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_ON3_OFFSET_ADDR, 0xC0000000);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_ON4_OFFSET_ADDR, 0xF8000000);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_ON5_OFFSET_ADDR, 0xFC000000);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_ON6_OFFSET_ADDR, 0x0);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_OFF1_OFFSET_ADDR, 0x57400000);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_OFF2_OFFSET_ADDR, 0x57400000);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_OFF3_OFFSET_ADDR, 0x0);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_OFF4_OFFSET_ADDR, 0x0);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_OFF5_OFFSET_ADDR, 0xC4000000);
CONSYS_REG_WRITE(CONN_WT_SLP_CTL_REG_BASE +
CONSYS_GEN_WB_BG_OFF6_OFFSET_ADDR, 0x1);
}
void connsys_wt_slp_top_power_saving_ctrl_adie6637_mt6895_gen(
unsigned int hw_version,
unsigned int sleep_mode)
@ -1501,13 +1440,11 @@ void connsys_wt_slp_top_power_saving_ctrl_adie6637_mt6895_gen(
connsys_wt_slp_top_power_saving_ctrl_adie6637_sleep_mode_1_mt6895_gen();
else if (sleep_mode == 2)
connsys_wt_slp_top_power_saving_ctrl_adie6637_sleep_mode_2_mt6895_gen();
else if (sleep_mode == 3)
connsys_wt_slp_top_power_saving_ctrl_adie6637_sleep_mode_3_mt6895_gen();
else {
if (hw_version == 0x66378A00)
connsys_wt_slp_top_power_saving_ctrl_adie6637_sleep_mode_1_mt6895_gen();
else
connsys_wt_slp_top_power_saving_ctrl_adie6637_sleep_mode_3_mt6895_gen();
connsys_wt_slp_top_power_saving_ctrl_adie6637_sleep_mode_2_mt6895_gen();
}
}
@ -1926,7 +1863,7 @@ int connsys_low_power_setting_mt6895_gen(void)
/* unmask osc_en for osc_en_rc */
#ifndef CONFIG_FPGA_EARLY_PORTING
CONSYS_REG_WRITE_MASK(CONN_CFG_ON_BASE +
CONSYS_GEN_CONN_INFRA_CFG_RC_CTL_1_OFFSET_ADDR, 0xC0, 0xF0);
CONSYS_GEN_CONN_INFRA_CFG_RC_CTL_1_OFFSET_ADDR, 0xD0, 0xF0);
#endif
/* enable conn_emi_bt_only_rc_en => conn_srcclkena = conn_srcclkena_cfg || conn_srcclkena_emi */
@ -1953,7 +1890,7 @@ int connsys_low_power_setting_mt6895_gen(void)
/* enable ddr_en timeout, timeout value = 1023 T (Bus clock) */
#ifndef CONFIG_FPGA_EARLY_PORTING
CONSYS_REG_WRITE_MASK(CONN_CFG_BASE +
CONSYS_GEN_EMI_CTL_0_OFFSET_ADDR, 0x3FF0, 0x7FF0);
CONSYS_GEN_EMI_CTL_0_OFFSET_ADDR, 0x10230, 0x7FF0);
#endif
/* update ddr_en timeout value enable */
@ -1992,7 +1929,7 @@ int connsys_low_power_setting_mt6895_gen(void)
/* set conn_infra_off bus apb/ahb/axi layer timeout - step 1 set timing */
CONSYS_REG_WRITE_MASK(CONN_BUS_CR_BASE +
CONSYS_GEN_CONN_INFRA_OFF_BUS_TIMEOUT_CTRL_OFFSET_ADDR, 0x110, 0x7F8);
CONSYS_GEN_CONN_INFRA_OFF_BUS_TIMEOUT_CTRL_OFFSET_ADDR, 0x188, 0x7F8);
/* set conn_infra_off bus apb/ahb/axi layer timeout - step 2 enable function */
CONSYS_SET_BIT(CONN_BUS_CR_BASE +
@ -2006,14 +1943,6 @@ int connsys_low_power_setting_mt6895_gen(void)
CONSYS_SET_BIT(CONN_BUS_CR_ON_BASE +
CONSYS_GEN_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_OFFSET_ADDR, (0x1 << 0));
/* set conn_von_top bus apb timeout - step 1 set timing */
CONSYS_REG_WRITE_MASK(CONN_BUS_CR_ON_BASE +
CONSYS_GEN_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_OFFSET_ADDR, 0x498, 0x7F8);
/* set conn_von_top bus apb timeout - step 2 enable function */
CONSYS_SET_BIT(CONN_BUS_CR_ON_BASE +
CONSYS_GEN_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_OFFSET_ADDR, (0x1 << 0));
/* enable conn_infra off bus tool auto gen timeout feature */
CONSYS_SET_BIT(CONN_OFF_DEBUG_CTRL_AO_BASE +
CONSYS_GEN_CONN_INFRA_VDNR_GEN_U_DEBUG_CTRL_AO_CONN_INFRA_OFF_CTRL0_OFFSET_ADDR, (0x1 << 9));
@ -2145,8 +2074,6 @@ int consys_conninfra_wakeup_mt6895_gen(void)
CONSYS_REG_WRITE(CONN_HOST_CSR_TOP_BASE +
CONSYS_GEN_CONN_INFRA_WAKEPU_TOP_OFFSET_ADDR, 0x1);
udelay(200);
/* check CONN_INFRA IP versionn */
/* (polling "10 times" for specific project code and each polling interval is "1ms") */
if (consys_polling_chipid_mt6895_gen(NULL))

1
drivers/misc/mediatek/connectivity/conninfra/platform/mt6983/include/mt6983.h
View file

@ -48,6 +48,5 @@ int consys_platform_spm_conn_ctrl_mt6983(unsigned int enable);
int consys_co_clock_type_mt6983(void);
void update_thermal_data_mt6983(struct consys_plat_thermal_data_mt6983* input);
unsigned int consys_get_adie_chipid_mt6983(void);
int consys_pre_cal_restore_mt6983(void);
#endif /* _PLATFORM_MT6983_H_ */

3
drivers/misc/mediatek/connectivity/conninfra/platform/mt6983/include/mt6983_consys_reg.h
View file

@ -68,8 +68,5 @@ extern struct consys_base_addr conn_reg_mt6983;
#define CONN_REG_SPM_ADDR conn_reg_mt6983.reg_base_addr[SPM_BASE_INDEX].vir_addr
#define CONN_REG_TOP_RGU_ADDR conn_reg_mt6983.reg_base_addr[TOP_RGU_BASE_INDEX].vir_addr
int consys_check_conninfra_on_domain_mt6983(void);
int consys_print_debug_mt6983(int level);
#endif /* _PLATFORM_MT6983_CONSYS_REG_H_ */

49
drivers/misc/mediatek/connectivity/conninfra/platform/mt6983/include/mt6983_debug_gen.h
View file

@ -11,7 +11,7 @@
* It should not be modified by hand.
*
* Reference debug file,
* - [Lxxxn]connsys_power_debug.xlsx (Modified date: 2021-12-28)
* - [Lxxxn]connsys_power_debug.xlsx (Modified date: 2021-08-18)
* - [Lxxxn]conn_infra_bus_debug_ctrl.xlsx (Modified date: 2021-10-14)
*/
@ -80,27 +80,11 @@ void consys_print_bus_slpprot_debug_dbg_level_0_mt6983_debug_gen(
/* Base: CONSYS_DBG_GEN_SRCLKENRC_BASE_ADDR (0x1C00_D000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_SRCLKENRC_BASE_ADDR 0x1C00D000
#define CONSYS_DBG_GEN_FSM_STA_0_OFFSET_ADDR 0x100
#define CONSYS_DBG_GEN_CMD_STA_0_OFFSET_ADDR 0x104
#define CONSYS_DBG_GEN_CMD_STA_1_OFFSET_ADDR 0x108
#define CONSYS_DBG_GEN_SPI_STA_0_OFFSET_ADDR 0x10C
#define CONSYS_DBG_GEN_PI_PO_STA_0_OFFSET_ADDR 0x110
#define CONSYS_DBG_GEN_M00_REQ_STA_0_OFFSET_ADDR 0x114
#define CONSYS_DBG_GEN_M01_REQ_STA_0_OFFSET_ADDR 0x118
#define CONSYS_DBG_GEN_M02_REQ_STA_0_OFFSET_ADDR 0x11C
#define CONSYS_DBG_GEN_M03_REQ_STA_0_OFFSET_ADDR 0x120
#define CONSYS_DBG_GEN_M04_REQ_STA_0_OFFSET_ADDR 0x124
#define CONSYS_DBG_GEN_M05_REQ_STA_0_OFFSET_ADDR 0x128
#define CONSYS_DBG_GEN_M06_REQ_STA_0_OFFSET_ADDR 0x12C
#define CONSYS_DBG_GEN_M07_REQ_STA_0_OFFSET_ADDR 0x130
#define CONSYS_DBG_GEN_M08_REQ_STA_0_OFFSET_ADDR 0x134
#define CONSYS_DBG_GEN_M09_REQ_STA_0_OFFSET_ADDR 0x138
#define CONSYS_DBG_GEN_M10_REQ_STA_0_OFFSET_ADDR 0x13C
#define CONSYS_DBG_GEN_M11_REQ_STA_0_OFFSET_ADDR 0x140
#define CONSYS_DBG_GEN_M12_REQ_STA_0_OFFSET_ADDR 0x144
#define CONSYS_DBG_GEN_M13_REQ_STA_0_OFFSET_ADDR 0x148
#define CONSYS_DBG_GEN_DEBUG_STA_0_OFFSET_ADDR 0x14C
#define CONSYS_DBG_GEN_SPMI_P_STA_0_OFFSET_ADDR 0x150
#define CONSYS_DBG_GEN_DEBUG_TRACE_0_LSB_OFFSET_ADDR 0x700
#define CONSYS_DBG_GEN_DEBUG_TRACE_0_MSB_OFFSET_ADDR 0x704
#define CONSYS_DBG_GEN_DEBUG_TRACE_1_LSB_OFFSET_ADDR 0x708
@ -146,20 +130,6 @@ void consys_print_bus_slpprot_debug_dbg_level_0_mt6983_debug_gen(
#define CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR 0xa04
#define CONSYS_DBG_GEN_CONNSYS_PWR_STATES_OFFSET_ADDR 0xA10
/*************************************************************************************/
/* Base: CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR (0x1802_3000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR 0x18023000
#define CONSYS_DBG_GEN_CONN_INFRA_MONFLAG_OUT_OFFSET_ADDR 0x200
#define CONSYS_DBG_GEN_CONN_INFRA_BUS_TIMEOUT_IRQ_OFFSET_ADDR 0x400
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_BUS_DBG_OUT_OFFSET_ADDR 0x404
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_BUS_DBG_SEL_OFFSET_ADDR 0x408
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUGSYS_CTRL_OFFSET_ADDR 0x40c
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_INFO_OFFSET_ADDR 0x410
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_ADDR_OFFSET_ADDR 0x414
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_WDATA_OFFSET_ADDR 0x418
#define CONSYS_DBG_GEN_CONN_INFRA_VON_BUS_DEBUG_INFO_OFFSET_ADDR 0x41c
/*************************************************************************************/
/* Base: CONN_CFG_BASE (0x1801_1000) */
/*************************************************************************************/
@ -208,14 +178,17 @@ void consys_print_bus_slpprot_debug_dbg_level_0_mt6983_debug_gen(
#define CONSYS_DBG_GEN_CONN_INFRA_SYSRAM_BASE_OFFSET_ADDR 0x18050000
/*************************************************************************************/
/* Base: CONN_RF_SPI_MST_REG_BASE (0x1804_2000) */
/* Base: CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR (0x1802_3000) */
/*************************************************************************************/
#define CONSYS_DBG_GEN_SPI_STA_OFFSET_ADDR 0x0
#define CONSYS_DBG_GEN_SPI_CRTL_OFFSET_ADDR 0x4
#define CONSYS_DBG_GEN_SPI_TOP_ADDR_OFFSET_ADDR 0x50
#define CONSYS_DBG_GEN_SPI_TOP_WDAT_OFFSET_ADDR 0x54
#define CONSYS_DBG_GEN_SPI_TOP_RDAT_OFFSET_ADDR 0x58
#define CONSYS_DBG_GEN_SPI_HSCK_CTL_OFFSET_ADDR 0x108
#define CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR 0x18023000
#define CONSYS_DBG_GEN_CONN_INFRA_BUS_TIMEOUT_IRQ_OFFSET_ADDR 0x400
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_BUS_DBG_OUT_OFFSET_ADDR 0x404
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_BUS_DBG_SEL_OFFSET_ADDR 0x408
#define CONSYS_DBG_GEN_CONN_INFRA_OFF_DEBUGSYS_CTRL_OFFSET_ADDR 0x40c
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_INFO_OFFSET_ADDR 0x410
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_ADDR_OFFSET_ADDR 0x414
#define CONSYS_DBG_GEN_CONN_VON_BUS_APB_TIMEOUT_WDATA_OFFSET_ADDR 0x418
#define CONSYS_DBG_GEN_CONN_INFRA_VON_BUS_DEBUG_INFO_OFFSET_ADDR 0x41c
/*************************************************************************************/
/* Base: CONN_BUS_CR_ON_BASE (0x1800_e000) */

2
drivers/misc/mediatek/connectivity/conninfra/platform/mt6983/include/mt6983_pos.h
View file

@ -8,7 +8,7 @@
#include <linux/types.h>
unsigned int consys_emi_set_remapping_reg_mt6983(phys_addr_t, phys_addr_t, phys_addr_t);
unsigned int consys_emi_set_remapping_reg_mt6983(phys_addr_t, phys_addr_t);
int consys_conninfra_on_power_ctrl_mt6983(unsigned int enable);
int consys_conninfra_wakeup_mt6983(void);

21
drivers/misc/mediatek/connectivity/conninfra/platform/mt6983/include/mt6983_pos_gen.h
View file

@ -11,9 +11,9 @@
* It should not be modified by hand.
*
* Reference POS file,
* - Lxxxn_power_on_sequence_20211124.xlsx
* - Lxxxn_conn_infra_sub_task_211117.xlsx
* - conn_infra_cmdbt_instr_autogen_20220216.txt
* - Lxxxn_power_on_sequence_20211007.xlsx
* - Lxxxn_conn_infra_sub_task_210811.xlsx
* - conn_infra_cmdbt_instr_autogen_20210902.txt
*/
@ -28,7 +28,6 @@ int consys_polling_chipid_mt6983_gen(unsigned int *pconsys_ver_id);
unsigned int consys_emi_set_remapping_reg_mt6983_gen(
phys_addr_t con_emi_base_addr,
phys_addr_t md_shared_emi_base_addr,
phys_addr_t gps_emi_base_addr,
unsigned int emi_base_addr_offset);
void consys_init_conninfra_sysram_mt6983_gen(void);
void connsys_get_d_die_efuse_mt6983_gen(unsigned int *p_d_die_efuse);
@ -171,12 +170,6 @@ int consys_conninfra_sleep_mt6983_gen(void);
#define CONSYS_GEN_CLK_CFG_20_SET_OFFSET_ADDR 0x154
#define CONSYS_GEN_CLK_CFG_20_CLR_OFFSET_ADDR 0x158
/****************************************************************************************************/
/* Base: CONSYS_GEN_CONN_DBG_CTL_BASE_ADDR (0x1802_3000) */
/****************************************************************************************************/
#define CONSYS_GEN_CONN_DBG_CTL_BASE_ADDR 0x18023000
#define CONSYS_GEN_CLOCK_DETECT_OFFSET_ADDR 0x0
/****************************************************************************************************/
/* Base: CONN_CFG_BASE (0x1801_1000) */
/****************************************************************************************************/
@ -198,18 +191,11 @@ int consys_conninfra_sleep_mt6983_gen(void);
#define CONSYS_GEN_CONN_INFRA_CONN2AP_EMI_PATH_ADDR_END_OFFSET_ADDR 0x74
#define CONSYS_GEN_CONN2AP_REMAP_MCU_EMI_BASE_ADDR_OFFSET_ADDR 0x354
#define CONSYS_GEN_CONN2AP_REMAP_MD_SHARE_EMI_BASE_ADDR_OFFSET_ADDR 0x35C
#define CONSYS_GEN_CONN2AP_REMAP_GPS_EMI_BASE_ADDR_OFFSET_ADDR 0x360
#define CONSYS_GEN_CONN2AP_REMAP_WF_PERI_BASE_ADDR_OFFSET_ADDR 0x364
#define CONSYS_GEN_CONN2AP_REMAP_BT_PERI_BASE_ADDR_OFFSET_ADDR 0x368
#define CONSYS_GEN_CONN2AP_REMAP_GPS_PERI_BASE_ADDR_OFFSET_ADDR 0x36C
#define CONSYS_GEN_SCPSYS_SRAM_BASE_ADDR_OFFSET_ADDR 0x370
#define CONSYS_GEN_LIGHT_SECURITY_CTRL_OFFSET_ADDR 0x374
#define CONSYS_GEN_WF_LIGHT_SECURITY_START_ADDR_4_OFFSET_ADDR 0x398
#define CONSYS_GEN_WF_LIGHT_SECURITY_END_ADDR_4_OFFSET_ADDR 0x39C
#define CONSYS_GEN_BT_LIGHT_SECURITY_START_ADDR_4_OFFSET_ADDR 0x3C0
#define CONSYS_GEN_BT_LIGHT_SECURITY_END_ADDR_4_OFFSET_ADDR 0x3C4
#define CONSYS_GEN_M3_LIGHT_SECURITY_START_ADDR_4_OFFSET_ADDR 0x3E8
#define CONSYS_GEN_M3_LIGHT_SECURITY_END_ADDR_4_OFFSET_ADDR 0x3EC
/****************************************************************************************************/
/* Base: CONSYS_GEN_CONN_INFRA_SYSRAM_BASE_OFFSET_ADDR (0x1805_0000) */
@ -368,7 +354,6 @@ int consys_conninfra_sleep_mt6983_gen(void);
/****************************************************************************************************/
/* Base: CONN_BUS_CR_ON_BASE (0x1800_E000) */
/****************************************************************************************************/
#define CONSYS_GEN_CONN_INFRA_VON_BUS_TIMEOUT_CTRL_OFFSET_ADDR 0x24
#define CONSYS_GEN_CONN_INFRA_ON_BUS_TIMEOUT_CTRL_OFFSET_ADDR 0x38
#define CONSYS_GEN_CONN_VON_BUS_DCM_CTL_1_OFFSET_ADDR 0x104
#define CONSYS_GEN_CONN_OFF_BUS_DCM_CTL_1_OFFSET_ADDR 0x110

371
drivers/misc/mediatek/connectivity/conninfra/platform/mt6983/mt6983.c
View file

@ -15,13 +15,6 @@
#include <connectivity_build_in_adapter.h>
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
#include <oplus_conn_event.h>
#include <linux/string.h>
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
#include "osal.h"
#include "conninfra.h"
#include "conninfra_conf.h"
@ -47,7 +40,6 @@
********************************************************************************
*/
#define PLATFORM_SOC_CHIP 0x6983
#define PRINT_THERMAL_LOG_THRESHOLD 60
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
@ -64,18 +56,6 @@
********************************************************************************
*/
struct rf_cr_backup_data {
unsigned int addr;
unsigned int value1;
unsigned int value2;
};
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
static char mUevent[256] = {'\0'};
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
@ -89,17 +69,12 @@ static int consys_thermal_query_mt6983(void);
/* Power state relative */
static int consys_enable_power_dump_mt6983(void);
static int consys_reset_power_state_mt6983(void);
static int consys_reset_power_state(void);
static int consys_power_state_dump_mt6983(char *buf, unsigned int size);
static int consys_power_state_dump_mt6983(void);
static unsigned long long consys_soc_timestamp_get_mt6983(void);
static unsigned int consys_adie_detection_mt6983(void);
static void consys_set_mcu_control_mt6983(int type, bool onoff);
static int consys_pre_cal_backup_mt6983(unsigned int offset, unsigned int size);
static int consys_pre_cal_clean_data_mt6983(void);
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
@ -143,14 +118,11 @@ struct consys_hw_ops_struct g_consys_hw_ops_mt6983 = {
.consys_plt_thermal_query = consys_thermal_query_mt6983,
.consys_plt_enable_power_dump = consys_enable_power_dump_mt6983,
.consys_plt_reset_power_state = consys_reset_power_state_mt6983,
.consys_plt_reset_power_state = consys_power_state_dump_mt6983,
.consys_plt_power_state = consys_power_state_dump_mt6983,
.consys_plt_soc_timestamp_get = consys_soc_timestamp_get_mt6983,
.consys_plt_adie_detection = consys_adie_detection_mt6983,
.consys_plt_set_mcu_control = consys_set_mcu_control_mt6983,
.consys_plt_pre_cal_backup = consys_pre_cal_backup_mt6983,
.consys_plt_pre_cal_clean_data = consys_pre_cal_clean_data_mt6983,
};
extern struct consys_hw_ops_struct g_consys_hw_ops_mt6983;
@ -172,31 +144,22 @@ const struct conninfra_plat_data mt6983_plat_data = {
static struct consys_plat_thermal_data_mt6983 g_consys_plat_therm_data;
/* For calibration backup/restore */
static struct rf_cr_backup_data *mt6637_backup_data = NULL;
static unsigned int mt6637_backup_cr_number = 0;
extern phys_addr_t gConEmiPhyBase;
static void __iomem *ccif_wf2ap_sw_irq_b_addr;
static void __iomem *ccif_bgf2ap_sw_irq_b_addr;
int consys_co_clock_type_mt6983(void)
{
const struct conninfra_conf *conf;
struct regmap *map = consys_clock_mng_get_regmap();
int value = 0;
static int clock_type = -1;
int value = 0, clock_type = CONNSYS_CLOCK_SCHEMATIC_26M_COTMS;
const char *clock_name[CONNSYS_CLOCK_SCHEMATIC_MAX] = {
"26M co-clock", "52M co-clock", "26M tcxo", "52M tcxo"};
if (clock_type >= 0)
return clock_type;
/* Default solution */
conf = conninfra_conf_get_cfg();
if (NULL == conf) {
pr_err("[%s] Get conf fail", __func__);
return -1;
}
pr_info("[%s] conf->tcxo_gpio=%d conn_hw_env.tcxo_support=%d",
__func__, conf->tcxo_gpio, conn_hw_env.tcxo_support);
if (conf->tcxo_gpio != 0 || conn_hw_env.tcxo_support) {
if (conf->co_clock_flag == 3)
@ -204,19 +167,15 @@ int consys_co_clock_type_mt6983(void)
else
clock_type = CONNSYS_CLOCK_SCHEMATIC_26M_EXTCXO;
} else {
if (!map) {
if (!map)
pr_notice("%s, failed to get regmap.\n", __func__);
return -1;
} else {
else {
regmap_read(map, DCXO_DIGCLK_ELR, &value);
if (value & 0x1)
clock_type = CONNSYS_CLOCK_SCHEMATIC_52M_COTMS;
else
clock_type = CONNSYS_CLOCK_SCHEMATIC_26M_COTMS;
}
}
pr_info("[%s] conf->tcxo_gpio=%d conn_hw_env.tcxo_support=%d, %s",
__func__, conf->tcxo_gpio, conn_hw_env.tcxo_support, clock_name[clock_type]);
pr_info("%s: %s\n", __func__, clock_name[clock_type]);
return clock_type;
}
@ -226,13 +185,6 @@ int consys_clk_get_from_dts_mt6983(struct platform_device *pdev)
pm_runtime_enable(&pdev->dev);
dev_pm_syscore_device(&pdev->dev, true);
/* remap these two CR for print irq status */
if (!ccif_wf2ap_sw_irq_b_addr)
ccif_wf2ap_sw_irq_b_addr = ioremap(0x1803C008, 0x4);
if (!ccif_bgf2ap_sw_irq_b_addr)
ccif_bgf2ap_sw_irq_b_addr = ioremap(0x1803E008, 0x4);
return 0;
}
@ -250,18 +202,26 @@ int consys_platform_spm_conn_ctrl_mt6983(unsigned int enable)
ret = pm_runtime_get_sync(&(pdev->dev));
if (ret)
pr_info("pm_runtime_get_sync() fail(%d)\n", ret);
else
pr_info("pm_runtime_get_sync() CONSYS ok\n");
ret = device_init_wakeup(&(pdev->dev), true);
if (ret)
pr_info("device_init_wakeup(true) fail.\n");
else
pr_info("device_init_wakeup(true) CONSYS ok\n");
} else {
ret = device_init_wakeup(&(pdev->dev), false);
if (ret)
pr_info("device_init_wakeup(false) fail.\n");
else
pr_info("device_init_wakeup(false) CONSYS ok\n");
ret = pm_runtime_put_sync(&(pdev->dev));
if (ret)
pr_info("pm_runtime_put_sync() fail.\n");
else
pr_info("pm_runtime_put_sync() CONSYS ok\n");
}
return ret;
}
@ -299,7 +259,7 @@ int consys_enable_power_dump_mt6983(void)
return 0;
}
int consys_reset_power_state(void)
int consys_reset_power_state_mt6983(void)
{
/* Clear data and disable stop */
/* I. Clear
@ -371,43 +331,6 @@ static inline void __sleep_count_trigger_read(void)
}
static void consys_print_irq_status(void)
{
unsigned int val_1, val_2, val_3, val_4;
val_1 = CONSYS_REG_READ(CONN_REG_CONN_HOST_CSR_TOP_ADDR + 0x38) & 0x1;
val_2 = CONSYS_REG_READ(CONN_REG_CONN_HOST_CSR_TOP_ADDR + 0x34) & 0x1;
val_3 = CONSYS_REG_READ(CONN_REG_CONN_HOST_CSR_TOP_ADDR + 0x3C) & 0x2;
val_4 = CONSYS_REG_READ(CONN_REG_CONN_HOST_CSR_TOP_ADDR + 0x44) & 0x1;
// conn_bgf_hif_on_host_int_b
// (~(0x1806_0038[0] & 0x1806_0034[0])) & (~(0x1806_0038[1] & 0x1806_003C[0]))
if ((val_1 && val_2) || (val_1 && val_3))
pr_info("conn_bgf_hif_on_host_int_b %x %x %x", val_1, val_2, val_3);
// conn_gps_hif_on_host_int_b
// ~ (0x1806_0038[0] & 0x1806_0044[0])
if (val_1 && val_4)
pr_info("conn_gps_hif_on_host_int_b %x %x", val_1, val_4);
if (consys_check_conninfra_on_domain_mt6983() == 0)
return;
// ccif_wf2ap_sw_irq_b 0x1803_C008[7:0]
// ccif_bgf2ap_sw_irq_b 0x1803_E008[7:0]
if (ccif_wf2ap_sw_irq_b_addr) {
val_1 = CONSYS_REG_READ(ccif_wf2ap_sw_irq_b_addr) & 0xFF;
if (val_1 > 0)
pr_info("ccif_wf2ap_sw_irq_b %x", val_1);
}
if (ccif_bgf2ap_sw_irq_b_addr) {
val_1 = CONSYS_REG_READ(ccif_bgf2ap_sw_irq_b_addr) & 0xFF;
if (val_1 > 0)
pr_info("ccif_bgf2ap_sw_irq_b %x", val_1);
}
}
static void consys_power_state(void)
{
unsigned int i, str_len;
@ -425,29 +348,17 @@ static void consys_power_state(void)
for (i = 0; i < 15; i++) {
str_len = strlen(osc_str[i]);
if ((r & (0x1 << (1 + i))) > 0 && (buf_len + str_len < 256)) {
strncat(buf, osc_str[i], str_len);
buf_len += str_len;
}
}
if (r & 0xFFFF) {
pr_info("[%s] [0x%x] %s", __func__, r, buf);
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
snprintf(mUevent, sizeof(mUevent), "consys=power_state:%s;", buf);
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
}
consys_print_irq_status();
pr_info("[%s] [0x%x] %s", __func__, r, buf);
}
static int consys_power_state_dump(char *buf, unsigned int size, int print_log)
int consys_power_state_dump_mt6983(void)
{
#define POWER_STATE_BUF_SIZE 256
#define CONN_32K_TICKS_PER_SEC (32768)
#define CONN_TICK_TO_SEC(TICK) (TICK / CONN_32K_TICKS_PER_SEC)
static u64 round = 0;
static u64 t_conninfra_sleep_cnt = 0, t_conninfra_sleep_time = 0;
static u64 t_wf_sleep_cnt = 0, t_wf_sleep_time = 0;
@ -457,9 +368,6 @@ static int consys_power_state_dump(char *buf, unsigned int size, int print_log)
unsigned int wf_sleep_cnt, wf_sleep_time;
unsigned int bt_sleep_cnt, bt_sleep_time;
unsigned int gps_sleep_cnt, gps_sleep_time;
char temp_buf[POWER_STATE_BUF_SIZE];
char* buf_p = temp_buf;
int buf_sz = POWER_STATE_BUF_SIZE;
/* Sleep count */
/* 1. Setup read select: 0x1806_0380[3:1]
@ -482,10 +390,6 @@ static int consys_power_state_dump(char *buf, unsigned int size, int print_log)
t_conninfra_sleep_time += conninfra_sleep_time;
t_conninfra_sleep_cnt += conninfra_sleep_cnt;
/* Wait 60 us to make sure the duration to next write to SLP_COUNTER_RD_TRIGGER is
* long enough.
*/
udelay(60);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_CTL_HOST_SLP_COUNTER_SEL,
@ -498,7 +402,6 @@ static int consys_power_state_dump(char *buf, unsigned int size, int print_log)
t_wf_sleep_time += wf_sleep_time;
t_wf_sleep_cnt += wf_sleep_cnt;
udelay(60);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_CTL_HOST_SLP_COUNTER_SEL,
@ -511,7 +414,6 @@ static int consys_power_state_dump(char *buf, unsigned int size, int print_log)
t_bt_sleep_time += bt_sleep_time;
t_bt_sleep_cnt += bt_sleep_cnt;
udelay(60);
CONSYS_REG_WRITE_HW_ENTRY(
CONN_HOST_CSR_TOP_HOST_CONN_INFRA_SLP_CNT_CTL_HOST_SLP_COUNTER_SEL,
@ -524,106 +426,28 @@ static int consys_power_state_dump(char *buf, unsigned int size, int print_log)
t_gps_sleep_time += gps_sleep_time;
t_gps_sleep_cnt += gps_sleep_cnt;
if (print_log > 0 && buf != NULL && size > 0) {
buf_p = buf;
buf_sz = size;
}
if (print_log > 0 && snprintf(buf_p, buf_sz,"[consys_power_state][round:%llu]"
"conninfra:%u.%03u,%u;wf:%u.%03u,%u;bt:%u.%03u,%u;gps:%u.%03u,%u;"
"[total]conninfra:%llu.%03llu,%llu;wf:%llu.%03llu,%llu;"
"bt:%llu.%03llu,%llu;gps:%llu.%03llu,%llu;",
pr_info("[consys_power_state][round:%llu]conninfra:%u,%u;wf:%u,%u;bt:%u,%u;gps:%u,%u;",
round,
CONN_TICK_TO_SEC(conninfra_sleep_time),
CONN_TICK_TO_SEC((conninfra_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
conninfra_sleep_cnt,
CONN_TICK_TO_SEC(wf_sleep_time),
CONN_TICK_TO_SEC((wf_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
wf_sleep_cnt,
CONN_TICK_TO_SEC(bt_sleep_time),
CONN_TICK_TO_SEC((bt_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
bt_sleep_cnt,
CONN_TICK_TO_SEC(gps_sleep_time),
CONN_TICK_TO_SEC((gps_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
gps_sleep_cnt,
CONN_TICK_TO_SEC(t_conninfra_sleep_time),
CONN_TICK_TO_SEC((t_conninfra_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_conninfra_sleep_cnt,
CONN_TICK_TO_SEC(t_wf_sleep_time),
CONN_TICK_TO_SEC((t_wf_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_wf_sleep_cnt,
CONN_TICK_TO_SEC(t_bt_sleep_time),
CONN_TICK_TO_SEC((t_bt_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_bt_sleep_cnt,
CONN_TICK_TO_SEC(t_gps_sleep_time),
CONN_TICK_TO_SEC((t_gps_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_gps_sleep_cnt) > 0) {
pr_info("%s", buf_p);
}
conninfra_sleep_time, conninfra_sleep_cnt,
wf_sleep_time, wf_sleep_cnt,
bt_sleep_time, bt_sleep_cnt,
gps_sleep_time, gps_sleep_cnt);
pr_info("[consys_power_state][total]conninfra:%llu,%llu;wf:%llu,%llu;bt:%llu,%llu;gps:%llu,%llu;",
t_conninfra_sleep_time, t_conninfra_sleep_cnt,
t_wf_sleep_time, t_wf_sleep_cnt,
t_bt_sleep_time, t_bt_sleep_cnt,
t_gps_sleep_time, t_gps_sleep_cnt);
/* Power state */
if (print_log > 0) {
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
memset(mUevent, '\0', sizeof(mUevent));
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
consys_power_state();
#ifdef OPLUS_FEATURE_CONN_POWER_MONITOR
//CONNECTIVITY.WIFI.HARDWARE.POWER, 2022/06/30
//add for mtk connectivity power monitor
if (strlen(mUevent) > 0) {
snprintf(&(mUevent[strlen(mUevent)]), sizeof(mUevent)-strlen(mUevent),
"conninfra:%u.%03u,%u;wf:%u.%03u,%u;bt:%u.%03u,%u;gps:%u.%03u,%u;"
"[total]conninfra:%llu.%03llu,%llu;wf:%llu.%03llu,%llu;"
"bt:%llu.%03llu,%llu;gps:%llu.%03llu,%llu;",
CONN_TICK_TO_SEC(conninfra_sleep_time),
CONN_TICK_TO_SEC((conninfra_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
conninfra_sleep_cnt,
CONN_TICK_TO_SEC(wf_sleep_time),
CONN_TICK_TO_SEC((wf_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
wf_sleep_cnt,
CONN_TICK_TO_SEC(bt_sleep_time),
CONN_TICK_TO_SEC((bt_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
bt_sleep_cnt,
CONN_TICK_TO_SEC(gps_sleep_time),
CONN_TICK_TO_SEC((gps_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
gps_sleep_cnt,
CONN_TICK_TO_SEC(t_conninfra_sleep_time),
CONN_TICK_TO_SEC((t_conninfra_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_conninfra_sleep_cnt,
CONN_TICK_TO_SEC(t_wf_sleep_time),
CONN_TICK_TO_SEC((t_wf_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_wf_sleep_cnt,
CONN_TICK_TO_SEC(t_bt_sleep_time),
CONN_TICK_TO_SEC((t_bt_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_bt_sleep_cnt,
CONN_TICK_TO_SEC(t_gps_sleep_time),
CONN_TICK_TO_SEC((t_gps_sleep_time % CONN_32K_TICKS_PER_SEC)* 1000),
t_gps_sleep_cnt);
oplusConnSendUevent(mUevent);
}
#endif /* OPLUS_FEATURE_CONN_POWER_MONITOR */
}
consys_power_state();
round++;
/* reset after sleep time is accumulated. */
consys_reset_power_state();
consys_reset_power_state_mt6983();
return 0;
}
int consys_reset_power_state_mt6983(void)
{
return consys_power_state_dump(NULL, 0, 0);
}
int consys_power_state_dump_mt6983(char *buf, unsigned int size)
{
return consys_power_state_dump(buf, size, 1);
}
unsigned int consys_get_hw_ver_mt6983(void)
{
return CONN_HW_VER;
@ -645,9 +469,10 @@ static int calculate_thermal_temperature(int y)
t = (y - (data->thermal_b == 0 ? 0x38 : data->thermal_b)) *
(data->slop_molecule + 1866) / 1000 + const_offset;
if (t > PRINT_THERMAL_LOG_THRESHOLD)
pr_info("y=[%d] b=[%d] constOffset=[%d] [%d] [%d] => t=[%d]\n",
y, data->thermal_b, const_offset, data->slop_molecule, data->offset, t);
pr_info("y=[%d] b=[%d] constOffset=[%d] [%d] [%d] => t=[%d]\n",
y, data->thermal_b, const_offset, data->slop_molecule, data->offset,
t);
return t;
}
@ -712,11 +537,10 @@ int consys_thermal_query_mt6983(void)
CONSYS_REG_READ(CONN_REG_CONN_THERM_CTL_ADDR + thermal_dump_crs[i])) >= 0)
strncat(tmp_buf, tmp, strlen(tmp));
}
pr_info("[%s] efuse:[0x%08x][0x%08x][0x%08x][0x%08x] thermal dump: %s",
__func__, efuse0, efuse1, efuse2, efuse3, tmp_buf);
res = calculate_thermal_temperature(cal_val);
if (res > PRINT_THERMAL_LOG_THRESHOLD)
pr_info("[%s] efuse:[0x%08x][0x%08x][0x%08x][0x%08x] thermal dump: %s",
__func__, efuse0, efuse1, efuse2, efuse3, tmp_buf);
/* GPT2 disable */
CONSYS_REG_WRITE(addr + CONN_GPT2_CTRL_AP_EN, 0);
@ -781,122 +605,3 @@ static void consys_set_mcu_control_mt6983(int type, bool onoff)
else // Turn off
CONSYS_CLR_BIT(CONN_INFRA_SYSRAM_SW_CR_MCU_LOG_CONTROL, (0x1 << type));
}
static int consys_pre_cal_backup_mt6983(unsigned int offset, unsigned int size)
{
void __iomem* vir_addr = 0;
unsigned int expected_size = 0;
pr_info("[%s] emi base=0x%x offset=0x%x size=%d", __func__, gConEmiPhyBase, offset, size);
if ((size == 0) || ((offset & 0x3) != 0x0))
return 1;
if (mt6637_backup_data != NULL) {
kfree(mt6637_backup_data);
mt6637_backup_data = NULL;
}
/* Read CR number from EMI */
vir_addr = ioremap(gConEmiPhyBase + offset, 4);
if (vir_addr == NULL) {
pr_err("[%s] ioremap CR number fail", __func__);
return -ENOMEM;
}
mt6637_backup_cr_number = readl(vir_addr);
iounmap(vir_addr);
expected_size = sizeof(struct rf_cr_backup_data)*mt6637_backup_cr_number + 4;
if (size < expected_size) {
pr_err("[%s] cr number=%d, expected_size=0x%x size=0x%x", __func__, mt6637_backup_cr_number, expected_size, size);
mt6637_backup_cr_number = 0;
return 1;
}
mt6637_backup_data =
kmalloc(
sizeof(struct rf_cr_backup_data)*mt6637_backup_cr_number,
GFP_KERNEL);
if (mt6637_backup_data == NULL) {
pr_err("[%s] allocate fail");
return -ENOMEM;
}
vir_addr = ioremap(gConEmiPhyBase + offset + 4,
sizeof(struct rf_cr_backup_data)*mt6637_backup_cr_number);
if (vir_addr == NULL) {
pr_err("[%s] ioremap data fail", __func__);
return -ENOMEM;
}
memcpy_fromio(mt6637_backup_data, vir_addr,
sizeof(struct rf_cr_backup_data)*mt6637_backup_cr_number);
iounmap(vir_addr);
return 0;
}
int consys_pre_cal_restore_mt6983(void)
{
int i;
if (mt6637_backup_cr_number == 0 || mt6637_backup_data == NULL) {
pr_info("[%s] mt6637_backup_cr_number=%d mt6637_backup_data=%x",
__func__, mt6637_backup_cr_number, mt6637_backup_data);
return 1;
}
pr_info("[%s] mt6637_backup_cr_number=%d mt6637_backup_data=%x",
__func__, mt6637_backup_cr_number, mt6637_backup_data);
/* Acquire semaphore */
if (consys_sema_acquire_timeout_mt6983(CONN_SEMA_RFSPI_INDEX, CONN_SEMA_TIMEOUT) == CONN_SEMA_GET_FAIL) {
pr_err("[%s] Require semaphore fail\n", __func__);
return CONNINFRA_SPI_OP_FAIL;
}
/* Enable a-die top_ck en */
connsys_adie_top_ck_en_ctl_mt6983(true);
/* Enable WF clock
* ATOP 0xb04 0xfe000000
* ATOP 0xb08 0xe0000000
* ATOP 0xa04 0xffffffff
* ATOP 0xaf4 0xffffffff
*/
consys_spi_write_nolock_mt6983(SYS_SPI_TOP, 0xb04, 0xfe000000);
consys_spi_write_nolock_mt6983(SYS_SPI_TOP, 0xb08, 0xe0000000);
consys_spi_write_nolock_mt6983(SYS_SPI_TOP, 0xa04, 0xffffffff);
consys_spi_write_nolock_mt6983(SYS_SPI_TOP, 0xaf4, 0xffffffff);
/* Write CR back, SYS_SPI_WF & SYS_SPI_WF1 */
for (i = 0; i < mt6637_backup_cr_number; i++) {
consys_spi_write_nolock_mt6983(
SYS_SPI_WF,
mt6637_backup_data[i].addr,
mt6637_backup_data[i].value1);
}
for (i = 0; i < mt6637_backup_cr_number; i++) {
consys_spi_write_nolock_mt6983(
SYS_SPI_WF1,
mt6637_backup_data[i].addr,
mt6637_backup_data[i].value2);
}
/* Disable WF clock
* ATOP 0xb04 0x88000000
* ATOP 0xb08 0x00000000
* ATOP 0xa04 0x00000000
* ATOP 0xaf4 0x00000000
*/
consys_spi_write_nolock_mt6983(SYS_SPI_TOP, 0xb04, 0x88000000);
consys_spi_write_nolock_mt6983(SYS_SPI_TOP, 0xb08, 0x00000000);
consys_spi_write_nolock_mt6983(SYS_SPI_TOP, 0xa04, 0x00000000);
consys_spi_write_nolock_mt6983(SYS_SPI_TOP, 0xaf4, 0x00000000);
/* Release semaphore */
consys_sema_release_mt6983(CONN_SEMA_RFSPI_INDEX);
/* Disable a-die top ck en */
connsys_adie_top_ck_en_ctl_mt6983(false);
return 0;
}
static int consys_pre_cal_clean_data_mt6983(void)
{
if (mt6637_backup_data != NULL) {
kfree(mt6637_backup_data);
mt6637_backup_data = NULL;
}
mt6637_backup_cr_number = 0;
return 0;
}

82
drivers/misc/mediatek/connectivity/conninfra/platform/mt6983/mt6983_consys_reg.c
View file

@ -18,7 +18,7 @@
#include "osal.h"
#include "mt6983_pmic.h"
#define CONSYS_DUMP_BUF_SIZE 800
#define LOG_TMP_BUF_SZ 256
static int consys_reg_init(struct platform_device *pdev);
static int consys_reg_deinit(void);
@ -28,7 +28,6 @@ static int consys_check_reg_readable_for_coredump(void);
static int __consys_check_reg_readable(int check_type);
static int consys_is_consys_reg(unsigned int addr);
static int consys_is_bus_hang(void);
static void consys_print_platform_debug(void);
#endif
struct consys_base_addr conn_reg_mt6983;
@ -45,7 +44,6 @@ struct consys_reg_mng_ops g_dev_consys_reg_ops_mt6983 = {
};
static struct conn_debug_info_mt6983 *debug_info;
static char *debug_buf;
static const char* consys_base_addr_index_to_str[CONSYS_BASE_ADDR_MAX] = {
"infracfg_ao",
@ -81,16 +79,15 @@ int consys_is_consys_reg(unsigned int addr)
return 0;
}
#define CONSYS_DUMP_BUF_SIZE 512
static void consys_print_log(const char *title, struct conn_debug_info_mt6983 *info)
{
char buf[CONSYS_DUMP_BUF_SIZE];
char temp[13];
int i;
if (debug_buf == NULL)
return;
temp[0] = '\0';
if (snprintf(debug_buf, CONSYS_DUMP_BUF_SIZE, "%s", title) < 0) {
if (snprintf(buf, CONSYS_DUMP_BUF_SIZE, "%s", title) < 0) {
pr_notice("%s snprintf failed\n", __func__);
return;
}
@ -100,13 +97,9 @@ static void consys_print_log(const char *title, struct conn_debug_info_mt6983 *i
pr_notice("%s snprintf failed\n", __func__);
return;
}
if (strlen(debug_buf) + strlen(temp) < CONSYS_DUMP_BUF_SIZE)
strncat(debug_buf, temp, strlen(temp) + 1);
else
pr_notice("%s debug_buf len is not enough\n", __func__);
strncat(buf, temp, strlen(temp) + 1);
}
pr_info("%s\n", debug_buf);
pr_info("%s\n", buf);
}
static void consys_print_power_debug(int level)
@ -153,12 +146,11 @@ int consys_print_debug_mt6983(int level)
return 0;
}
consys_print_platform_debug();
if (debug_info == NULL) {
pr_notice("%s debug_info is NULL\n", __func__);
return -1;
}
consys_print_power_debug(level);
consys_print_bus_debug(level);
consys_pmic_debug_log_mt6983();
@ -216,11 +208,6 @@ static int consys_check_conninfra_on_domain(void)
return 1;
}
int consys_check_conninfra_on_domain_mt6983(void)
{
return consys_check_conninfra_on_domain();
}
static int consys_check_conninfra_off_domain(void)
{
unsigned int r;
@ -236,37 +223,6 @@ static int consys_check_conninfra_off_domain(void)
return 1;
}
static void consys_print_platform_debug(void)
{
void __iomem *addr = NULL;
unsigned int val[4];
/* gals dbg: 0x1020E804 */
/* slpport: 0x1021515C */
/* SI3: 0x10215160 */
/* ASL8: 0x10215168 */
addr = ioremap(0x1020E804, 0x4);
if (!addr) {
pr_notice("%s remap failed");
return;
}
val[0] = CONSYS_REG_READ(addr);
iounmap(addr);
addr = ioremap(0x10215150, 0x20);
if (!addr) {
pr_notice("%s remap failed");
return;
}
val[1] = CONSYS_REG_READ(addr + 0x0c);
val[2] = CONSYS_REG_READ(addr + 0x10);
val[3] = CONSYS_REG_READ(addr + 0x18);
iounmap(addr);
pr_info("%s 0x1020E804=0x%x,0x1021515C=0x%x,0x10215160=0x%x,0x10215168=0x%x",
__func__, val[0], val[1],val[2],val[3]);
}
static int __consys_check_reg_readable(int check_type)
{
// Type includes:
@ -289,10 +245,8 @@ static int __consys_check_reg_readable(int check_type)
return 0;
/* wake up conninfra to read off register */
if (consys_hw_force_conninfra_wakeup() != 0)
return 0;
wakeup_conninfra = 1;
consys_hw_force_conninfra_wakeup();
ret = 0;
}
@ -319,13 +273,7 @@ static void consys_debug_init_mt6983(void)
{
debug_info = (struct conn_debug_info_mt6983 *)osal_malloc(sizeof(struct conn_debug_info_mt6983));
if (debug_info == NULL) {
pr_notice("%s debug_info malloc failed\n", __func__);
return;
}
debug_buf = osal_malloc(CONSYS_DUMP_BUF_SIZE);
if (debug_buf == NULL) {
pr_notice("%s debug_buf malloc failed\n", __func__);
pr_notice("%s malloc failed\n", __func__);
return;
}
@ -334,15 +282,13 @@ static void consys_debug_init_mt6983(void)
static void consys_debug_deinit_mt6983(void)
{
if (debug_info != NULL) {
osal_free(debug_info);
debug_info = NULL;
if (debug_info == NULL) {
pr_notice("%s debug_info is NULL\n", __func__);
return;
}
if (debug_buf != NULL) {
osal_free(debug_buf);
debug_buf = NULL;
}
osal_free(debug_info);
debug_info = NULL;
consys_debug_deinit_mt6983_debug_gen();
}

383
drivers/misc/mediatek/connectivity/conninfra/platform/mt6983/mt6983_debug_gen.c
View file

@ -11,7 +11,7 @@
* It should not be modified by hand.
*
* Reference debug file,
* - [Lxxxn]connsys_power_debug.xlsx (Modified date: 2021-12-28)
* - [Lxxxn]connsys_power_debug.xlsx (Modified date: 2021-08-18)
* - [Lxxxn]conn_infra_bus_debug_ctrl.xlsx (Modified date: 2021-10-14)
*/
@ -30,16 +30,16 @@
void __iomem *vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 = NULL;
void __iomem *vir_addr_consys_dbg_gen_topckgen_base_mt6983 = NULL;
void __iomem *vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6983 = NULL;
void __iomem *vir_addr_consys_dbg_gen_conn_infra_sysram_base_offset_mt6983 = NULL;
void __iomem *vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6983 = NULL;
void __iomem *vir_addr_0x1804c000_mt6983 = NULL;
void consys_debug_init_mt6983_debug_gen(void)
{
vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 = ioremap(CONSYS_DBG_GEN_SRCLKENRC_BASE_ADDR, 0x77C);
vir_addr_consys_dbg_gen_topckgen_base_mt6983 = ioremap(CONSYS_DBG_GEN_TOPCKGEN_BASE_ADDR, 0x180);
vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6983 = ioremap(CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR, 0x41c);
vir_addr_consys_dbg_gen_conn_infra_sysram_base_offset_mt6983 = ioremap(CONSYS_DBG_GEN_CONN_INFRA_SYSRAM_BASE_OFFSET_ADDR, 0xBA4);
vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6983 = ioremap(CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR, 0x41c);
vir_addr_0x1804c000_mt6983 = ioremap(0x1804c000, 0xc);
}
@ -51,12 +51,12 @@ void consys_debug_deinit_mt6983_debug_gen(void)
if (vir_addr_consys_dbg_gen_topckgen_base_mt6983)
iounmap(vir_addr_consys_dbg_gen_topckgen_base_mt6983);
if (vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6983)
iounmap(vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6983);
if (vir_addr_consys_dbg_gen_conn_infra_sysram_base_offset_mt6983)
iounmap(vir_addr_consys_dbg_gen_conn_infra_sysram_base_offset_mt6983);
if (vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6983)
iounmap(vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6983);
if (vir_addr_0x1804c000_mt6983)
iounmap(vir_addr_0x1804c000_mt6983);
}
@ -159,336 +159,234 @@ void consys_print_power_debug_dbg_level_0_mt6983_debug_gen(
/* A2 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A2", 0x1C00D000 + CONSYS_DBG_GEN_FSM_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_FSM_STA_0_OFFSET_ADDR));
/* A3 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A3", 0x1C00D000 + CONSYS_DBG_GEN_CMD_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_CMD_STA_0_OFFSET_ADDR));
/* A4 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A4", 0x1C00D000 + CONSYS_DBG_GEN_CMD_STA_1_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_CMD_STA_1_OFFSET_ADDR));
/* A5 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A5", 0x1C00D000 + CONSYS_DBG_GEN_SPI_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SPI_STA_0_OFFSET_ADDR));
/* A6 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A6", 0x1C00D000 + CONSYS_DBG_GEN_PI_PO_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_PI_PO_STA_0_OFFSET_ADDR));
/* A7 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A7", 0x1C00D000 + CONSYS_DBG_GEN_M00_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M00_REQ_STA_0_OFFSET_ADDR));
/* A8 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A8", 0x1C00D000 + CONSYS_DBG_GEN_M01_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M01_REQ_STA_0_OFFSET_ADDR));
/* A9 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A9", 0x1C00D000 + CONSYS_DBG_GEN_M02_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M02_REQ_STA_0_OFFSET_ADDR));
/* A10 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A10", 0x1C00D000 + CONSYS_DBG_GEN_M03_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M03_REQ_STA_0_OFFSET_ADDR));
/* A11 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A11", 0x1C00D000 + CONSYS_DBG_GEN_M04_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M04_REQ_STA_0_OFFSET_ADDR));
/* A12 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A12", 0x1C00D000 + CONSYS_DBG_GEN_M05_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M05_REQ_STA_0_OFFSET_ADDR));
/* A13 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A13", 0x1C00D000 + CONSYS_DBG_GEN_M06_REQ_STA_0_OFFSET_ADDR,
"A2", 0x1C00D000 + CONSYS_DBG_GEN_M06_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M06_REQ_STA_0_OFFSET_ADDR));
/* A14 */
/* A3 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A14", 0x1C00D000 + CONSYS_DBG_GEN_M07_REQ_STA_0_OFFSET_ADDR,
"A3", 0x1C00D000 + CONSYS_DBG_GEN_M07_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M07_REQ_STA_0_OFFSET_ADDR));
/* A15 */
/* A4 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A15", 0x1C00D000 + CONSYS_DBG_GEN_M08_REQ_STA_0_OFFSET_ADDR,
"A4", 0x1C00D000 + CONSYS_DBG_GEN_M08_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M08_REQ_STA_0_OFFSET_ADDR));
/* A16 */
/* A5 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A16", 0x1C00D000 + CONSYS_DBG_GEN_M09_REQ_STA_0_OFFSET_ADDR,
"A5", 0x1C00D000 + CONSYS_DBG_GEN_M09_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M09_REQ_STA_0_OFFSET_ADDR));
/* A17 */
/* A6 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A17", 0x1C00D000 + CONSYS_DBG_GEN_M10_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M10_REQ_STA_0_OFFSET_ADDR));
/* A18 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A18", 0x1C00D000 + CONSYS_DBG_GEN_M11_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M11_REQ_STA_0_OFFSET_ADDR));
/* A19 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A19", 0x1C00D000 + CONSYS_DBG_GEN_M12_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M12_REQ_STA_0_OFFSET_ADDR));
/* A20 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A20", 0x1C00D000 + CONSYS_DBG_GEN_M13_REQ_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_M13_REQ_STA_0_OFFSET_ADDR));
/* A21 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A21", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_STA_0_OFFSET_ADDR));
/* A21 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A21", 0x1C00D000 + CONSYS_DBG_GEN_SPMI_P_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SPMI_P_STA_0_OFFSET_ADDR));
/* A22 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A22", 0x1C001000 + CONSYS_DBG_GEN_CONN_PWR_CON_OFFSET_ADDR,
"A6", 0x1C001000 + CONSYS_DBG_GEN_CONN_PWR_CON_OFFSET_ADDR,
CONSYS_REG_READ(SPM_REG_BASE +
CONSYS_DBG_GEN_CONN_PWR_CON_OFFSET_ADDR));
/* A23 */
/* A7 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A23", 0x10000000 + 0x180,
"A7", 0x10000000 + 0x180,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_topckgen_base_mt6983 + 0x180));
/* A24 */
/* A8 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A24", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_0_LSB_OFFSET_ADDR,
"A8", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_0_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_0_LSB_OFFSET_ADDR));
/* A25 */
/* A9 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A25", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_0_MSB_OFFSET_ADDR,
"A9", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_0_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_0_MSB_OFFSET_ADDR));
/* A26 */
/* A10 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A26", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_1_LSB_OFFSET_ADDR,
"A10", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_1_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_1_LSB_OFFSET_ADDR));
/* A27 */
/* A11 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A27", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_1_MSB_OFFSET_ADDR,
"A11", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_1_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_1_MSB_OFFSET_ADDR));
/* A28 */
/* A12 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A28", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_2_LSB_OFFSET_ADDR,
"A12", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_2_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_2_LSB_OFFSET_ADDR));
/* A29 */
/* A13 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A29", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_2_MSB_OFFSET_ADDR,
"A13", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_2_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_2_MSB_OFFSET_ADDR));
/* A30 */
/* A14 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A30", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_3_LSB_OFFSET_ADDR,
"A14", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_3_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_3_LSB_OFFSET_ADDR));
/* A31 */
/* A15 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A31", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_3_MSB_OFFSET_ADDR,
"A15", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_3_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_3_MSB_OFFSET_ADDR));
/* A32 */
/* A16 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A32", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_4_LSB_OFFSET_ADDR,
"A16", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_4_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_4_LSB_OFFSET_ADDR));
/* A33 */
/* A17 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A33", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_4_MSB_OFFSET_ADDR,
"A17", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_4_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_4_MSB_OFFSET_ADDR));
/* A34 */
/* A18 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A34", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_5_LSB_OFFSET_ADDR,
"A18", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_5_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_5_LSB_OFFSET_ADDR));
/* A35 */
/* A19 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A35", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_5_MSB_OFFSET_ADDR,
"A19", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_5_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_5_MSB_OFFSET_ADDR));
/* A36 */
/* A20 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A36", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_6_LSB_OFFSET_ADDR,
"A20", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_6_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_6_LSB_OFFSET_ADDR));
/* A37 */
/* A21 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A37", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_6_MSB_OFFSET_ADDR,
"A21", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_6_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_6_MSB_OFFSET_ADDR));
/* A38 */
/* A22 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A38", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_7_LSB_OFFSET_ADDR,
"A22", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_7_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_7_LSB_OFFSET_ADDR));
/* A39 */
/* A23 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A39", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_7_MSB_OFFSET_ADDR,
"A23", 0x1C00D000 + CONSYS_DBG_GEN_DEBUG_TRACE_7_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_DEBUG_TRACE_7_MSB_OFFSET_ADDR));
/* A40 */
/* A24 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A40", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_LSB_OFFSET_ADDR,
"A24", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_LSB_OFFSET_ADDR));
/* A41 */
/* A25 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A41", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_MSB_OFFSET_ADDR,
"A25", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_0_MSB_OFFSET_ADDR));
/* A42 */
/* A26 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A42", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_LSB_OFFSET_ADDR,
"A26", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_LSB_OFFSET_ADDR));
/* A43 */
/* A27 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A43", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_MSB_OFFSET_ADDR,
"A27", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_1_MSB_OFFSET_ADDR));
/* A44 */
/* A28 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A44", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_LSB_OFFSET_ADDR,
"A28", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_LSB_OFFSET_ADDR));
/* A45 */
/* A29 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A45", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_MSB_OFFSET_ADDR,
"A29", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_2_MSB_OFFSET_ADDR));
/* A46 */
/* A30 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A46", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_LSB_OFFSET_ADDR,
"A30", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_LSB_OFFSET_ADDR));
/* A47 */
/* A31 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A47", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_MSB_OFFSET_ADDR,
"A31", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_3_MSB_OFFSET_ADDR));
/* A48 */
/* A32 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A48", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_LSB_OFFSET_ADDR,
"A32", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_LSB_OFFSET_ADDR));
/* A49 */
/* A33 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A49", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_MSB_OFFSET_ADDR,
"A33", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_4_MSB_OFFSET_ADDR));
/* A50 */
/* A34 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A50", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_LSB_OFFSET_ADDR,
"A34", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_LSB_OFFSET_ADDR));
/* A51 */
/* A35 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A51", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_MSB_OFFSET_ADDR,
"A35", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_5_MSB_OFFSET_ADDR));
/* A52 */
/* A36 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A52", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_LSB_OFFSET_ADDR,
"A36", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_LSB_OFFSET_ADDR));
/* A53 */
/* A37 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A53", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_MSB_OFFSET_ADDR,
"A37", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_6_MSB_OFFSET_ADDR));
/* A54 */
/* A38 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A54", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_LSB_OFFSET_ADDR,
"A38", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_LSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_LSB_OFFSET_ADDR));
/* A55 */
/* A39 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A55", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_MSB_OFFSET_ADDR,
"A39", 0x1C00D000 + CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_MSB_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_SYS_TIMER_LATCH_7_MSB_OFFSET_ADDR));
/* A56 */
/* A40 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_0_info,
"A56", 0x1C00D000 + CONSYS_DBG_GEN_CMD_STA_0_OFFSET_ADDR,
"A40", 0x1C00D000 + CONSYS_DBG_GEN_CMD_STA_0_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_srclkenrc_base_mt6983 +
CONSYS_DBG_GEN_CMD_STA_0_OFFSET_ADDR));
}
@ -505,12 +403,6 @@ void consys_print_power_debug_dbg_level_1_mt6983_debug_gen(
if (level < 1)
return;
if (!vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6983) {
pr_notice("vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6983(%x) ioremap fail\n",
CONSYS_DBG_GEN_CONN_DBG_CTL_BASE_ADDR);
return;
}
if (CONN_HOST_CSR_TOP_BASE == 0) {
pr_notice("CONN_HOST_CSR_TOP_BASE is not defined\n");
return;
@ -553,74 +445,8 @@ void consys_print_power_debug_dbg_level_1_mt6983_debug_gen(
CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR));
/* B3 */
CONSYS_REG_WRITE_MASK(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR, 0x1, 0x7);
update_debug_write_info_mt6983_debug_gen(pdbg_level_1_info,
"B3", 0x18060000 + CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR,
0, 2, 0x1);
update_debug_read_info_mt6983_debug_gen(pdbg_level_1_info,
NULL, 0x18060000 + CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR,
CONSYS_REG_READ(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR));
/* B4 */
CONSYS_REG_WRITE_MASK(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR, 0x2, 0x7);
update_debug_write_info_mt6983_debug_gen(pdbg_level_1_info,
"B4", 0x18060000 + CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR,
0, 2, 0x2);
update_debug_read_info_mt6983_debug_gen(pdbg_level_1_info,
NULL, 0x18060000 + CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR,
CONSYS_REG_READ(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR));
/* B5 */
CONSYS_REG_WRITE_MASK(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR, 0x3, 0x7);
update_debug_write_info_mt6983_debug_gen(pdbg_level_1_info,
"B5", 0x18060000 + CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR,
0, 2, 0x3);
update_debug_read_info_mt6983_debug_gen(pdbg_level_1_info,
NULL, 0x18060000 + CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR,
CONSYS_REG_READ(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR));
/* B6 */
CONSYS_REG_WRITE_MASK(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR, 0x6, 0x7);
update_debug_write_info_mt6983_debug_gen(pdbg_level_1_info,
"B6", 0x18060000 + CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR,
0, 2, 0x6);
update_debug_read_info_mt6983_debug_gen(pdbg_level_1_info,
NULL, 0x18060000 + CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR,
CONSYS_REG_READ(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR));
/* B7 */
CONSYS_REG_WRITE_MASK(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR, 0x7, 0x7);
update_debug_write_info_mt6983_debug_gen(pdbg_level_1_info,
"B7", 0x18060000 + CONSYS_DBG_GEN_CR_CONN_INFRA_CFG_ON_DBG_MUX_SEL_OFFSET_ADDR,
0, 2, 0x7);
update_debug_read_info_mt6983_debug_gen(pdbg_level_1_info,
NULL, 0x18060000 + CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR,
CONSYS_REG_READ(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CONN_INFRA_CFG_ON_DBG_OFFSET_ADDR));
/* B8 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_1_info,
"B8", 0x18023000 + CONSYS_DBG_GEN_CONN_INFRA_MONFLAG_OUT_OFFSET_ADDR,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_conn_dbg_ctl_base_mt6983 +
CONSYS_DBG_GEN_CONN_INFRA_MONFLAG_OUT_OFFSET_ADDR));
/* B9 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_1_info,
"B9", 0x18060000 + CONSYS_DBG_GEN_CONNSYS_PWR_STATES_OFFSET_ADDR,
"B3", 0x18060000 + CONSYS_DBG_GEN_CONNSYS_PWR_STATES_OFFSET_ADDR,
CONSYS_REG_READ(CONN_HOST_CSR_TOP_BASE +
CONSYS_DBG_GEN_CONNSYS_PWR_STATES_OFFSET_ADDR));
}
@ -668,11 +494,6 @@ void consys_print_power_debug_dbg_level_2_mt6983_debug_gen(
return;
}
if (CONN_RF_SPI_MST_REG_BASE == 0) {
pr_notice("CONN_RF_SPI_MST_REG_BASE is not defined\n");
return;
}
/* C0 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_2_info,
"C0", 0x18011000 + CONSYS_DBG_GEN_PLL_STATUS_OFFSET_ADDR,
@ -827,42 +648,6 @@ void consys_print_power_debug_dbg_level_2_mt6983_debug_gen(
update_debug_read_info_mt6983_debug_gen(pdbg_level_2_info,
"C22", 0x18050000 + 0xBA4,
CONSYS_REG_READ(vir_addr_consys_dbg_gen_conn_infra_sysram_base_offset_mt6983 + 0xBA4));
/* C23 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_2_info,
"C23", 0x18042000 + CONSYS_DBG_GEN_SPI_STA_OFFSET_ADDR,
CONSYS_REG_READ(CONN_RF_SPI_MST_REG_BASE +
CONSYS_DBG_GEN_SPI_STA_OFFSET_ADDR));
/* C24 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_2_info,
"C24", 0x18042000 + CONSYS_DBG_GEN_SPI_TOP_ADDR_OFFSET_ADDR,
CONSYS_REG_READ(CONN_RF_SPI_MST_REG_BASE +
CONSYS_DBG_GEN_SPI_TOP_ADDR_OFFSET_ADDR));
/* C25 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_2_info,
"C25", 0x18042000 + CONSYS_DBG_GEN_SPI_TOP_WDAT_OFFSET_ADDR,
CONSYS_REG_READ(CONN_RF_SPI_MST_REG_BASE +
CONSYS_DBG_GEN_SPI_TOP_WDAT_OFFSET_ADDR));
/* C26 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_2_info,
"C26", 0x18042000 + CONSYS_DBG_GEN_SPI_TOP_RDAT_OFFSET_ADDR,
CONSYS_REG_READ(CONN_RF_SPI_MST_REG_BASE +
CONSYS_DBG_GEN_SPI_TOP_RDAT_OFFSET_ADDR));
/* C27 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_2_info,
"C27", 0x18042000 + CONSYS_DBG_GEN_SPI_HSCK_CTL_OFFSET_ADDR,
CONSYS_REG_READ(CONN_RF_SPI_MST_REG_BASE +
CONSYS_DBG_GEN_SPI_HSCK_CTL_OFFSET_ADDR));
/* C28 */
update_debug_read_info_mt6983_debug_gen(pdbg_level_2_info,
"C28", 0x18042000 + CONSYS_DBG_GEN_SPI_CRTL_OFFSET_ADDR,
CONSYS_REG_READ(CONN_RF_SPI_MST_REG_BASE +
CONSYS_DBG_GEN_SPI_CRTL_OFFSET_ADDR));
}
void consys_print_bus_debug_dbg_level_1_mt6983_debug_gen(

73
drivers/misc/mediatek/connectivity/conninfra/platform/mt6983/mt6983_pmic.c
View file

@ -154,10 +154,10 @@ int consys_plt_pmic_get_from_dts_mt6983(struct platform_device *pdev, struct con
int consys_plt_pmic_common_power_ctrl_mt6983(unsigned int enable)
{
int ret = 0;
#ifdef CONFIG_FPGA_EARLY_PORTING
pr_info("[%s] not support on FPGA", __func__);
#else
int ret;
int sleep_mode;
if (enable) {
@ -185,25 +185,21 @@ int consys_plt_pmic_common_power_ctrl_mt6983(unsigned int enable)
msleep(1);
/* set PMIC VCN13 LDO SW_EN = 0, SW_LP =0 (sw disable) */
regulator_set_mode(reg_VCN13, REGULATOR_MODE_NORMAL);
ret = regulator_disable(reg_VCN13);
if (ret)
pr_notice("%s regulator_disable err: %d", __func__, ret);
regulator_disable(reg_VCN13);
/* set PMIC VRFIO18 LDO SW_EN = 0, SW_LP =0 (sw disable) */
regulator_set_mode(reg_VRFIO18, REGULATOR_MODE_NORMAL);
sleep_mode = consys_get_sleep_mode_mt6983();
if (sleep_mode == 1) {
ret = regulator_disable(reg_VRFIO18);
if (ret)
pr_notice("%s regulator_disable err: %d", __func__, ret);
}
if (sleep_mode == 1)
regulator_disable(reg_VRFIO18);
/* Set buckboost to 3.45V (for VCN33_1 & VCN33_2) */
if (reg_buckboost)
if (reg_buckboost) {
regulator_set_voltage(reg_buckboost, 3450000, 3450000);
pr_info("Set buckboost to 3.45V\n");
}
}
#endif
return ret;
return 0;
}
static void consys_pmic_regmap_set_value(struct regmap *rmap, unsigned int address,
@ -224,7 +220,6 @@ static void consys_pmic_regmap_set_value(struct regmap *rmap, unsigned int addre
int consys_plt_pmic_common_power_low_power_mode_mt6983(unsigned int enable)
{
int ret = 0;
#ifdef CONFIG_FPGA_EARLY_PORTING
pr_info("[%s] not support on FPGA", __func__);
#else
@ -264,9 +259,7 @@ int consys_plt_pmic_common_power_low_power_mode_mt6983(unsigned int enable)
regulator_set_mode(reg_VRFIO18, REGULATOR_MODE_IDLE);
} else {
/* set PMIC VRFIO18 LDO SW_EN = 0, SW_LP =0 */
ret = regulator_disable(reg_VRFIO18);
if (ret)
pr_notice("%s regulator_disable err: %d", __func__, ret);
regulator_disable(reg_VRFIO18);
regulator_set_mode(reg_VRFIO18, REGULATOR_MODE_NORMAL); /* SW_LP = 0 */
}
@ -327,7 +320,7 @@ int consys_plt_pmic_common_power_low_power_mode_mt6983(unsigned int enable)
}
consys_pmic_vant18_power_ctl_mt6983(enable);
#endif
return ret;
return 0;
}
int consys_plt_pmic_wifi_power_ctrl_mt6983(unsigned int enable)
@ -394,7 +387,6 @@ static int consys_pmic_vcn33_1_power_ctl_mt6983_lg(bool enable)
{
struct regmap *r = g_regmap_mt6373;
static int enable_count = 0;
int ret;
/* In legacy mode, VCN33_1 should be turned on either WIFI or BT is on */
@ -411,10 +403,8 @@ static int consys_pmic_vcn33_1_power_ctl_mt6983_lg(bool enable)
}
if (enable_count == 0) {
ret = regulator_disable(reg_VCN33_1);
if (ret)
pr_notice("%s regulator_disable err: %d", __func__, ret);
return ret;
regulator_disable(reg_VCN33_1);
return 0;
}
/* vcn33_1 is already on in these two cases */
@ -431,24 +421,19 @@ static int consys_pmic_vcn33_1_power_ctl_mt6983_lg(bool enable)
/* 2. set PMIC VCN33_1 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =0 */
regulator_set_mode(reg_VCN33_1, REGULATOR_MODE_NORMAL);
ret = regulator_enable(reg_VCN33_1);
if (ret)
pr_notice("%s regulator_enable err: %d", __func__, ret);
regulator_enable(reg_VCN33_1);
return ret;
return 0;
}
static int consys_pmic_vcn33_2_power_ctl_mt6983_lg(bool enable)
{
struct regmap *r = g_regmap_mt6373;
int ret = 0;
if (!enable) {
ret = regulator_disable(reg_VCN33_2);
if (ret)
pr_notice("%s regulator_disable err: %d", __func__, ret);
} else {
if (!enable)
regulator_disable(reg_VCN33_2);
else {
/* 1. set PMIC VCN33_2 LDO PMIC HW mode control by SRCCLKENA0 */
/* 1.1. set PMIC VCN33_2 LDO op_mode = 1 */
/* 1.2. set PMIC VCN33_2 LDO HW_OP_EN = 1, HW_OP_CFG = 0 */
@ -458,11 +443,9 @@ static int consys_pmic_vcn33_2_power_ctl_mt6983_lg(bool enable)
/* 2. set PMIC VCN33_2 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =0 */
regulator_set_mode(reg_VCN33_2, REGULATOR_MODE_NORMAL);
ret = regulator_enable(reg_VCN33_2);
if (ret)
pr_notice("%s regulator_enable err: %d", __func__, ret);
regulator_enable(reg_VCN33_2);
}
return ret;
return 0;
}
static int consys_pmic_vcn33_2_power_ctl_mt6983_rc(bool enable)
@ -488,17 +471,13 @@ static int consys_pmic_vcn33_2_power_ctl_mt6983_rc(bool enable)
static int consys_pmic_vant18_power_ctl_mt6983(bool enable)
{
struct regmap *r = g_regmap_mt6373;
int ret = 0;
if (!enable) {
/* 1. VANT18 will be set to SW_EN=1 only in legacy momde. */
/* 2. VANT18 might not be enabled because power on fail before low power control is executed. */
if (consys_is_rc_mode_enable_mt6983() == 0 && regulator_is_enabled(reg_VANT18)) {
ret = regulator_disable(reg_VANT18);
if (ret)
pr_notice("%s regulator_disable err:%d", __func__, ret);
}
return ret;
if (consys_is_rc_mode_enable_mt6983() == 0 && regulator_is_enabled(reg_VANT18))
regulator_disable(reg_VANT18);
return 0;
}
if (consys_is_rc_mode_enable_mt6983()) {
@ -521,12 +500,10 @@ static int consys_pmic_vant18_power_ctl_mt6983(bool enable)
/* 2. set PMIC VANT18 LDO SW_OP_EN =1, SW_EN = 1, SW_LP =0 */
regulator_set_mode(reg_VANT18, REGULATOR_MODE_NORMAL);
ret = regulator_enable(reg_VANT18);
if (ret)
pr_notice("%s regulator_enable err: %d", __func__, ret);
regulator_enable(reg_VANT18);
}
return ret;
return 0;
}
static void dump_adie_cr(enum sys_spi_subsystem subsystem, const unsigned int *adie_cr, int num, char *title)
@ -636,7 +613,7 @@ void consys_pmic_debug_log_mt6983(void)
{
struct regmap *r = g_regmap_mt6363;
struct regmap *r2 = g_regmap_mt6373;
int vcn13 = 0, vrfio18 = 0, vcn33_1 = 0, vcn33_2 = 0, vant18 = 0;
int vcn13, vrfio18, vcn33_1, vcn33_2, vant18;
if (!r || !r2) {
pr_notice("%s regmap is NULL\n", __func__);

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