755 lines
21 KiB
C
755 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Michael Hsiao <michael.hsiao@mediatek.com>
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*/
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/*******************************************************************************
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*
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* Filename:
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* ---------
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* mt_soc_pcm_i2s0.c
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*
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* Project:
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* --------
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* Audio Driver Kernel Function
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*
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* Description:
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* ------------
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* Audio i2s0 playback
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*
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* Author:
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* -------
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* Chipeng Chang
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*
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*------------------------------------------------------------------------------
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*
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*
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******************************************************************************
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*/
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/*****************************************************************************
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* C O M P I L E R F L A G S
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*****************************************************************************/
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/*****************************************************************************
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* E X T E R N A L R E F E R E N C E S
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*****************************************************************************/
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#include "mtk-auddrv-afe.h"
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#include "mtk-auddrv-ana.h"
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#include "mtk-auddrv-clk.h"
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#include "mtk-auddrv-common.h"
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#include "mtk-auddrv-def.h"
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#include "mtk-auddrv-kernel.h"
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#include "mtk-soc-afe-control.h"
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#include "mtk-soc-pcm-common.h"
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#include "mtk-soc-pcm-platform.h"
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#include "mtk-auddrv-gpio.h"
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#include <linux/dma-mapping.h>
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static struct afe_mem_control_t *pI2s0MemControl;
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static struct device *mDev;
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/*
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* function implementation
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*/
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static int mtk_i2s0_probe(struct platform_device *pdev);
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static int mtk_pcm_i2s0_close(struct snd_pcm_substream *substream);
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static int mtk_afe_i2s0_component_probe(struct snd_soc_component *component);
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int mtk_soc_always_hd;
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int extcodec_echoref_control;
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static int mi2s0_sidegen_control;
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static int hdoutput_control;
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const char *const i2s0_SIDEGEN[] = {"Off", "On8000", "On16000",
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"On32000", "On44100", "On48000",
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"On96000", "On192000"};
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const char *const i2s0_HD_output[] = {"Off", "On"};
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const char *const ExtCodec_EchoRef_Routing[] = {"Off", "MD1", "MD3", "SCP"};
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static const struct soc_enum Audio_i2s0_Enum[] = {
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SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(i2s0_SIDEGEN), i2s0_SIDEGEN),
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SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(i2s0_HD_output), i2s0_HD_output),
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SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ExtCodec_EchoRef_Routing),
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ExtCodec_EchoRef_Routing),
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};
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static int Audio_i2s0_SideGen_Get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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ucontrol->value.integer.value[0] = mi2s0_sidegen_control;
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return 0;
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}
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static int Audio_i2s0_SideGen_Set(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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bool ret = false;
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static int samplerate;
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unsigned int u32AudioI2sOut = 0;
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unsigned int u32Audio2ndI2sIn = 0;
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AudDrv_Clk_On();
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if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(i2s0_SIDEGEN)) {
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pr_err("return -EINVAL\n");
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return -EINVAL;
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}
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mi2s0_sidegen_control = ucontrol->value.integer.value[0];
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/* Config smart pa I2S pin */
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AudDrv_GPIO_SMARTPA_Select(mi2s0_sidegen_control > 0 ? 1 : 0);
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pr_debug(
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"%s(), sidegen = %d, hdoutput = %d, extcodec_echoref = %d, always_hd = %d\n",
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__func__, mi2s0_sidegen_control, hdoutput_control,
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extcodec_echoref_control, mtk_soc_always_hd);
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/* Set SmartPa i2s by platform. Return false if no platform implement,
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* then use default i2s3/0.
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*/
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if (get_afe_platform_ops()->set_smartpa_i2s != NULL) {
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ret = get_afe_platform_ops()->set_smartpa_i2s(
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mi2s0_sidegen_control, hdoutput_control,
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extcodec_echoref_control, mtk_soc_always_hd);
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goto i2s_config_done;
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}
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if (mi2s0_sidegen_control) {
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/* Phone call echo ref, speaker mode connection*/
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switch (extcodec_echoref_control) {
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case 1:
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/* MD1 connection */
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SetIntfConnection(
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Soc_Aud_InterCon_Connection,
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Soc_Aud_AFE_IO_Block_MODEM_PCM_2_I_CH1,
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Soc_Aud_AFE_IO_Block_I2S3);
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SetIntfConnection(
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Soc_Aud_InterCon_Connection,
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Soc_Aud_AFE_IO_Block_I2S0_CH1,
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Soc_Aud_AFE_IO_Block_MODEM_PCM_2_O_CH4);
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break;
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case 2:
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/* MD3 connection */
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SetIntfConnection(
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Soc_Aud_InterCon_Connection,
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Soc_Aud_AFE_IO_Block_MODEM_PCM_1_I_CH1,
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Soc_Aud_AFE_IO_Block_I2S3);
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SetIntfConnection(
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Soc_Aud_InterCon_Connection,
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Soc_Aud_AFE_IO_Block_I2S0_CH1,
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Soc_Aud_AFE_IO_Block_MODEM_PCM_1_O_CH4);
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break;
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case 3:
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/* SCP IV data */
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SetIntfConnection(Soc_Aud_InterCon_Connection,
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Soc_Aud_AFE_IO_Block_I2S0,
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get_usage_digital_block_io
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(AUDIO_USAGE_SCP_SPK_IV_DATA));
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break;
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default:
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break;
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}
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switch (mi2s0_sidegen_control) {
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case 1:
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samplerate = 8000;
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break;
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case 2:
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samplerate = 16000;
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break;
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case 3:
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samplerate = 32000;
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break;
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case 4:
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samplerate = 44100;
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break;
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case 5:
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samplerate = 48000;
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break;
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case 6:
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samplerate = 96000;
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break;
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case 7:
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samplerate = 192000;
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break;
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default:
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pr_err("%s, sidegen_control error, return -EINVAL\n",
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__func__);
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return false;
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}
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AudDrv_Clk_On();
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if (!mtk_soc_always_hd) {
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EnableALLbySampleRate(samplerate);
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EnableAPLLTunerbySampleRate(samplerate);
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}
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/* I2S0 clock-gated */
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Afe_Set_Reg(AUDIO_TOP_CON1, 0x1 << 4, 0x1 << 4);
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/* I2S sample rate Control */
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SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S,
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samplerate);
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/* I2S0 Input Control */
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SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_2,
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true);
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u32Audio2ndI2sIn |= (Soc_Aud_LR_SWAP_NO_SWAP << 31);
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u32Audio2ndI2sIn |=
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(hdoutput_control ? Soc_Aud_LOW_JITTER_CLOCK
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: Soc_Aud_NORMAL_CLOCK)
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<< 12;
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u32Audio2ndI2sIn |=
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(Soc_Aud_I2S_IN_PAD_SEL_I2S_IN_FROM_IO_MUX
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<< 28);
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u32Audio2ndI2sIn |= (Soc_Aud_INV_LRCK_NO_INVERSE << 5);
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u32Audio2ndI2sIn |= (Soc_Aud_I2S_FORMAT_I2S << 3);
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u32Audio2ndI2sIn |= (Soc_Aud_I2S_WLEN_WLEN_16BITS << 1);
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Afe_Set_Reg(AFE_I2S_CON, u32Audio2ndI2sIn, MASK_ALL);
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/* I2S3 clock-gated */
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Afe_Set_Reg(AUDIO_TOP_CON1, 0x1 << 7, 0x1 << 7);
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/* I2S3 Input Control */
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SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, true);
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u32AudioI2sOut =
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SampleRateTransform(samplerate,
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Soc_Aud_Digital_Block_I2S_OUT_2)
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<< 8;
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u32AudioI2sOut |= Soc_Aud_I2S_FORMAT_I2S
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<< 3; /* us3 I2s format */
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u32AudioI2sOut |= Soc_Aud_I2S_WLEN_WLEN_16BITS
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<< 1; /* 16 BITS */
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u32AudioI2sOut |= (hdoutput_control ? Soc_Aud_LOW_JITTER_CLOCK
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: Soc_Aud_NORMAL_CLOCK)
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<< 12;
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Afe_Set_Reg(AFE_I2S_CON3, u32AudioI2sOut,
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AFE_MASK_ALL); /* set I2S3 configuration */
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/* Clear I2S0 clock-gated */
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Afe_Set_Reg(AUDIO_TOP_CON1, 0 << 4, 0x1 << 4);
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/* Enable I2S0 */
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Set2ndI2SEnable(true);
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pr_debug(
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"%s(), Turn on. AFE_I2S_CON0=0x%x, AFE_DAC_CON1=0x%x",
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__func__, Afe_Get_Reg(AFE_I2S_CON),
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Afe_Get_Reg(AFE_DAC_CON1));
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/* Clear I2S3 clock-gated */
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Afe_Set_Reg(AUDIO_TOP_CON1, 0 << 7, 0x1 << 7);
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/* Enable I2S3 */
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Set2ndI2SOutEnable(true);
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/* pr_debug("%s(), Turn on. AFE_I2S_CON3=0x%x\n", __func__,
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* Afe_Get_Reg(AFE_I2S_CON3));
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*/
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EnableAfe(true);
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} else {
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if (extcodec_echoref_control > 0) {
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SetIntfConnection(
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Soc_Aud_InterCon_DisConnect,
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Soc_Aud_AFE_IO_Block_I2S0_CH1,
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Soc_Aud_AFE_IO_Block_MODEM_PCM_1_O_CH4);
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SetIntfConnection(
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Soc_Aud_InterCon_DisConnect,
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Soc_Aud_AFE_IO_Block_I2S0_CH1,
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Soc_Aud_AFE_IO_Block_MODEM_PCM_2_O_CH4);
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SetIntfConnection(Soc_Aud_InterCon_DisConnect,
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Soc_Aud_AFE_IO_Block_I2S0,
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get_usage_digital_block_io
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(AUDIO_USAGE_SCP_SPK_IV_DATA));
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}
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SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_2,
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false);
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SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, false);
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if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) ==
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false) {
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Set2ndI2SOutEnable(false); /* Disable I2S3 */
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udelay(20);
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Afe_Set_Reg(AUDIO_TOP_CON1, 0x1 << 7,
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0x1 << 7); /* I2S3 clock-gated */
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if (GetMemoryPathEnable(
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Soc_Aud_Digital_Block_I2S_IN_2) == false) {
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Set2ndI2SEnable(false); /* Disable I2S0 */
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udelay(20);
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Afe_Set_Reg(AUDIO_TOP_CON1, 0x1 << 4,
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0x1 << 4); /* I2S0 clock-gated */
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}
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SetIntfConnection(
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Soc_Aud_InterCon_DisConnect,
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Soc_Aud_AFE_IO_Block_MODEM_PCM_2_I_CH1,
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Soc_Aud_AFE_IO_Block_I2S3);
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SetIntfConnection(
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Soc_Aud_InterCon_DisConnect,
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Soc_Aud_AFE_IO_Block_MODEM_PCM_1_I_CH1,
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Soc_Aud_AFE_IO_Block_I2S3);
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pr_debug(
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"%s(), Turn off. AFE_I2S_CON=0x%x, AFE_I2S_CON3=0x%x\n",
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__func__, Afe_Get_Reg(AFE_I2S_CON),
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Afe_Get_Reg(AFE_I2S_CON3));
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}
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if (!mtk_soc_always_hd) {
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DisableAPLLTunerbySampleRate(samplerate);
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DisableALLbySampleRate(samplerate);
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}
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EnableAfe(false);
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AudDrv_Clk_Off();
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}
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i2s_config_done:
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AudDrv_Clk_Off();
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return 0;
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}
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static int audio_always_hd_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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pr_debug("%s(), mtk_soc_always_hd %d\n", __func__, mtk_soc_always_hd);
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ucontrol->value.integer.value[0] = mtk_soc_always_hd;
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return 0;
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}
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static int audio_always_hd_set(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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pr_debug("%s(), mtk_soc_always_hd %d\n", __func__, mtk_soc_always_hd);
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if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(i2s0_HD_output)) {
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pr_err("return -EINVAL\n");
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return -EINVAL;
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}
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mtk_soc_always_hd = ucontrol->value.integer.value[0];
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return 0;
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}
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static int Audio_i2s0_hdoutput_Get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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pr_debug("%s(), hdoutput_control = %d\n", __func__, hdoutput_control);
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ucontrol->value.integer.value[0] = hdoutput_control;
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return 0;
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}
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static int Audio_i2s0_hdoutput_Set(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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pr_debug("+%s()\n", __func__);
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if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(i2s0_HD_output)) {
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pr_err("return -EINVAL\n");
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return -EINVAL;
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}
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hdoutput_control = ucontrol->value.integer.value[0];
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/*
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if (hdoutput_control) {
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EnableApll1(true);
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EnableApll2(true);
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EnableI2SDivPower(AUDIO_APLL1_DIV0, true);
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EnableI2SDivPower(AUDIO_APLL2_DIV0, true);
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} else {
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EnableApll1(false);
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EnableApll2(false);
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EnableI2SDivPower(AUDIO_APLL1_DIV0, false);
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EnableI2SDivPower(AUDIO_APLL2_DIV0, false);
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}
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*/
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return 0;
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}
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static int Audio_i2s0_ExtCodec_EchoRef_Get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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pr_debug("%s(), extcodec_echoref_control = %d\n",
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__func__,
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extcodec_echoref_control);
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ucontrol->value.integer.value[0] = extcodec_echoref_control;
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return 0;
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}
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static int Audio_i2s0_ExtCodec_EchoRef_Set(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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pr_debug("%s()\n", __func__);
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if (ucontrol->value.enumerated.item[0] >
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ARRAY_SIZE(ExtCodec_EchoRef_Routing)) {
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pr_err("return -EINVAL\n");
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return -EINVAL;
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}
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extcodec_echoref_control = ucontrol->value.integer.value[0];
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return 0;
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}
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static const struct snd_kcontrol_new Audio_snd_i2s0_controls[] = {
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SOC_ENUM_EXT("Audio_i2s0_SideGen_Switch", Audio_i2s0_Enum[0],
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Audio_i2s0_SideGen_Get, Audio_i2s0_SideGen_Set),
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SOC_ENUM_EXT("Audio_i2s0_hd_Switch", Audio_i2s0_Enum[1],
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Audio_i2s0_hdoutput_Get, Audio_i2s0_hdoutput_Set),
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SOC_ENUM_EXT("Audio_always_hd_Switch", Audio_i2s0_Enum[1],
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audio_always_hd_get, audio_always_hd_set),
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SOC_ENUM_EXT("Audio_ExtCodec_EchoRef_Switch", Audio_i2s0_Enum[2],
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Audio_i2s0_ExtCodec_EchoRef_Get,
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Audio_i2s0_ExtCodec_EchoRef_Set),
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};
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static struct snd_pcm_hardware mtk_i2s0_hardware = {
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.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
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.formats = Dl1_MAX_BUFFER_SIZE,
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.rates = SOC_HIGH_USE_RATE,
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.rate_min = SOC_HIGH_USE_RATE_MIN,
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.rate_max = SOC_HIGH_USE_RATE_MAX,
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.channels_min = SOC_NORMAL_USE_CHANNELS_MIN,
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.channels_max = SOC_NORMAL_USE_CHANNELS_MAX,
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.buffer_bytes_max = Dl1_MAX_BUFFER_SIZE,
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.period_bytes_max = Dl1_MAX_BUFFER_SIZE,
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.periods_min = SOC_NORMAL_USE_PERIODS_MIN,
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.periods_max = SOC_NORMAL_USE_PERIODS_MAX,
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.fifo_size = 0,
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};
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static int mtk_pcm_i2s0_stop(struct snd_pcm_substream *substream)
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{
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struct afe_block_t *Afe_Block = &(pI2s0MemControl->rBlock);
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pr_debug("%s()\n", __func__);
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irq_remove_user(substream,
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irq_request_number(Soc_Aud_Digital_Block_MEM_DL1));
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/* here start digital part */
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SetIntfConnection(Soc_Aud_InterCon_DisConnect,
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Soc_Aud_AFE_IO_Block_MEM_DL1,
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Soc_Aud_AFE_IO_Block_I2S3);
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SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, false);
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/* stop I2S */
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Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1);
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EnableAfe(false);
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/* clean audio hardware buffer */
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memset_io(Afe_Block->pucVirtBufAddr, 0, Afe_Block->u4BufferSize);
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RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream);
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return 0;
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}
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static snd_pcm_uframes_t
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mtk_pcm_i2s0_pointer(struct snd_pcm_substream *substream)
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{
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return get_mem_frame_index(substream, pI2s0MemControl,
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Soc_Aud_Digital_Block_MEM_DL1);
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}
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|
|
|
static int mtk_pcm_i2s0_hw_params(struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *hw_params)
|
|
{
|
|
int ret = 0;
|
|
#if defined(AUD_DEBUG_LOG)
|
|
pr_debug("mtk_pcm_hw_params\n");
|
|
#endif
|
|
/* runtime->dma_bytes has to be set manually to allow mmap */
|
|
substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
|
|
|
|
/* here to allcoate sram to hardware --------------------------- */
|
|
AudDrv_Allocate_mem_Buffer(mDev, Soc_Aud_Digital_Block_MEM_DL1,
|
|
substream->runtime->dma_bytes);
|
|
substream->runtime->dma_area =
|
|
(unsigned char *)Get_Afe_SramBase_Pointer();
|
|
substream->runtime->dma_addr = AFE_INTERNAL_SRAM_PHY_BASE;
|
|
SetHighAddr(Soc_Aud_Digital_Block_MEM_DL1, false,
|
|
substream->runtime->dma_addr);
|
|
AudDrv_Emi_Clk_On();
|
|
|
|
/* ------------------------------------------------------- */
|
|
#if defined(AUD_DEBUG_LOG)
|
|
pr_debug("1 dma_bytes = %zu dma_area = %p dma_addr = 0x%lx\n",
|
|
substream->runtime->dma_bytes,
|
|
substream->runtime->dma_area,
|
|
(long)substream->runtime->dma_addr);
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
static int mtk_pcm_i2s0_hw_free(struct snd_pcm_substream *substream)
|
|
{
|
|
AudDrv_Emi_Clk_Off();
|
|
return 0;
|
|
}
|
|
|
|
static struct snd_pcm_hw_constraint_list constraints_sample_rates = {
|
|
.count = ARRAY_SIZE(soc_high_supported_sample_rates),
|
|
.list = soc_high_supported_sample_rates,
|
|
.mask = 0,
|
|
};
|
|
|
|
static unsigned int mPlaybackDramState;
|
|
static int mtk_pcm_i2s0_open(struct snd_pcm_substream *substream)
|
|
{
|
|
int ret = 0;
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
|
|
AfeControlSramLock();
|
|
if (GetSramState() == SRAM_STATE_FREE) {
|
|
mtk_i2s0_hardware.buffer_bytes_max = GetPLaybackSramFullSize();
|
|
mPlaybackDramState = SRAM_STATE_PLAYBACKFULL;
|
|
SetSramState(mPlaybackDramState);
|
|
} else {
|
|
mtk_i2s0_hardware.buffer_bytes_max = GetPLaybackSramPartial();
|
|
mPlaybackDramState = SRAM_STATE_PLAYBACKPARTIAL;
|
|
SetSramState(mPlaybackDramState);
|
|
}
|
|
AfeControlSramUnLock();
|
|
runtime->hw = mtk_i2s0_hardware;
|
|
|
|
AudDrv_Clk_On();
|
|
memcpy((void *)(&(runtime->hw)), (void *)&mtk_i2s0_hardware,
|
|
sizeof(struct snd_pcm_hardware));
|
|
pI2s0MemControl = Get_Mem_ControlT(Soc_Aud_Digital_Block_MEM_DL1);
|
|
|
|
ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
|
|
&constraints_sample_rates);
|
|
ret = snd_pcm_hw_constraint_integer(runtime,
|
|
SNDRV_PCM_HW_PARAM_PERIODS);
|
|
|
|
/* print for hw pcm information */
|
|
pr_debug(
|
|
"%s(), runtime rate = %d, channels = %d, substream->pcm->device = %d\n",
|
|
__func__, runtime->rate, runtime->channels, substream->pcm->device);
|
|
|
|
if (ret < 0) {
|
|
pr_err("mtk_pcm_i2s0_close\n");
|
|
mtk_pcm_i2s0_close(substream);
|
|
return ret;
|
|
}
|
|
pr_debug("%s(), return\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_pcm_i2s0_close(struct snd_pcm_substream *substream)
|
|
{
|
|
pr_debug("%s\n", __func__);
|
|
AfeControlSramLock();
|
|
ClearSramState(mPlaybackDramState);
|
|
mPlaybackDramState = GetSramState();
|
|
AfeControlSramUnLock();
|
|
AudDrv_Clk_Off();
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_pcm_i2s0_prepare(struct snd_pcm_substream *substream)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_pcm_i2s0_start(struct snd_pcm_substream *substream)
|
|
{
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
unsigned int u32AudioI2S = 0;
|
|
|
|
SetMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream);
|
|
if (runtime->format == SNDRV_PCM_FORMAT_S32_LE ||
|
|
runtime->format == SNDRV_PCM_FORMAT_S32_LE) {
|
|
SetMemIfFetchFormatPerSample(
|
|
Soc_Aud_Digital_Block_MEM_DL1,
|
|
AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA);
|
|
} else {
|
|
SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1,
|
|
AFE_WLEN_16_BIT);
|
|
}
|
|
|
|
SetConnectionFormat(OUTPUT_DATA_FORMAT_16BIT,
|
|
Soc_Aud_AFE_IO_Block_I2S3);
|
|
|
|
/* here start digital part */
|
|
SetIntfConnection(Soc_Aud_InterCon_Connection,
|
|
Soc_Aud_AFE_IO_Block_MEM_DL1,
|
|
Soc_Aud_AFE_IO_Block_I2S3);
|
|
|
|
u32AudioI2S = SampleRateTransform(runtime->rate,
|
|
Soc_Aud_Digital_Block_I2S_OUT_2)
|
|
<< 8;
|
|
u32AudioI2S |= Soc_Aud_I2S_FORMAT_I2S << 3; /* us3 I2s format */
|
|
u32AudioI2S |= Soc_Aud_I2S_WLEN_WLEN_16BITS << 1; /* 16 BITS */
|
|
|
|
if (hdoutput_control)
|
|
u32AudioI2S |= Soc_Aud_LOW_JITTER_CLOCK
|
|
<< 12; /* Low jitter mode */
|
|
|
|
Afe_Set_Reg(AFE_I2S_CON3, u32AudioI2S | 1, AFE_MASK_ALL);
|
|
|
|
SetSampleRate(Soc_Aud_Digital_Block_MEM_DL1, runtime->rate);
|
|
SetChannels(Soc_Aud_Digital_Block_MEM_DL1, runtime->channels);
|
|
SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, true);
|
|
|
|
/* here to set interrupt */
|
|
irq_add_user(substream,
|
|
irq_request_number(Soc_Aud_Digital_Block_MEM_DL1),
|
|
substream->runtime->rate, substream->runtime->period_size);
|
|
|
|
EnableAfe(true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_pcm_i2s0_trigger(struct snd_pcm_substream *substream, int cmd)
|
|
{
|
|
pr_debug("%s(), cmd = %d\n", __func__, cmd);
|
|
|
|
switch (cmd) {
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
return mtk_pcm_i2s0_start(substream);
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
return mtk_pcm_i2s0_stop(substream);
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int mtk_pcm_i2s0_copy(struct snd_pcm_substream *substream, int channel,
|
|
unsigned long pos, void __user *dst,
|
|
unsigned long count)
|
|
{
|
|
return mtk_memblk_copy(substream, channel, pos, dst, count,
|
|
pI2s0MemControl, Soc_Aud_Digital_Block_MEM_DL1);
|
|
}
|
|
|
|
static int mtk_pcm_i2s0_silence(struct snd_pcm_substream *substream,
|
|
int channel,
|
|
unsigned long pos,
|
|
unsigned long bytes)
|
|
{
|
|
return 0; /* do nothing */
|
|
}
|
|
|
|
static void *dummy_page[2];
|
|
|
|
static struct page *mtk_i2s0_pcm_page(struct snd_pcm_substream *substream,
|
|
unsigned long offset)
|
|
{
|
|
return virt_to_page(dummy_page[substream->stream]); /* the same page */
|
|
}
|
|
|
|
static struct snd_pcm_ops mtk_i2s0_ops = {
|
|
.open = mtk_pcm_i2s0_open,
|
|
.close = mtk_pcm_i2s0_close,
|
|
.ioctl = snd_pcm_lib_ioctl,
|
|
.hw_params = mtk_pcm_i2s0_hw_params,
|
|
.hw_free = mtk_pcm_i2s0_hw_free,
|
|
.prepare = mtk_pcm_i2s0_prepare,
|
|
.trigger = mtk_pcm_i2s0_trigger,
|
|
.pointer = mtk_pcm_i2s0_pointer,
|
|
.copy_user = mtk_pcm_i2s0_copy,
|
|
.fill_silence = mtk_pcm_i2s0_silence,
|
|
.page = mtk_i2s0_pcm_page,
|
|
};
|
|
|
|
static const struct snd_soc_component_driver mtk_i2s0_soc_component = {
|
|
.name = AFE_PCM_NAME,
|
|
.ops = &mtk_i2s0_ops,
|
|
.probe = mtk_afe_i2s0_component_probe,
|
|
};
|
|
|
|
static int mtk_i2s0_probe(struct platform_device *pdev)
|
|
{
|
|
pr_debug("%s\n", __func__);
|
|
|
|
pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
|
|
if (!pdev->dev.dma_mask)
|
|
pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
|
|
|
|
if (pdev->dev.of_node)
|
|
dev_set_name(&pdev->dev, "%s", MT_SOC_I2S0_PCM);
|
|
pdev->name = pdev->dev.kobj.name;
|
|
|
|
pr_debug("%s: dev name %s\n", __func__, dev_name(&pdev->dev));
|
|
|
|
mDev = &pdev->dev;
|
|
|
|
return snd_soc_register_component(&pdev->dev,
|
|
&mtk_i2s0_soc_component,
|
|
NULL,
|
|
0);
|
|
}
|
|
|
|
static int mtk_afe_i2s0_component_probe(struct snd_soc_component *component)
|
|
{
|
|
pr_debug("%s\n", __func__);
|
|
snd_soc_add_component_controls(component, Audio_snd_i2s0_controls,
|
|
ARRAY_SIZE(Audio_snd_i2s0_controls));
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_i2s0_remove(struct platform_device *pdev)
|
|
{
|
|
snd_soc_unregister_component(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id mt_soc_pcm_dl1_i2s0_of_ids[] = {
|
|
{
|
|
.compatible = "mediatek,mt_soc_pcm_dl1_i2s0",
|
|
},
|
|
{} };
|
|
#endif
|
|
|
|
static struct platform_driver mtk_i2s0_driver = {
|
|
.driver = {
|
|
|
|
.name = MT_SOC_I2S0_PCM,
|
|
.owner = THIS_MODULE,
|
|
#ifdef CONFIG_OF
|
|
.of_match_table = mt_soc_pcm_dl1_i2s0_of_ids,
|
|
#endif
|
|
},
|
|
.probe = mtk_i2s0_probe,
|
|
.remove = mtk_i2s0_remove,
|
|
};
|
|
|
|
#ifndef CONFIG_OF
|
|
static struct platform_device *soc_mtki2s0_dev;
|
|
#endif
|
|
|
|
static int __init mtk_i2s0_soc_platform_init(void)
|
|
{
|
|
int ret;
|
|
|
|
pr_debug("%s\n", __func__);
|
|
#ifndef CONFIG_OF
|
|
soc_mtki2s0_dev = platform_device_alloc(MT_SOC_I2S0_PCM, -1);
|
|
if (!soc_mtki2s0_dev)
|
|
return -ENOMEM;
|
|
|
|
ret = platform_device_add(soc_mtki2s0_dev);
|
|
if (ret != 0) {
|
|
platform_device_put(soc_mtki2s0_dev);
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
ret = platform_driver_register(&mtk_i2s0_driver);
|
|
return ret;
|
|
}
|
|
module_init(mtk_i2s0_soc_platform_init);
|
|
|
|
static void __exit mtk_i2s0_soc_platform_exit(void)
|
|
{
|
|
platform_driver_unregister(&mtk_i2s0_driver);
|
|
}
|
|
module_exit(mtk_i2s0_soc_platform_exit);
|
|
|
|
MODULE_DESCRIPTION("AFE PCM module platform driver");
|
|
MODULE_LICENSE("GPL");
|